x86: I/O APIC: keep the timer IRQ masked during set-up
Keep the timer interrupt line masked when reconfiguring its interrupt redirection entry in the I/O APIC. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -1316,7 +1316,7 @@ static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
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* to the first CPU.
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* to the first CPU.
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*/
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*/
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entry.dest_mode = INT_DEST_MODE;
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entry.dest_mode = INT_DEST_MODE;
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entry.mask = 0; /* unmask IRQ now */
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entry.mask = 1; /* mask IRQ now */
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entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
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entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
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entry.delivery_mode = INT_DELIVERY_MODE;
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entry.delivery_mode = INT_DELIVERY_MODE;
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entry.polarity = 0;
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entry.polarity = 0;
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@ -911,7 +911,7 @@ static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
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* to the first CPU.
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* to the first CPU.
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*/
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*/
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entry.dest_mode = INT_DEST_MODE;
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entry.dest_mode = INT_DEST_MODE;
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entry.mask = 0; /* unmask IRQ now */
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entry.mask = 1; /* mask IRQ now */
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entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
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entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
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entry.delivery_mode = INT_DELIVERY_MODE;
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entry.delivery_mode = INT_DELIVERY_MODE;
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entry.polarity = 0;
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entry.polarity = 0;
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