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MIPS: perf events: handle switch statement falling through warnings 

Now that we build with -Wimplicit-fallthrough=3, some warnings are
produced in the arch/mips perf events code that are promoted to errors:

 arch/mips/kernel/perf_event_mipsxx.c:792:3: error: this statement may fall through [-Werror=implicit-fallthrough=]
 arch/mips/kernel/perf_event_mipsxx.c:795:3: error: this statement may fall through [-Werror=implicit-fallthrough=]
 arch/mips/kernel/perf_event_mipsxx.c:798:3: error: this statement may fall through [-Werror=implicit-fallthrough=]
 arch/mips/kernel/perf_event_mipsxx.c:1407:6: error: this statement may fall through [-Werror=implicit-fallthrough=]

Assume the fall throughs are deliberate amd annotate/eliminate them.

Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Gustavo A. R. Silva <gustavo@embeddedor.com>
Cc: Kees Cook <keescook@chromium.org>
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
[paul.burton@mips.com:
  - Make n signed to fix the loop condition.
  - Simplify the initialization of n, which should never have a value
    greater than 4.
  - Invert conditions in the loop to decrease indentation.]
Signed-off-by: Paul Burton <paul.burton@mips.com>
This commit is contained in:
Stephen Rothwell 2019-07-15 11:55:04 +01:00 committed by Paul Burton
parent c9093486f2
commit 03bcba73cb
No known key found for this signature in database
GPG Key ID: 3EA79FACB57500DD
1 changed files with 15 additions and 15 deletions
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30
arch/mips/kernel/perf_event_mipsxx.c
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@ -793,15 +793,19 @@ static void reset_counters(void *arg)
case 4:
mipsxx_pmu_write_control(3, 0);
mipspmu.write_counter(3, 0);
/* fall through */
case 3:
mipsxx_pmu_write_control(2, 0);
mipspmu.write_counter(2, 0);
/* fall through */
case 2:
mipsxx_pmu_write_control(1, 0);
mipspmu.write_counter(1, 0);
/* fall through */
case 1:
mipsxx_pmu_write_control(0, 0);
mipspmu.write_counter(0, 0);
/* fall through */
}
}
@ -1383,7 +1387,7 @@ static int mipsxx_pmu_handle_shared_irq(void)
struct perf_sample_data data;
unsigned int counters = mipspmu.num_counters;
u64 counter;
int handled = IRQ_NONE;
int n, handled = IRQ_NONE;
struct pt_regs *regs;
if (cpu_has_perf_cntr_intr_bit && !(read_c0_cause() & CAUSEF_PCI))
@ -1404,20 +1408,16 @@ static int mipsxx_pmu_handle_shared_irq(void)
perf_sample_data_init(&data, 0, 0);
switch (counters) {
#define HANDLE_COUNTER(n) \
case n + 1: \
if (test_bit(n, cpuc->used_mask)) { \
counter = mipspmu.read_counter(n); \
if (counter & mipspmu.overflow) { \
handle_associated_event(cpuc, n, &data, regs); \
handled = IRQ_HANDLED; \
} \
}
HANDLE_COUNTER(3)
HANDLE_COUNTER(2)
HANDLE_COUNTER(1)
HANDLE_COUNTER(0)
for (n = counters - 1; n >= 0; n--) {
if (!test_bit(n, cpuc->used_mask))
continue;
counter = mipspmu.read_counter(n);
if (!(counter & mipspmu.overflow))
continue;
handle_associated_event(cpuc, n, &data, regs);
handled = IRQ_HANDLED;
}
#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS