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drm/i915/gen9+: Use the watermarks from crtc_state for everything, v2. 

There's no need to keep a duplicate skl_pipe_wm around any more,
everything can be discovered from crtc_state, which we pass around
correctly now even in case of plane disable.

The copy in intel_crtc->wm.skl.active is equal to
crtc_state->wm.skl.optimal after the atomic commit completes.
It's useful for two-step watermark programming, but not required for
gen9+ which does it in a single step. We can pull the old allocation
from old_crtc_state.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1477489299-25777-9-git-send-email-maarten.lankhorst@linux.intel.com
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
This commit is contained in:
Maarten Lankhorst 2016-10-26 15:41:36 +02:00
parent 49845a7aff
commit 03af79e0b8
3 changed files with 9 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/i915/intel_display.c
View File

@ -13458,7 +13458,7 @@ static void verify_wm_state(struct drm_crtc *crtc,
return;
skl_pipe_wm_get_hw_state(crtc, &hw_wm);
sw_wm = &intel_crtc->wm.active.skl;
sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
skl_ddb_get_hw_state(dev_priv, &hw_ddb);
sw_ddb = &dev_priv->wm.skl_hw.ddb;

1
drivers/gpu/drm/i915/intel_drv.h
View File

@ -722,7 +722,6 @@ struct intel_crtc {
/* watermarks currently being used */
union {
struct intel_pipe_wm ilk;
struct skl_pipe_wm skl;
} active;
/* allow CxSR on this pipe */

18
drivers/gpu/drm/i915/intel_pm.c
View File

@ -3930,11 +3930,11 @@ bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
}
static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
struct skl_ddb_allocation *ddb, /* out */
const struct skl_pipe_wm *old_pipe_wm,
struct skl_pipe_wm *pipe_wm, /* out */
struct skl_ddb_allocation *ddb, /* out */
bool *changed /* out */)
{
struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
int ret;
@ -3942,7 +3942,7 @@ static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
if (ret)
return ret;
if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
*changed = false;
else
*changed = true;
@ -4169,10 +4169,12 @@ skl_compute_wm(struct drm_atomic_state *state)
for_each_crtc_in_state(state, crtc, cstate, i) {
struct intel_crtc_state *intel_cstate =
to_intel_crtc_state(cstate);
const struct skl_pipe_wm *old_pipe_wm =
&to_intel_crtc_state(crtc->state)->wm.skl.optimal;
pipe_wm = &intel_cstate->wm.skl.optimal;
ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
&changed);
ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
&results->ddb, &changed);
if (ret)
return ret;
@ -4205,8 +4207,6 @@ static void skl_update_wm(struct drm_crtc *crtc)
if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
return;
intel_crtc->wm.active.skl = *pipe_wm;
mutex_lock(&dev_priv->wm.wm_mutex);
/*
@ -4374,10 +4374,8 @@ void skl_wm_get_hw_state(struct drm_device *dev)
skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
if (intel_crtc->active) {
if (intel_crtc->active)
hw->dirty_pipes |= drm_crtc_mask(crtc);
intel_crtc->wm.active.skl = cstate->wm.skl.optimal;
}
}
if (dev_priv->active_crtcs) {