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media: rkisp1: csi: Handle CSI-2 RX configuration fully in rkisp1-csi.c 

The ISP layer now calls multiple functions of the CSI-2 RX layer to
configure, start and stop it, with the steps for the last two
operations. Move those calls to rkisp1_mipi_csi2_start() and
rkisp1_mipi_csi2_stop() to simplify the ISP code and the API exposed by
the CSI-2 receiver component.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Dafna Hirschfeld <dafna@fastmail.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
This commit is contained in:
Laurent Pinchart 2022-06-14 20:10:52 +01:00 committed by Mauro Carvalho Chehab
parent 4fd1e6a9ab
commit 039a73427b
3 changed files with 35 additions and 38 deletions
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59
drivers/media/platform/rockchip/rkisp1/rkisp1-csi.c
View File

@ -18,7 +18,7 @@
#include "rkisp1-common.h"
#include "rkisp1-csi.h"
int rkisp1_config_mipi(struct rkisp1_csi *csi)
static int rkisp1_config_mipi(struct rkisp1_csi *csi)
{
struct rkisp1_device *rkisp1 = csi->rkisp1;
const struct rkisp1_mbus_info *sink_fmt = rkisp1->isp.sink_fmt;
@ -69,6 +69,30 @@ int rkisp1_config_mipi(struct rkisp1_csi *csi)
return 0;
}
static void rkisp1_mipi_start(struct rkisp1_csi *csi)
{
struct rkisp1_device *rkisp1 = csi->rkisp1;
u32 val;
val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL);
rkisp1_write(rkisp1, RKISP1_CIF_MIPI_CTRL,
val | RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA);
}
static void rkisp1_mipi_stop(struct rkisp1_csi *csi)
{
struct rkisp1_device *rkisp1 = csi->rkisp1;
u32 val;
/* Mask and clear interrupts. */
rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMSC, 0);
rkisp1_write(rkisp1, RKISP1_CIF_MIPI_ICR, ~0);
val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL);
rkisp1_write(rkisp1, RKISP1_CIF_MIPI_CTRL,
val & (~RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA));
}
int rkisp1_mipi_csi2_start(struct rkisp1_csi *csi,
struct rkisp1_sensor_async *sensor)
{
@ -76,6 +100,11 @@ int rkisp1_mipi_csi2_start(struct rkisp1_csi *csi,
union phy_configure_opts opts;
struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy;
s64 pixel_clock;
int ret;
ret = rkisp1_config_mipi(csi);
if (ret)
return ret;
pixel_clock = v4l2_ctrl_g_ctrl_int64(sensor->pixel_rate_ctrl);
if (!pixel_clock) {
@ -90,38 +119,18 @@ int rkisp1_mipi_csi2_start(struct rkisp1_csi *csi,
phy_configure(csi->dphy, &opts);
phy_power_on(csi->dphy);
rkisp1_mipi_start(csi);
return 0;
}
void rkisp1_mipi_csi2_stop(struct rkisp1_csi *csi)
{
rkisp1_mipi_stop(csi);
phy_power_off(csi->dphy);
}
void rkisp1_mipi_start(struct rkisp1_csi *csi)
{
struct rkisp1_device *rkisp1 = csi->rkisp1;
u32 val;
val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL);
rkisp1_write(rkisp1, RKISP1_CIF_MIPI_CTRL,
val | RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA);
}
void rkisp1_mipi_stop(struct rkisp1_csi *csi)
{
struct rkisp1_device *rkisp1 = csi->rkisp1;
u32 val;
/* Mask and clear interrupts. */
rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMSC, 0);
rkisp1_write(rkisp1, RKISP1_CIF_MIPI_ICR, ~0);
val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL);
rkisp1_write(rkisp1, RKISP1_CIF_MIPI_CTRL,
val & (~RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA));
}
irqreturn_t rkisp1_mipi_isr(int irq, void *ctx)
{
struct device *dev = ctx;

4
drivers/media/platform/rockchip/rkisp1/rkisp1-csi.h
View File

@ -18,12 +18,8 @@ struct rkisp1_sensor_async;
int rkisp1_csi_init(struct rkisp1_device *rkisp1);
void rkisp1_csi_cleanup(struct rkisp1_device *rkisp1);
int rkisp1_config_mipi(struct rkisp1_csi *csi);
int rkisp1_mipi_csi2_start(struct rkisp1_csi *csi,
struct rkisp1_sensor_async *sensor);
void rkisp1_mipi_csi2_stop(struct rkisp1_csi *csi);
void rkisp1_mipi_start(struct rkisp1_csi *csi);
void rkisp1_mipi_stop(struct rkisp1_csi *csi);
#endif /* _RKISP1_CSI_H */

10
drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
View File

@ -276,7 +276,6 @@ static int rkisp1_config_path(struct rkisp1_device *rkisp1)
ret = rkisp1_config_dvp(rkisp1);
dpcl |= RKISP1_CIF_VI_DPCL_IF_SEL_PARALLEL;
} else if (sensor->mbus_type == V4L2_MBUS_CSI2_DPHY) {
ret = rkisp1_config_mipi(&rkisp1->csi);
dpcl |= RKISP1_CIF_VI_DPCL_IF_SEL_MIPI;
}
@ -309,15 +308,13 @@ static void rkisp1_isp_stop(struct rkisp1_device *rkisp1)
* ISP(mi) stop in mi frame end -> Stop ISP(mipi) ->
* Stop ISP(isp) ->wait for ISP isp off
*/
/* stop and clear MI, MIPI, and ISP interrupts */
/* stop and clear MI and ISP interrupts */
rkisp1_write(rkisp1, RKISP1_CIF_ISP_IMSC, 0);
rkisp1_write(rkisp1, RKISP1_CIF_ISP_ICR, ~0);
rkisp1_write(rkisp1, RKISP1_CIF_MI_IMSC, 0);
rkisp1_write(rkisp1, RKISP1_CIF_MI_ICR, ~0);
rkisp1_mipi_stop(&rkisp1->csi);
/* stop ISP */
val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL);
val &= ~(RKISP1_CIF_ISP_CTRL_ISP_INFORM_ENABLE |
@ -358,15 +355,10 @@ static void rkisp1_config_clk(struct rkisp1_device *rkisp1)
static void rkisp1_isp_start(struct rkisp1_device *rkisp1)
{
struct rkisp1_sensor_async *sensor = rkisp1->active_sensor;
u32 val;
rkisp1_config_clk(rkisp1);
/* Activate MIPI */
if (sensor->mbus_type == V4L2_MBUS_CSI2_DPHY)
rkisp1_mipi_start(&rkisp1->csi);
/* Activate ISP */
val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL);
val |= RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD |