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PCI: qcom-ep: Disable Master AXI Clock when there is no PCIe traffic 

The Master AXI clock can be disabled when it is not used i.e., when there
is no traffic on the PCIe bus. This helps to save power during idle state.

[bhelgaas: tidy and wrap comment]
Link: https://lore.kernel.org/r/20220914075350.7992-8-manivannan.sadhasivam@linaro.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Manivannan Sadhasivam 2022-09-14 13:23:45 +05:30 committed by Bjorn Helgaas
parent c457ac029e
commit 0391632948
1 changed files with 8 additions and 1 deletions
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9
drivers/pci/controller/dwc/pcie-qcom-ep.c
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@ -105,6 +105,7 @@
/* PARF_SYS_CTRL register fields */
#define PARF_SYS_CTRL_AUX_PWR_DET BIT(4)
#define PARF_SYS_CTRL_CORE_CLK_CGC_DIS BIT(6)
#define PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS BIT(10)
#define PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE BIT(11)
/* PARF_DB_CTRL register fields */
@ -341,8 +342,14 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
val &= ~PARF_Q2A_FLUSH_EN;
writel_relaxed(val, pcie_ep->parf + PARF_Q2A_FLUSH);
/* Disable DBI Wakeup, core clock CGC and enable AUX power */
/*
* Disable Master AXI clock during idle. Do not allow DBI access
* to take the core out of L1. Disable core clock gating that
* gates PIPE clock from propagating to core clock. Report to the
* host that Vaux is present.
*/
val = readl_relaxed(pcie_ep->parf + PARF_SYS_CTRL);
val &= ~PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS;
val |= PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE |
PARF_SYS_CTRL_CORE_CLK_CGC_DIS |
PARF_SYS_CTRL_AUX_PWR_DET;