ath5k: review and add comments for descriptors
I carefully reviewed desh.h against the HAL sources. Added comments and made differences between 5210, 5211 and 5212 more clear by adding _521x to the defines which are specific to that chipset. Renamed some defines. No functional changes. Signed-off-by: Bruno Randolf <br1@einfach.org> Acked-by: Bob Copeland <me@bobcopeland.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Bruno Randolf
John W. Linville
parent
62412a8f0d
commit
03417bc605
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@ -95,10 +95,10 @@ ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
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* XXX: I only found that on 5210 code, does it work on 5211 ?
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*/
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if (ah->ah_version == AR5K_AR5210) {
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if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN)
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if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210)
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return -EINVAL;
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tx_ctl->tx_control_0 |=
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AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN);
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AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210);
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}
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/*Differences between 5210-5211*/
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@ -114,7 +114,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
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}
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tx_ctl->tx_control_0 |=
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AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE) |
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AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_5210) |
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AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
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} else {
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@ -123,7 +123,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
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AR5K_REG_SM(antenna_mode,
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AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT);
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tx_ctl->tx_control_1 |=
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AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE);
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AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_5211);
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}
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#define _TX_FLAGS(_c, _flag) \
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if (flags & AR5K_TXDESC_##_flag) { \
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@ -147,7 +147,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
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AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
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tx_ctl->tx_control_1 |=
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AR5K_REG_SM(key_index,
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AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
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AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX);
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}
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/*
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@ -156,7 +156,7 @@ ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
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if ((ah->ah_version == AR5K_AR5210) &&
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(flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
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tx_ctl->tx_control_1 |= rtscts_duration &
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AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
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AR5K_2W_TX_DESC_CTL1_RTS_DURATION_5210;
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return 0;
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}
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@ -255,7 +255,7 @@ static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
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if (key_index != AR5K_TXKEYIX_INVALID) {
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tx_ctl->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
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tx_ctl->tx_control_1 |= AR5K_REG_SM(key_index,
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AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
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AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_IDX);
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}
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/*
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@ -409,11 +409,11 @@ static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
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ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
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AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
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ts->ts_antenna = (tx_status->tx_status_1 &
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AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1;
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AR5K_DESC_TX_STATUS1_XMIT_ANTENNA_5212) ? 2 : 1;
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ts->ts_status = 0;
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ts->ts_final_idx = AR5K_REG_MS(tx_status->tx_status_1,
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AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX);
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AR5K_DESC_TX_STATUS1_FINAL_TS_IX_5212);
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/* The longretry counter has the number of un-acked retries
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* for the final rate. To get the total number of retries
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@ -527,7 +527,7 @@ static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
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rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
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AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE);
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rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0,
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AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA);
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AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5211);
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rs->rs_more = !!(rx_status->rx_status_0 &
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AR5K_5210_RX_DESC_STATUS0_MORE);
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/* TODO: this timestamp is 13 bit, later on we assume 15 bit */
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@ -555,7 +555,7 @@ static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
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rs->rs_status |= AR5K_RXERR_CRC;
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if (rx_status->rx_status_1 &
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AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN)
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AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN_5210)
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rs->rs_status |= AR5K_RXERR_FIFO;
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if (rx_status->rx_status_1 &
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@ -17,28 +17,24 @@
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*/
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/*
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* Internal RX/TX descriptor structures
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* (rX: reserved fields possibily used by future versions of the ar5k chipset)
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* RX/TX descriptor structures
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*/
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/*
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* common hardware RX control descriptor
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* Common hardware RX control descriptor
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*/
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struct ath5k_hw_rx_ctl {
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u32 rx_control_0; /* RX control word 0 */
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u32 rx_control_1; /* RX control word 1 */
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} __packed;
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/* RX control word 0 field/sflags */
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#define AR5K_DESC_RX_CTL0 0x00000000
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/* RX control word 1 fields/flags */
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#define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff
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#define AR5K_DESC_RX_CTL1_INTREQ 0x00002000
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#define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff /* data buffer length */
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#define AR5K_DESC_RX_CTL1_INTREQ 0x00002000 /* RX interrupt request */
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/*
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* common hardware RX status descriptor
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* 5210/11 and 5212 differ only in the flags defined below
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* Common hardware RX status descriptor
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* 5210, 5211 and 5212 differ only in the fields and flags defined below
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*/
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struct ath5k_hw_rx_status {
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u32 rx_status_0; /* RX status word 0 */
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@ -47,68 +43,69 @@ struct ath5k_hw_rx_status {
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/* 5210/5211 */
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/* RX status word 0 fields/flags */
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#define AR5K_5210_RX_DESC_STATUS0_DATA_LEN 0x00000fff
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#define AR5K_5210_RX_DESC_STATUS0_MORE 0x00001000
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#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE 0x00078000
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#define AR5K_5210_RX_DESC_STATUS0_DATA_LEN 0x00000fff /* RX data length */
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#define AR5K_5210_RX_DESC_STATUS0_MORE 0x00001000 /* more desc for this frame */
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#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5210 0x00004000 /* [5210] receive on ant 1 TODO */
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#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE 0x00078000 /* reception rate */
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#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE_S 15
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#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x07f80000
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#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x07f80000 /* rssi */
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#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 19
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#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA 0x38000000
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#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 27
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#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5211 0x38000000 /* [5211] receive antenna */
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#define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5211_S 27
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/* RX status word 1 fields/flags */
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#define AR5K_5210_RX_DESC_STATUS1_DONE 0x00000001
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#define AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002
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#define AR5K_5210_RX_DESC_STATUS1_CRC_ERROR 0x00000004
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#define AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN 0x00000008
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#define AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000010
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#define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR 0x000000e0
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#define AR5K_5210_RX_DESC_STATUS1_DONE 0x00000001 /* descriptor complete */
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#define AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 /* reception success */
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#define AR5K_5210_RX_DESC_STATUS1_CRC_ERROR 0x00000004 /* CRC error */
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#define AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN_5210 0x00000008 /* [5210] FIFO overrun */
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#define AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000010 /* decyption CRC failure */
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#define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR 0x000000e0 /* PHY error */
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#define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR_S 5
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#define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100
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#define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX 0x00007e00
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#define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 /* key index valid */
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#define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX 0x00007e00 /* decyption key index */
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#define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_S 9
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#define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000
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#define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000 /* 13 bit of TSF */
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#define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 15
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#define AR5K_5210_RX_DESC_STATUS1_KEY_CACHE_MISS 0x10000000
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#define AR5K_5210_RX_DESC_STATUS1_KEY_CACHE_MISS 0x10000000 /* key cache miss */
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/* 5212 */
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/* RX status word 0 fields/flags */
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#define AR5K_5212_RX_DESC_STATUS0_DATA_LEN 0x00000fff
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#define AR5K_5212_RX_DESC_STATUS0_MORE 0x00001000
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#define AR5K_5212_RX_DESC_STATUS0_DECOMP_CRC_ERROR 0x00002000
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#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE 0x000f8000
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#define AR5K_5212_RX_DESC_STATUS0_DATA_LEN 0x00000fff /* RX data length */
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#define AR5K_5212_RX_DESC_STATUS0_MORE 0x00001000 /* more desc for this frame */
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#define AR5K_5212_RX_DESC_STATUS0_DECOMP_CRC_ERROR 0x00002000 /* decompression CRC error */
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#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE 0x000f8000 /* reception rate */
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#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE_S 15
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#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x0ff00000
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#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x0ff00000 /* rssi */
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#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 20
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#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA 0xf0000000
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#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA 0xf0000000 /* receive antenna */
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#define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 28
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/* RX status word 1 fields/flags */
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#define AR5K_5212_RX_DESC_STATUS1_DONE 0x00000001
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#define AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002
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#define AR5K_5212_RX_DESC_STATUS1_CRC_ERROR 0x00000004
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#define AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000008
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#define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR 0x00000010
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#define AR5K_5212_RX_DESC_STATUS1_MIC_ERROR 0x00000020
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#define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100
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#define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX 0x0000fe00
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#define AR5K_5212_RX_DESC_STATUS1_DONE 0x00000001 /* descriptor complete */
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#define AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 /* frame reception success */
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#define AR5K_5212_RX_DESC_STATUS1_CRC_ERROR 0x00000004 /* CRC error */
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#define AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000008 /* decryption CRC failure */
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#define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR 0x00000010 /* PHY error */
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#define AR5K_5212_RX_DESC_STATUS1_MIC_ERROR 0x00000020 /* MIC decrypt error */
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#define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 /* key index valid */
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#define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX 0x0000fe00 /* decryption key index */
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#define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_S 9
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#define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000
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#define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000 /* first 15bit of the TSF */
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#define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 16
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#define AR5K_5212_RX_DESC_STATUS1_KEY_CACHE_MISS 0x80000000
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#define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR_CODE 0x0000ff00
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#define AR5K_5212_RX_DESC_STATUS1_KEY_CACHE_MISS 0x80000000 /* key cache miss */
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#define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR_CODE 0x0000ff00 /* phy error code overlays key index and valid fields */
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#define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR_CODE_S 8
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/**
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* enum ath5k_phy_error_code - PHY Error codes
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*/
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enum ath5k_phy_error_code {
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AR5K_RX_PHY_ERROR_UNDERRUN = 0, /* Transmit underrun */
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AR5K_RX_PHY_ERROR_UNDERRUN = 0, /* Transmit underrun, [5210] No error */
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AR5K_RX_PHY_ERROR_TIMING = 1, /* Timing error */
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AR5K_RX_PHY_ERROR_PARITY = 2, /* Illegal parity */
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AR5K_RX_PHY_ERROR_RATE = 3, /* Illegal rate */
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AR5K_RX_PHY_ERROR_LENGTH = 4, /* Illegal length */
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AR5K_RX_PHY_ERROR_RADAR = 5, /* Radar detect */
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AR5K_RX_PHY_ERROR_RADAR = 5, /* Radar detect, [5210] 64 QAM rate */
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AR5K_RX_PHY_ERROR_SERVICE = 6, /* Illegal service */
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AR5K_RX_PHY_ERROR_TOR = 7, /* Transmit override receive */
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/* these are specific to the 5212 */
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@ -135,45 +132,41 @@ struct ath5k_hw_2w_tx_ctl {
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} __packed;
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/* TX control word 0 fields/flags */
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#define AR5K_2W_TX_DESC_CTL0_FRAME_LEN 0x00000fff
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#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN 0x0003f000 /*[5210 ?]*/
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#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_S 12
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#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE 0x003c0000
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#define AR5K_2W_TX_DESC_CTL0_FRAME_LEN 0x00000fff /* frame length */
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#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210 0x0003f000 /* [5210] header length */
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#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210_S 12
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#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE 0x003c0000 /* tx rate */
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#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE_S 18
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#define AR5K_2W_TX_DESC_CTL0_RTSENA 0x00400000
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#define AR5K_2W_TX_DESC_CTL0_CLRDMASK 0x01000000
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#define AR5K_2W_TX_DESC_CTL0_LONG_PACKET 0x00800000 /*[5210]*/
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#define AR5K_2W_TX_DESC_CTL0_VEOL 0x00800000 /*[5211]*/
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#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE 0x1c000000 /*[5210]*/
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#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_S 26
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#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 0x02000000
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#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211 0x1e000000
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#define AR5K_2W_TX_DESC_CTL0_RTSENA 0x00400000 /* RTS/CTS enable */
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#define AR5K_2W_TX_DESC_CTL0_LONG_PACKET_5210 0x00800000 /* [5210] long packet */
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#define AR5K_2W_TX_DESC_CTL0_VEOL 0x00800000 /* [5211] virtual end-of-list TODO */
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#define AR5K_2W_TX_DESC_CTL0_CLRDMASK 0x01000000 /* clear destination mask */
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#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 0x02000000 /* [5210] antenna selection */
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#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211 0x1e000000 /* [5211] antenna selection */
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#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT \
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(ah->ah_version == AR5K_AR5210 ? \
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AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 : \
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AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211)
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#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25
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#define AR5K_2W_TX_DESC_CTL0_INTREQ 0x20000000
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#define AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000
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#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_5210 0x1c000000 /* [5210] frame type */
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#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_5210_S 26
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#define AR5K_2W_TX_DESC_CTL0_INTREQ 0x20000000 /* TX interrupt request */
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#define AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 /* key is valid */
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/* TX control word 1 fields/flags */
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#define AR5K_2W_TX_DESC_CTL1_BUF_LEN 0x00000fff
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#define AR5K_2W_TX_DESC_CTL1_MORE 0x00001000
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#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 0x0007e000
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#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211 0x000fe000
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#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX \
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#define AR5K_2W_TX_DESC_CTL1_BUF_LEN 0x00000fff /* data buffer length */
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#define AR5K_2W_TX_DESC_CTL1_MORE 0x00001000 /* more desc for this frame */
|
||||
#define AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_5210 0x0007e000 /* [5210] key table index */
|
||||
#define AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_5211 0x000fe000 /* [5211] key table index */
|
||||
#define AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX \
|
||||
(ah->ah_version == AR5K_AR5210 ? \
|
||||
AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 : \
|
||||
AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211)
|
||||
|
||||
#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13
|
||||
#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE 0x00700000 /*[5211]*/
|
||||
#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_S 20
|
||||
#define AR5K_2W_TX_DESC_CTL1_NOACK 0x00800000 /*[5211]*/
|
||||
#define AR5K_2W_TX_DESC_CTL1_RTS_DURATION 0xfff80000 /*[5210 ?]*/
|
||||
AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_5210 : \
|
||||
AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_5211)
|
||||
#define AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_S 13
|
||||
#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_5211 0x00700000 /* [5211] frame type */
|
||||
#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_5211_S 20
|
||||
#define AR5K_2W_TX_DESC_CTL1_NOACK 0x00800000 /* [5211] no ACK TODO */
|
||||
#define AR5K_2W_TX_DESC_CTL1_RTS_DURATION_5210 0xfff80000 /* [5210] lower 13 bit of duration */
|
||||
|
||||
/* Frame types */
|
||||
#define AR5K_AR5210_TX_DESC_FRAME_TYPE_NORMAL 0x00
|
||||
|
|
@ -187,60 +180,61 @@ struct ath5k_hw_2w_tx_ctl {
|
|||
*/
|
||||
struct ath5k_hw_4w_tx_ctl {
|
||||
u32 tx_control_0; /* TX control word 0 */
|
||||
|
||||
#define AR5K_4W_TX_DESC_CTL0_FRAME_LEN 0x00000fff
|
||||
#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER 0x003f0000
|
||||
#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER_S 16
|
||||
#define AR5K_4W_TX_DESC_CTL0_RTSENA 0x00400000
|
||||
#define AR5K_4W_TX_DESC_CTL0_VEOL 0x00800000
|
||||
#define AR5K_4W_TX_DESC_CTL0_CLRDMASK 0x01000000
|
||||
#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT 0x1e000000
|
||||
#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25
|
||||
#define AR5K_4W_TX_DESC_CTL0_INTREQ 0x20000000
|
||||
#define AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000
|
||||
#define AR5K_4W_TX_DESC_CTL0_CTSENA 0x80000000
|
||||
|
||||
u32 tx_control_1; /* TX control word 1 */
|
||||
u32 tx_control_2; /* TX control word 2 */
|
||||
u32 tx_control_3; /* TX control word 3 */
|
||||
} __packed;
|
||||
|
||||
#define AR5K_4W_TX_DESC_CTL1_BUF_LEN 0x00000fff
|
||||
#define AR5K_4W_TX_DESC_CTL1_MORE 0x00001000
|
||||
#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX 0x000fe000
|
||||
#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13
|
||||
#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE 0x00f00000
|
||||
/* TX control word 0 fields/flags */
|
||||
#define AR5K_4W_TX_DESC_CTL0_FRAME_LEN 0x00000fff /* frame length */
|
||||
#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER 0x003f0000 /* transmit power */
|
||||
#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER_S 16
|
||||
#define AR5K_4W_TX_DESC_CTL0_RTSENA 0x00400000 /* RTS/CTS enable */
|
||||
#define AR5K_4W_TX_DESC_CTL0_VEOL 0x00800000 /* virtual end-of-list */
|
||||
#define AR5K_4W_TX_DESC_CTL0_CLRDMASK 0x01000000 /* clear destination mask */
|
||||
#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT 0x1e000000 /* TX antenna selection */
|
||||
#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25
|
||||
#define AR5K_4W_TX_DESC_CTL0_INTREQ 0x20000000 /* TX interrupt request */
|
||||
#define AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 /* destination index valid */
|
||||
#define AR5K_4W_TX_DESC_CTL0_CTSENA 0x80000000 /* precede frame with CTS */
|
||||
|
||||
/* TX control word 1 fields/flags */
|
||||
#define AR5K_4W_TX_DESC_CTL1_BUF_LEN 0x00000fff /* data buffer length */
|
||||
#define AR5K_4W_TX_DESC_CTL1_MORE 0x00001000 /* more desc for this frame */
|
||||
#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_IDX 0x000fe000 /* destination table index */
|
||||
#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_IDX_S 13
|
||||
#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE 0x00f00000 /* frame type */
|
||||
#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE_S 20
|
||||
#define AR5K_4W_TX_DESC_CTL1_NOACK 0x01000000
|
||||
#define AR5K_4W_TX_DESC_CTL1_COMP_PROC 0x06000000
|
||||
#define AR5K_4W_TX_DESC_CTL1_NOACK 0x01000000 /* no ACK */
|
||||
#define AR5K_4W_TX_DESC_CTL1_COMP_PROC 0x06000000 /* compression processing */
|
||||
#define AR5K_4W_TX_DESC_CTL1_COMP_PROC_S 25
|
||||
#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN 0x18000000
|
||||
#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN 0x18000000 /* length of frame IV */
|
||||
#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN_S 27
|
||||
#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN 0x60000000
|
||||
#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN 0x60000000 /* length of frame ICV */
|
||||
#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN_S 29
|
||||
|
||||
u32 tx_control_2; /* TX control word 2 */
|
||||
/* TX control word 2 fields/flags */
|
||||
#define AR5K_4W_TX_DESC_CTL2_RTS_DURATION 0x00007fff /* RTS/CTS duration */
|
||||
#define AR5K_4W_TX_DESC_CTL2_DURATION_UPD_EN 0x00008000 /* frame duration update */
|
||||
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0 0x000f0000 /* series 0 max attempts */
|
||||
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0_S 16
|
||||
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1 0x00f00000 /* series 1 max attempts */
|
||||
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1_S 20
|
||||
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2 0x0f000000 /* series 2 max attempts */
|
||||
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2_S 24
|
||||
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3 0xf0000000 /* series 3 max attempts */
|
||||
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3_S 28
|
||||
|
||||
#define AR5K_4W_TX_DESC_CTL2_RTS_DURATION 0x00007fff
|
||||
#define AR5K_4W_TX_DESC_CTL2_DURATION_UPDATE_ENABLE 0x00008000
|
||||
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0 0x000f0000
|
||||
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0_S 16
|
||||
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1 0x00f00000
|
||||
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1_S 20
|
||||
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2 0x0f000000
|
||||
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2_S 24
|
||||
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3 0xf0000000
|
||||
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3_S 28
|
||||
|
||||
u32 tx_control_3; /* TX control word 3 */
|
||||
|
||||
#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 0x0000001f
|
||||
#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1 0x000003e0
|
||||
/* TX control word 3 fields/flags */
|
||||
#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 0x0000001f /* series 0 tx rate */
|
||||
#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1 0x000003e0 /* series 1 tx rate */
|
||||
#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1_S 5
|
||||
#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2 0x00007c00
|
||||
#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2 0x00007c00 /* series 2 tx rate */
|
||||
#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2_S 10
|
||||
#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3 0x000f8000
|
||||
#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3 0x000f8000 /* series 3 tx rate */
|
||||
#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3_S 15
|
||||
#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE 0x01f00000
|
||||
#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE 0x01f00000 /* RTS or CTS rate */
|
||||
#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S 20
|
||||
} __packed;
|
||||
|
||||
/*
|
||||
* Common TX status descriptor
|
||||
|
|
@ -251,37 +245,34 @@ struct ath5k_hw_tx_status {
|
|||
} __packed;
|
||||
|
||||
/* TX status word 0 fields/flags */
|
||||
#define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001
|
||||
#define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002
|
||||
#define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004
|
||||
#define AR5K_DESC_TX_STATUS0_FILTERED 0x00000008
|
||||
/*???
|
||||
#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT 0x000000f0
|
||||
#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT_S 4
|
||||
*/
|
||||
#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT 0x000000f0
|
||||
#define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001 /* TX success */
|
||||
#define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002 /* excessive retries */
|
||||
#define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004 /* FIFO underrun */
|
||||
#define AR5K_DESC_TX_STATUS0_FILTERED 0x00000008 /* TX filter indication */
|
||||
/* according to the HAL sources the spec has short/long retry counts reversed.
|
||||
* we have it reversed to the HAL sources as well, for 5210 and 5211.
|
||||
* For 5212 these fields are defined as RTS_FAIL_COUNT and DATA_FAIL_COUNT,
|
||||
* but used respectively as SHORT and LONG retry count in the code later. This
|
||||
* is consistent with the definitions here... TODO: check */
|
||||
#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT 0x000000f0 /* short retry count */
|
||||
#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S 4
|
||||
/*???
|
||||
#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT 0x00000f00
|
||||
#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT_S 8
|
||||
*/
|
||||
#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT 0x00000f00
|
||||
#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT 0x00000f00 /* long retry count */
|
||||
#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT_S 8
|
||||
#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT 0x0000f000
|
||||
#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT_S 12
|
||||
#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000
|
||||
#define AR5K_DESC_TX_STATUS0_VIRTCOLL_CT_5211 0x0000f000 /* [5211+] virtual collision count */
|
||||
#define AR5K_DESC_TX_STATUS0_VIRTCOLL_CT_5212_S 12
|
||||
#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000 /* TX timestamp */
|
||||
#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP_S 16
|
||||
|
||||
/* TX status word 1 fields/flags */
|
||||
#define AR5K_DESC_TX_STATUS1_DONE 0x00000001
|
||||
#define AR5K_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe
|
||||
#define AR5K_DESC_TX_STATUS1_DONE 0x00000001 /* descriptor complete */
|
||||
#define AR5K_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe /* TX sequence number */
|
||||
#define AR5K_DESC_TX_STATUS1_SEQ_NUM_S 1
|
||||
#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000
|
||||
#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000 /* signal strength of ACK */
|
||||
#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13
|
||||
#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX 0x00600000
|
||||
#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX_S 21
|
||||
#define AR5K_DESC_TX_STATUS1_COMP_SUCCESS 0x00800000
|
||||
#define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA 0x01000000
|
||||
#define AR5K_DESC_TX_STATUS1_FINAL_TS_IX_5212 0x00600000 /* [5212] final TX attempt series ix */
|
||||
#define AR5K_DESC_TX_STATUS1_FINAL_TS_IX_5212_S 21
|
||||
#define AR5K_DESC_TX_STATUS1_COMP_SUCCESS_5212 0x00800000 /* [5212] compression status */
|
||||
#define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA_5212 0x01000000 /* [5212] transmit antenna */
|
||||
|
||||
/*
|
||||
* 5210/5211 hardware TX descriptor
|
||||
|
|
@ -300,7 +291,7 @@ struct ath5k_hw_5212_tx_desc {
|
|||
} __packed;
|
||||
|
||||
/*
|
||||
* common hardware RX descriptor
|
||||
* Common hardware RX descriptor
|
||||
*/
|
||||
struct ath5k_hw_all_rx_desc {
|
||||
struct ath5k_hw_rx_ctl rx_ctl;
|
||||
|
|
@ -308,7 +299,7 @@ struct ath5k_hw_all_rx_desc {
|
|||
} __packed;
|
||||
|
||||
/*
|
||||
* Atheros hardware descriptor
|
||||
* Atheros hardware DMA descriptor
|
||||
* This is read and written to by the hardware
|
||||
*/
|
||||
struct ath5k_desc {
|
||||
|
|
@ -330,4 +321,3 @@ struct ath5k_desc {
|
|||
#define AR5K_TXDESC_CTSENA 0x0008
|
||||
#define AR5K_TXDESC_INTREQ 0x0010
|
||||
#define AR5K_TXDESC_VEOL 0x0020 /*[5211+]*/
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue