drm/amd/powerplay/vega20: enable fan RPM and pwm settings V2
Manual fan RPM and pwm setting on vega20 are available now. V2: correct the register for fan speed setting and avoid divide-by-zero Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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42fae99520
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031db09017
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@ -26,6 +26,18 @@
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#define mmCG_MULT_THERMAL_STATUS 0x005f
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#define mmCG_MULT_THERMAL_STATUS_BASE_IDX 0
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#define mmCG_FDO_CTRL0 0x0067
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#define mmCG_FDO_CTRL0_BASE_IDX 0
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#define mmCG_FDO_CTRL1 0x0068
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#define mmCG_FDO_CTRL1_BASE_IDX 0
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#define mmCG_FDO_CTRL2 0x0069
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#define mmCG_FDO_CTRL2_BASE_IDX 0
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#define mmCG_TACH_CTRL 0x006a
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#define mmCG_TACH_CTRL_BASE_IDX 0
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#define mmTHM_THERMAL_INT_ENA 0x000a
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#define mmTHM_THERMAL_INT_ENA_BASE_IDX 0
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#define mmTHM_THERMAL_INT_CTRL 0x000b
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@ -28,6 +28,16 @@
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#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9
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#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x000001FFL
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#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x0003FE00L
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#define CG_FDO_CTRL2__TMIN__SHIFT 0x0
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#define CG_FDO_CTRL2__TMIN_MASK 0x000000FFL
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#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb
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#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x00003800L
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#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0
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#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0x000000FFL
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#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0
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#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0x000000FFL
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#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3
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#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xFFFFFFF8L
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//THM_THERMAL_INT_ENA
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#define THM_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0
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@ -2289,6 +2289,25 @@ static uint32_t vega20_get_fan_control_mode(struct pp_hwmgr *hwmgr)
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return AMD_FAN_CTRL_AUTO;
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}
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static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
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{
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switch (mode) {
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case AMD_FAN_CTRL_NONE:
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vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
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break;
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case AMD_FAN_CTRL_MANUAL:
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if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
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vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
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break;
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case AMD_FAN_CTRL_AUTO:
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if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
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vega20_fan_ctrl_start_smc_fan_control(hwmgr);
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break;
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default:
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break;
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}
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}
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static int vega20_get_dal_power_level(struct pp_hwmgr *hwmgr,
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struct amd_pp_simple_clock_info *info)
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{
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@ -3452,12 +3471,20 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
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.disable_smc_firmware_ctf =
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vega20_thermal_disable_alert,
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/* fan control related */
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.get_fan_speed_percent =
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vega20_fan_ctrl_get_fan_speed_percent,
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.set_fan_speed_percent =
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vega20_fan_ctrl_set_fan_speed_percent,
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.get_fan_speed_info =
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vega20_fan_ctrl_get_fan_speed_info,
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.get_fan_speed_rpm =
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vega20_fan_ctrl_get_fan_speed_rpm,
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.set_fan_speed_rpm =
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vega20_fan_ctrl_set_fan_speed_rpm,
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.get_fan_control_mode =
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vega20_get_fan_control_mode,
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.set_fan_control_mode =
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vega20_set_fan_control_mode,
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/* smu memory related */
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.notify_cac_buffer_info =
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vega20_notify_cac_buffer_info,
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@ -29,6 +29,78 @@
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#include "soc15_common.h"
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#include "pp_debug.h"
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static int vega20_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
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{
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struct vega20_hwmgr *data = hwmgr->backend;
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int ret = 0;
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if (data->smu_features[GNLD_FAN_CONTROL].supported) {
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ret = vega20_enable_smc_features(
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hwmgr, false,
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data->smu_features[GNLD_FAN_CONTROL].
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smu_feature_bitmap);
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PP_ASSERT_WITH_CODE(!ret,
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"Disable FAN CONTROL feature Failed!",
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return ret);
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data->smu_features[GNLD_FAN_CONTROL].enabled = false;
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}
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return ret;
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}
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int vega20_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
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{
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struct vega20_hwmgr *data = hwmgr->backend;
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if (data->smu_features[GNLD_FAN_CONTROL].supported)
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return vega20_disable_fan_control_feature(hwmgr);
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return 0;
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}
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static int vega20_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
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{
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struct vega20_hwmgr *data = hwmgr->backend;
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int ret = 0;
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if (data->smu_features[GNLD_FAN_CONTROL].supported) {
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ret = vega20_enable_smc_features(
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hwmgr, true,
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data->smu_features[GNLD_FAN_CONTROL].
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smu_feature_bitmap);
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PP_ASSERT_WITH_CODE(!ret,
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"Enable FAN CONTROL feature Failed!",
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return ret);
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data->smu_features[GNLD_FAN_CONTROL].enabled = true;
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}
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return ret;
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}
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int vega20_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
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{
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struct vega20_hwmgr *data = hwmgr->backend;
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if (data->smu_features[GNLD_FAN_CONTROL].supported)
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return vega20_enable_fan_control_feature(hwmgr);
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return 0;
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}
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static int vega20_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
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REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
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CG_FDO_CTRL2, TMIN, 0));
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WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
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REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
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CG_FDO_CTRL2, FDO_PWM_MODE, mode));
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return 0;
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}
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static int vega20_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
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{
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int ret = 0;
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@ -42,12 +114,62 @@ static int vega20_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
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return 0;
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}
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int vega20_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
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uint32_t *speed)
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{
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struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
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PPTable_t *pp_table = &(data->smc_state_table.pp_table);
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uint32_t current_rpm, percent = 0;
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int ret = 0;
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ret = vega20_get_current_rpm(hwmgr, ¤t_rpm);
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if (ret)
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return ret;
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percent = current_rpm * 100 / pp_table->FanMaximumRpm;
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*speed = percent > 100 ? 100 : percent;
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return 0;
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}
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int vega20_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
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uint32_t speed)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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uint32_t duty100;
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uint32_t duty;
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uint64_t tmp64;
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if (speed > 100)
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speed = 100;
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if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
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vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
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duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
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CG_FDO_CTRL1, FMAX_DUTY100);
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if (duty100 == 0)
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return -EINVAL;
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tmp64 = (uint64_t)speed * duty100;
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do_div(tmp64, 100);
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duty = (uint32_t)tmp64;
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WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
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REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
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CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
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return vega20_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
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}
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int vega20_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
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struct phm_fan_speed_info *fan_speed_info)
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{
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memset(fan_speed_info, 0, sizeof(*fan_speed_info));
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fan_speed_info->supports_percent_read = false;
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fan_speed_info->supports_percent_write = false;
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fan_speed_info->supports_percent_read = true;
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fan_speed_info->supports_percent_write = true;
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fan_speed_info->supports_rpm_read = true;
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fan_speed_info->supports_rpm_write = true;
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@ -61,6 +183,31 @@ int vega20_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
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return vega20_get_current_rpm(hwmgr, speed);
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}
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int vega20_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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uint32_t tach_period, crystal_clock_freq;
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int result = 0;
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if (!speed)
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return -EINVAL;
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if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) {
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result = vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
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if (result)
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return result;
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}
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crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
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tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
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WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
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REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
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CG_TACH_CTRL, TARGET_PERIOD,
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tach_period));
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return vega20_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
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}
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/**
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* Reads the remote temperature from the SIslands thermal controller.
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*
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@ -50,15 +50,22 @@ struct vega20_temperature {
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#define FDO_PWM_MODE_STATIC_RPM 5
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extern int vega20_thermal_get_temperature(struct pp_hwmgr *hwmgr);
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extern int vega20_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
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extern int vega20_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
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struct phm_fan_speed_info *fan_speed_info);
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extern int vega20_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
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extern int vega20_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr,
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uint32_t *speed);
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extern int vega20_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr,
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uint32_t speed);
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extern int vega20_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
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uint32_t *speed);
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extern int vega20_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
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uint32_t speed);
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extern int vega20_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr);
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extern int vega20_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr);
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extern int vega20_thermal_disable_alert(struct pp_hwmgr *hwmgr);
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extern int vega20_start_thermal_controller(struct pp_hwmgr *hwmgr,
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struct PP_TemperatureRange *range);
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extern int vega20_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
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#endif
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