iwlagn: remove the indirection for the dma channel num
Not needed since the driver split. Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -125,7 +125,6 @@ static int iwl1000_hw_set_hw_params(struct iwl_priv *priv)
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iwlagn_mod_params.num_of_queues;
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priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
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priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
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priv->hw_params.scd_bc_tbls_size =
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priv->cfg->base_params->num_of_queues *
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sizeof(struct iwlagn_scd_bc_tbl);
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@ -123,7 +123,6 @@ static int iwl2000_hw_set_hw_params(struct iwl_priv *priv)
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iwlagn_mod_params.num_of_queues;
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priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
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priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
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priv->hw_params.scd_bc_tbls_size =
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priv->cfg->base_params->num_of_queues *
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sizeof(struct iwlagn_scd_bc_tbl);
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@ -156,7 +156,6 @@ static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
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iwlagn_mod_params.num_of_queues;
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priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
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priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
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priv->hw_params.scd_bc_tbls_size =
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priv->cfg->base_params->num_of_queues *
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sizeof(struct iwlagn_scd_bc_tbl);
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@ -200,7 +199,6 @@ static int iwl5150_hw_set_hw_params(struct iwl_priv *priv)
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iwlagn_mod_params.num_of_queues;
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priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
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priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
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priv->hw_params.scd_bc_tbls_size =
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priv->cfg->base_params->num_of_queues *
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sizeof(struct iwlagn_scd_bc_tbl);
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@ -144,7 +144,6 @@ static int iwl6000_hw_set_hw_params(struct iwl_priv *priv)
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iwlagn_mod_params.num_of_queues;
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priv->hw_params.max_txq_num = priv->cfg->base_params->num_of_queues;
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priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
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priv->hw_params.scd_bc_tbls_size =
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priv->cfg->base_params->num_of_queues *
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sizeof(struct iwlagn_scd_bc_tbl);
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@ -406,7 +406,7 @@ static int iwlagn_alive_notify(struct iwl_priv *priv)
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priv->scd_bc_tbls.dma >> 10);
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/* Enable DMA channel */
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for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
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for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
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iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
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FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
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@ -640,7 +640,6 @@ struct iwl_sensitivity_ranges {
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/**
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* struct iwl_hw_params
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* @max_txq_num: Max # Tx queues supported
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* @dma_chnl_num: Number of Tx DMA/FIFO channels
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* @scd_bc_tbls_size: size of scheduler byte count tables
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* @tfd_size: TFD size
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* @tx/rx_chains_num: Number of TX/RX chains
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@ -662,7 +661,6 @@ struct iwl_sensitivity_ranges {
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*/
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struct iwl_hw_params {
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u8 max_txq_num;
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u8 dma_chnl_num;
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u16 scd_bc_tbls_size;
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u32 tfd_size;
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u8 tx_chains_num;
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@ -326,7 +326,7 @@
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#define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60)
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/* Find Control/Status reg for given Tx DMA/FIFO channel */
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#define FH50_TCSR_CHNL_NUM (8)
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#define FH_TCSR_CHNL_NUM (8)
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/* TCSR: tx_config register values */
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#define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
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@ -529,7 +529,7 @@ static int iwl_trans_tx_stop(struct iwl_priv *priv)
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iwlagn_txq_set_sched(priv, 0);
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/* Stop each Tx DMA channel, and wait for it to be idle */
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for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
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for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
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iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
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if (iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
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FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
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