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drm/dp: reuse the 8b/10b link training delay helpers 

Reuse the 8b/10b link training delay helpers. Functionally this skips
the check for invalid values for DPCD 1.4 and later at clock recovery
delay (as it's a fixed delay and bypasses the rd_interval) but the same
value will be checked and invalid values reported at channel
equalization.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211014150059.28957-2-jani.nikula@intel.com
This commit is contained in:
Jani Nikula 2021-10-14 18:00:58 +03:00
parent ba3078dad1
commit 02ed47aa6c
1 changed files with 10 additions and 20 deletions
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30
drivers/gpu/drm/drm_dp_helper.c
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@ -270,35 +270,25 @@ EXPORT_SYMBOL(drm_dp_read_channel_eq_delay);
void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
const u8 dpcd[DP_RECEIVER_CAP_SIZE])
{
unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
DP_TRAINING_AUX_RD_MASK;
u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
DP_TRAINING_AUX_RD_MASK;
int delay_us;
if (rd_interval > 4)
drm_dbg_kms(aux->drm_dev, "%s: AUX interval %lu, out of range (max 4)\n",
aux->name, rd_interval);
if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
rd_interval = 100;
if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
delay_us = 100;
else
rd_interval *= 4 * USEC_PER_MSEC;
delay_us = __8b10b_clock_recovery_delay_us(aux, rd_interval);
usleep_range(rd_interval, rd_interval * 2);
usleep_range(delay_us, delay_us * 2);
}
EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
unsigned long rd_interval)
u8 rd_interval)
{
if (rd_interval > 4)
drm_dbg_kms(aux->drm_dev, "%s: AUX interval %lu, out of range (max 4)\n",
aux->name, rd_interval);
int delay_us = __8b10b_channel_eq_delay_us(aux, rd_interval);
if (rd_interval == 0)
rd_interval = 400;
else
rd_interval *= 4 * USEC_PER_MSEC;
usleep_range(rd_interval, rd_interval * 2);
usleep_range(delay_us, delay_us * 2);
}
void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,