drm/i915: properly guard ilk ips state
The update_gfx_val function called from mark_busy wasn't taking the mchdev_lock, as it should have. Also sprinkle a few spinlock asserts over the code to document things better. Things are still rather confusing, especially since a few variables in dev_priv are used by both the gen6+ rps code and the ilk ips code. But protected by totally different locks. Follow-on patches will clean that up. v2: Don't add a deadlock ... hence split up update_gfx_val into a wrapper that grabs the lock and an internal __ variant for callsites within intel_pm.c that already have taken the lock. v3: Mark the internal helper as static, noticed by Ben Widawsky. v4: Damien Lespiau had questions about the safety of the ips setup sequence, explain in a comment why it works. Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -2710,6 +2710,21 @@ static const struct cparams {
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{ 0, 800, 231, 23784 },
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};
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/**
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* Lock protecting IPS related data structures
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* - i915_mch_dev
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* - dev_priv->max_delay
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* - dev_priv->min_delay
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* - dev_priv->fmax
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* - dev_priv->gpu_busy
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* - dev_priv->gfx_power
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*/
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static DEFINE_SPINLOCK(mchdev_lock);
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/* Global for IPS driver to get at the current i915 device. Protected by
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* mchdev_lock. */
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static struct drm_i915_private *i915_mch_dev;
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unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
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{
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u64 total_count, diff, ret;
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@ -2717,6 +2732,8 @@ unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
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unsigned long now = jiffies_to_msecs(jiffies), diff1;
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int i;
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assert_spin_locked(&mchdev_lock);
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diff1 = now - dev_priv->last_time1;
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/* Prevent division-by-zero if we are asking too fast.
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@ -2918,15 +2935,14 @@ static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
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return v_table[pxvid].vd;
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}
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void i915_update_gfx_val(struct drm_i915_private *dev_priv)
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static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
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{
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struct timespec now, diff1;
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u64 diff;
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unsigned long diffms;
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u32 count;
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if (dev_priv->info->gen != 5)
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return;
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assert_spin_locked(&mchdev_lock);
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getrawmonotonic(&now);
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diff1 = timespec_sub(now, dev_priv->last_time2);
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@ -2954,11 +2970,25 @@ void i915_update_gfx_val(struct drm_i915_private *dev_priv)
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dev_priv->gfx_power = diff;
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}
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void i915_update_gfx_val(struct drm_i915_private *dev_priv)
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{
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if (dev_priv->info->gen != 5)
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return;
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spin_lock(&mchdev_lock);
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__i915_update_gfx_val(dev_priv);
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spin_unlock(&mchdev_lock);
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}
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unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
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{
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unsigned long t, corr, state1, corr2, state2;
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u32 pxvid, ext_v;
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assert_spin_locked(&mchdev_lock);
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pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
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pxvid = (pxvid >> 24) & 0x7f;
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ext_v = pvid_to_extvid(dev_priv, pxvid);
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@ -2984,23 +3014,11 @@ unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
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state2 = (corr2 * state1) / 10000;
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state2 /= 100; /* convert to mW */
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i915_update_gfx_val(dev_priv);
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__i915_update_gfx_val(dev_priv);
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return dev_priv->gfx_power + state2;
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}
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/* Global for IPS driver to get at the current i915 device */
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static struct drm_i915_private *i915_mch_dev;
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/*
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* Lock protecting IPS related data structures
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* - i915_mch_dev
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* - dev_priv->max_delay
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* - dev_priv->min_delay
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* - dev_priv->fmax
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* - dev_priv->gpu_busy
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*/
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static DEFINE_SPINLOCK(mchdev_lock);
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/**
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* i915_read_mch_val - return value for IPS use
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*
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@ -3163,6 +3181,8 @@ ips_ping_for_i915_load(void)
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void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
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{
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/* We only register the i915 ips part with intel-ips once everything is
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* set up, to avoid intel-ips sneaking in and reading bogus values. */
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spin_lock(&mchdev_lock);
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i915_mch_dev = dev_priv;
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dev_priv->mchdev_lock = &mchdev_lock;
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