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drm/amd/display: fix odm mpo disable 

It looks like mpo isn't properly disabled during odm, this change is
meant to fix that.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin 2019-04-23 16:02:45 -04:00 committed by Alex Deucher
parent 72c6473a6a
commit 02ce5a799a
1 changed files with 6 additions and 5 deletions
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11
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
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@ -2153,6 +2153,11 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
} else } else
need_split = context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 2; need_split = context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 2;
/* We do not support mpo + odm at the moment */
if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
&& context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
goto validate_fail;
if (need_split3d || need_split || force_split) { if (need_split3d || need_split || force_split) {
if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) { if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
/* pipe not split previously needs split */ /* pipe not split previously needs split */
@ -2168,11 +2173,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
goto validate_fail; goto validate_fail;
pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
} }
} else if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state) { } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
/* We do not support mpo + odm at the moment */
if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
goto validate_fail;
} else if (hsplit_pipe) {
/* merge should already have been done */ /* merge should already have been done */
ASSERT(0); ASSERT(0);
} }