clk: renesas: rzg2l: Fix reset status function
As per RZ/G2L HW(Rev.1.10) manual, reset monitor register value 0 means
reset signal is not applied (deassert state) and 1 means reset signal
is applied (assert state).
reset_control_status() expects a positive value if the reset line is
asserted. But rzg2l_cpg_status function returns zero for asserted
state.
This patch fixes the issue by adding double inverted logic, so that
reset_control_status returns a positive value if the reset line is
asserted.
Fixes: ef3c613ccd
("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220531071657.104121-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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@ -1180,7 +1180,7 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
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s8 monbit = info->resets[id].monbit;
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if (info->has_clk_mon_regs) {
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return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
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return !!(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
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} else if (monbit >= 0) {
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u32 monbitmask = BIT(monbit);
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