clk: samsung: mark s3c...._clk_sleep_init() as __init
These functions are referencing s3c...._clk_regs[], which are marked as
__initdata. When compiling with CONFIG_DEBUG_SECTION_MISMATCH=y, this
produces warnings like
WARNING: vmlinux.o(.text+0x198350):
Section mismatch in reference from the function s3c2410_clk_sleep_init()
to the (unknown reference) .init.data:(unknown)
Mark the s3c...._clk_sleep_init() functions as __init in
order to fix this.
Fixes: ca2e90ac18
("clk: samsung: add clock controller driver for s3c2412")
Signed-off-by: Martin Kaiser <martin@kaiser.cx>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
parent
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@ -76,7 +76,7 @@ static struct syscore_ops s3c2410_clk_syscore_ops = {
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.resume = s3c2410_clk_resume,
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};
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static void s3c2410_clk_sleep_init(void)
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static void __init s3c2410_clk_sleep_init(void)
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{
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s3c2410_save = samsung_clk_alloc_reg_dump(s3c2410_clk_regs,
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ARRAY_SIZE(s3c2410_clk_regs));
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@ -90,7 +90,7 @@ static void s3c2410_clk_sleep_init(void)
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return;
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}
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#else
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static void s3c2410_clk_sleep_init(void) {}
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static void __init s3c2410_clk_sleep_init(void) {}
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#endif
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PNAME(fclk_p) = { "mpll", "div_slow" };
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@ -69,7 +69,7 @@ static struct syscore_ops s3c2412_clk_syscore_ops = {
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.resume = s3c2412_clk_resume,
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};
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static void s3c2412_clk_sleep_init(void)
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static void __init s3c2412_clk_sleep_init(void)
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{
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s3c2412_save = samsung_clk_alloc_reg_dump(s3c2412_clk_regs,
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ARRAY_SIZE(s3c2412_clk_regs));
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@ -83,7 +83,7 @@ static void s3c2412_clk_sleep_init(void)
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return;
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}
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#else
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static void s3c2412_clk_sleep_init(void) {}
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static void __init s3c2412_clk_sleep_init(void) {}
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#endif
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static struct clk_div_table divxti_d[] = {
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@ -89,7 +89,7 @@ static struct syscore_ops s3c2443_clk_syscore_ops = {
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.resume = s3c2443_clk_resume,
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};
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static void s3c2443_clk_sleep_init(void)
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static void __init s3c2443_clk_sleep_init(void)
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{
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s3c2443_save = samsung_clk_alloc_reg_dump(s3c2443_clk_regs,
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ARRAY_SIZE(s3c2443_clk_regs));
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@ -103,7 +103,7 @@ static void s3c2443_clk_sleep_init(void)
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return;
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}
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#else
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static void s3c2443_clk_sleep_init(void) {}
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static void __init s3c2443_clk_sleep_init(void) {}
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#endif
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PNAME(epllref_p) = { "mpllref", "mpllref", "xti", "ext" };
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@ -121,7 +121,7 @@ static struct syscore_ops s3c64xx_clk_syscore_ops = {
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.resume = s3c64xx_clk_resume,
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};
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static void s3c64xx_clk_sleep_init(void)
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static void __init s3c64xx_clk_sleep_init(void)
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{
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s3c64xx_save_common = samsung_clk_alloc_reg_dump(s3c64xx_clk_regs,
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ARRAY_SIZE(s3c64xx_clk_regs));
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@ -145,7 +145,7 @@ err_warn:
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__func__);
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}
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#else
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static void s3c64xx_clk_sleep_init(void) {}
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static void __init s3c64xx_clk_sleep_init(void) {}
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#endif
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/* List of parent clocks common for all S3C64xx SoCs. */
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