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OpenCloudOS-Kernel
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Merge branches 'clk-legacy', 'clk-vc5', 'clk-allwinner', 'clk-nvidia' and 'clk-imx' into clk-next 

* clk-legacy:
  clkdev: remove unused clkdev_alloc() interfaces
  clkdev: remove CONFIG_CLKDEV_LOOKUP
  m68k: coldfire: remove private clk_get/clk_put
  m68k: coldfire: use clkdev_lookup on most coldfire
  mips: ralink: convert to CONFIG_COMMON_CLK
  mips: ar7: convert to CONFIG_COMMON_CLK
  mips: ar7: convert to clkdev_lookup

* clk-vc5:
  clk: vc5: fix output disabling when enabling a FOD

* clk-allwinner:
  clk: sunxi-ng: v3s: fix incorrect postdivider on pll-audio

* clk-nvidia:
  clk: tegra: clk-tegra124-dfll-fcpu: don't use devm functions for regulator
  clk: tegra: tegra124-emc: Fix clock imbalance in emc_set_timing()
  clk: tegra: Add stubs needed for compile-testing
  clk: tegra: Don't deassert reset on enabling clocks
  clk: tegra: Mark external clocks as not having reset control
  clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling
  clk: tegra: Don't allow zero clock rate for PLLs
  clk: tegra: Halve SCLK rate on Tegra20
  clk: tegra: Ensure that PLLU configuration is applied properly
  clk: tegra: Fix refcounting of gate clocks
  clk: tegra30: Use 300MHz for video decoder by default

* clk-imx:
  clk: imx8mq: remove SYS PLL 1/2 clock gates
  clk: imx: scu: Do not enable runtime PM for CPU clks
  clk: imx: scu: add parent save and restore
  clk: imx: scu: Only save DC SS clock using non-cached clock rate
  clk: imx: scu: Add A72 frequency scaling support
  clk: imx: scu: Add A53 frequency scaling support
  clk: imx: scu: bypass pi_pll enable status restore
  clk: imx: scu: detach pd if can't power up
  clk: imx: scu: bypass cpu clock save and restore
  clk: imx: scu: add parallel port clock ops
  clk: imx: scu: add more scu clocks
  clk: imx: scu: add enet rgmii gpr clocks
  clk: imx8qm: add clock valid resource checking
  clk: imx8qxp: add clock valid checking mechnism
  clk: imx: scu: add gpr clocks support
  clk: imx: scu: remove legacy scu clock binding support
  dt-bindings: arm: imx: scu: drop deprecated legacy clock binding
  dt-bindings: arm: imx: scu: fix naming typo of clk compatible string
  clk: imx: Remove the audio ipg clock from imx8mp
This commit is contained in:
Stephen Boyd 2021-06-29 13:33:10 -07:00
parent d915611eda 4c5519facf fc336ae622 ee7fe68769 2f0d67bf4c 8e5f17e6c2
commit 029eae234b
57 changed files with 1319 additions and 997 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
View File

@ -86,13 +86,11 @@ This binding uses the common clock binding[1].
Required properties:
- compatible: Should be one of:
"fsl,imx8qm-clock"
"fsl,imx8qxp-clock"
"fsl,imx8qm-clk"
"fsl,imx8qxp-clk"
followed by "fsl,scu-clk"
- #clock-cells: Should be either
2: Contains the Resource and Clock ID value.
or
1: Contains the Clock ID value. (DEPRECATED)
- #clock-cells: Should be 2.
Contains the Resource and Clock ID value.
- clocks: List of clock specifiers, must contain an entry for
each required entry in clock-names
- clock-names: Should include entries "xtal_32KHz", "xtal_24MHz"

2
arch/arm/Kconfig
View File

@ -353,7 +353,6 @@ config ARCH_EP93XX
select ARM_VIC
select GENERIC_IRQ_MULTI_HANDLER
select AUTO_ZRELADDR
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select CPU_ARM920T
select GPIOLIB
@ -504,7 +503,6 @@ config ARCH_OMAP1
bool "TI OMAP1"
depends on MMU
select ARCH_OMAP
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select GENERIC_IRQ_CHIP
select GENERIC_IRQ_MULTI_HANDLER

21
arch/m68k/coldfire/clk.c
View File

@ -73,20 +73,6 @@ struct clk_ops clk_ops1 = {
#endif /* MCFPM_PPMCR1 */
#endif /* MCFPM_PPMCR0 */
struct clk *clk_get(struct device *dev, const char *id)
{
const char *clk_name = dev ? dev_name(dev) : id ? id : NULL;
struct clk *clk;
unsigned i;
for (i = 0; (clk = mcf_clks[i]) != NULL; ++i)
if (!strcmp(clk->name, clk_name))
return clk;
pr_warn("clk_get: didn't find clock %s\n", clk_name);
return ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL(clk_get);
int clk_enable(struct clk *clk)
{
unsigned long flags;
@ -117,13 +103,6 @@ void clk_disable(struct clk *clk)
}
EXPORT_SYMBOL(clk_disable);
void clk_put(struct clk *clk)
{
if (clk->enabled != 0)
pr_warn("clk_put %s still enabled\n", clk->name);
}
EXPORT_SYMBOL(clk_put);
unsigned long clk_get_rate(struct clk *clk)
{
if (!clk)

25
arch/m68k/coldfire/m5206.c
View File

@ -10,6 +10,7 @@
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -23,21 +24,15 @@
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcftmr0,
&clk_mcftmr1,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfi2c0,
NULL
static struct clk_lookup m5206_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
};
/***************************************************************************/
@ -66,6 +61,8 @@ void __init config_BSP(char *commandp, int size)
mcf_mapirq2imr(28, MCFINTC_EINT4);
mcf_mapirq2imr(31, MCFINTC_EINT7);
m5206_i2c_init();
clkdev_add_table(m5206_clk_lookup, ARRAY_SIZE(m5206_clk_lookup));
}
/***************************************************************************/

51
arch/m68k/coldfire/m520x.c
View File

@ -12,6 +12,7 @@
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -48,31 +49,29 @@ DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK);
DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
DEFINE_CLK(0, "sdram.0", 42, MCF_CLK);
struct clk *mcf_clks[] = {
&__clk_0_2, /* flexbus */
&__clk_0_12, /* fec.0 */
&__clk_0_17, /* edma */
&__clk_0_18, /* intc.0 */
&__clk_0_21, /* iack.0 */
&__clk_0_22, /* imx1-i2c.0 */
&__clk_0_23, /* mcfqspi.0 */
&__clk_0_24, /* mcfuart.0 */
&__clk_0_25, /* mcfuart.1 */
&__clk_0_26, /* mcfuart.2 */
&__clk_0_28, /* mcftmr.0 */
&__clk_0_29, /* mcftmr.1 */
&__clk_0_30, /* mcftmr.2 */
&__clk_0_31, /* mcftmr.3 */
&__clk_0_32, /* mcfpit.0 */
&__clk_0_33, /* mcfpit.1 */
&__clk_0_34, /* mcfeport.0 */
&__clk_0_35, /* mcfwdt.0 */
&__clk_0_36, /* pll.0 */
&__clk_0_40, /* sys.0 */
&__clk_0_41, /* gpio.0 */
&__clk_0_42, /* sdram.0 */
NULL,
static struct clk_lookup m520x_clk_lookup[] = {
CLKDEV_INIT(NULL, "flexbus", &__clk_0_2),
CLKDEV_INIT("fec.0", NULL, &__clk_0_12),
CLKDEV_INIT("edma", NULL, &__clk_0_17),
CLKDEV_INIT("intc.0", NULL, &__clk_0_18),
CLKDEV_INIT("iack.0", NULL, &__clk_0_21),
CLKDEV_INIT("imx1-i2c.0", NULL, &__clk_0_22),
CLKDEV_INIT("mcfqspi.0", NULL, &__clk_0_23),
CLKDEV_INIT("mcfuart.0", NULL, &__clk_0_24),
CLKDEV_INIT("mcfuart.1", NULL, &__clk_0_25),
CLKDEV_INIT("mcfuart.2", NULL, &__clk_0_26),
CLKDEV_INIT("mcftmr.0", NULL, &__clk_0_28),
CLKDEV_INIT("mcftmr.1", NULL, &__clk_0_29),
CLKDEV_INIT("mcftmr.2", NULL, &__clk_0_30),
CLKDEV_INIT("mcftmr.3", NULL, &__clk_0_31),
CLKDEV_INIT("mcfpit.0", NULL, &__clk_0_32),
CLKDEV_INIT("mcfpit.1", NULL, &__clk_0_33),
CLKDEV_INIT("mcfeport.0", NULL, &__clk_0_34),
CLKDEV_INIT("mcfwdt.0", NULL, &__clk_0_35),
CLKDEV_INIT(NULL, "pll.0", &__clk_0_36),
CLKDEV_INIT(NULL, "sys.0", &__clk_0_40),
CLKDEV_INIT("gpio.0", NULL, &__clk_0_41),
CLKDEV_INIT("sdram.0", NULL, &__clk_0_42),
};
static struct clk * const enable_clks[] __initconst = {
@ -115,6 +114,8 @@ static void __init m520x_clk_init(void)
/* make sure these clocks are disabled */
for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
__clk_init_disabled(disable_clks[i]);
clkdev_add_table(m520x_clk_lookup, ARRAY_SIZE(m520x_clk_lookup));
}
/***************************************************************************/

40
arch/m68k/coldfire/m523x.c
View File

@ -13,6 +13,7 @@
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -26,31 +27,20 @@
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcfpit0,
&clk_mcfpit1,
&clk_mcfpit2,
&clk_mcfpit3,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfuart2,
&clk_mcfqspi0,
&clk_fec0,
&clk_mcfi2c0,
NULL
struct clk_lookup m523x_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcfpit.0", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.1", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.2", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.3", NULL, &clk_pll),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.2", NULL, &clk_sys),
CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
CLKDEV_INIT("fec.0", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
};
/***************************************************************************/
@ -100,6 +90,8 @@ void __init config_BSP(char *commandp, int size)
m523x_fec_init();
m523x_qspi_init();
m523x_i2c_init();
clkdev_add_table(m523x_clk_lookup, ARRAY_SIZE(m523x_clk_lookup));
}
/***************************************************************************/

31
arch/m68k/coldfire/m5249.c
View File

@ -9,6 +9,7 @@
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -23,25 +24,17 @@
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
DEFINE_CLK(mcfi2c1, "imx1-i2c.1", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcftmr0,
&clk_mcftmr1,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfqspi0,
&clk_mcfi2c0,
&clk_mcfi2c1,
NULL
struct clk_lookup m5249_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.1", NULL, &clk_sys),
};
/***************************************************************************/
@ -137,6 +130,8 @@ void __init config_BSP(char *commandp, int size)
#endif
m5249_qspi_init();
m5249_i2c_init();
clkdev_add_table(m5249_clk_lookup, ARRAY_SIZE(m5249_clk_lookup));
}
/***************************************************************************/

31
arch/m68k/coldfire/m525x.c
View File

@ -9,6 +9,7 @@
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -23,25 +24,17 @@
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
DEFINE_CLK(mcfi2c1, "imx1-i2c.1", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcftmr0,
&clk_mcftmr1,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfqspi0,
&clk_mcfi2c0,
&clk_mcfi2c1,
NULL
static struct clk_lookup m525x_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.1", NULL, &clk_sys),
};
/***************************************************************************/
@ -88,6 +81,8 @@ void __init config_BSP(char *commandp, int size)
m525x_qspi_init();
m525x_i2c_init();
clkdev_add_table(m525x_clk_lookup, ARRAY_SIZE(m525x_clk_lookup));
}
/***************************************************************************/

33
arch/m68k/coldfire/m5272.c
View File

@ -10,6 +10,7 @@
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -34,27 +35,18 @@ unsigned char ledbank = 0xff;
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcftmr2, "mcftmr.2", MCF_BUSCLK);
DEFINE_CLK(mcftmr3, "mcftmr.3", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcftmr0,
&clk_mcftmr1,
&clk_mcftmr2,
&clk_mcftmr3,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfqspi0,
&clk_fec0,
NULL
static struct clk_lookup m5272_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
CLKDEV_INIT("mcftmr.2", NULL, &clk_sys),
CLKDEV_INIT("mcftmr.3", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
CLKDEV_INIT("fec.0", NULL, &clk_sys),
};
/***************************************************************************/
@ -128,6 +120,7 @@ static int __init init_BSP(void)
{
m5272_uarts_init();
fixed_phy_add(PHY_POLL, 0, &nettel_fixed_phy_status);
clkdev_add_table(m5272_clk_lookup, ARRAY_SIZE(m5272_clk_lookup));
return 0;
}

42
arch/m68k/coldfire/m527x.c
View File

@ -13,6 +13,7 @@
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -27,33 +28,21 @@
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
DEFINE_CLK(fec1, "fec.1", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcfpit0,
&clk_mcfpit1,
&clk_mcfpit2,
&clk_mcfpit3,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfuart2,
&clk_mcfqspi0,
&clk_fec0,
&clk_fec1,
&clk_mcfi2c0,
NULL
static struct clk_lookup m527x_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcfpit.0", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.1", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.2", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.3", NULL, &clk_pll),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.2", NULL, &clk_sys),
CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
CLKDEV_INIT("fec.0", NULL, &clk_sys),
CLKDEV_INIT("fec.1", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
};
/***************************************************************************/
@ -151,6 +140,7 @@ void __init config_BSP(char *commandp, int size)
m527x_fec_init();
m527x_qspi_init();
m527x_i2c_init();
clkdev_add_table(m527x_clk_lookup, ARRAY_SIZE(m527x_clk_lookup));
}
/***************************************************************************/

40
arch/m68k/coldfire/m528x.c
View File

@ -13,6 +13,7 @@
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -28,31 +29,20 @@
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcfpit0,
&clk_mcfpit1,
&clk_mcfpit2,
&clk_mcfpit3,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfuart2,
&clk_mcfqspi0,
&clk_fec0,
&clk_mcfi2c0,
NULL
static struct clk_lookup m528x_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcfpit.0", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.1", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.2", NULL, &clk_pll),
CLKDEV_INIT("mcfpit.3", NULL, &clk_pll),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.2", NULL, &clk_sys),
CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
CLKDEV_INIT("fec.0", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
};
/***************************************************************************/
@ -146,6 +136,8 @@ void __init config_BSP(char *commandp, int size)
m528x_fec_init();
m528x_qspi_init();
m528x_i2c_init();
clkdev_add_table(m528x_clk_lookup, ARRAY_SIZE(m528x_clk_lookup));
}
/***************************************************************************/

25
arch/m68k/coldfire/m5307.c
View File

@ -10,6 +10,7 @@
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -32,21 +33,15 @@ unsigned char ledbank = 0xff;
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcftmr0,
&clk_mcftmr1,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfi2c0,
NULL
static struct clk_lookup m5307_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
};
/***************************************************************************/
@ -88,6 +83,8 @@ void __init config_BSP(char *commandp, int size)
wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
#endif
m5307_i2c_init();
clkdev_add_table(m5307_clk_lookup, ARRAY_SIZE(m5307_clk_lookup));
}
/***************************************************************************/

78
arch/m68k/coldfire/m53xx.c
View File

@ -13,6 +13,7 @@
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -65,45 +66,42 @@ DEFINE_CLK(1, "mdha.0", 32, MCF_CLK);
DEFINE_CLK(1, "skha.0", 33, MCF_CLK);
DEFINE_CLK(1, "rng.0", 34, MCF_CLK);
struct clk *mcf_clks[] = {
&__clk_0_2, /* flexbus */
&__clk_0_8, /* mcfcan.0 */
&__clk_0_12, /* fec.0 */
&__clk_0_17, /* edma */
&__clk_0_18, /* intc.0 */
&__clk_0_19, /* intc.1 */
&__clk_0_21, /* iack.0 */
&__clk_0_22, /* imx1-i2c.0 */
&__clk_0_23, /* mcfqspi.0 */
&__clk_0_24, /* mcfuart.0 */
&__clk_0_25, /* mcfuart.1 */
&__clk_0_26, /* mcfuart.2 */
&__clk_0_28, /* mcftmr.0 */
&__clk_0_29, /* mcftmr.1 */
&__clk_0_30, /* mcftmr.2 */
&__clk_0_31, /* mcftmr.3 */
&__clk_0_32, /* mcfpit.0 */
&__clk_0_33, /* mcfpit.1 */
&__clk_0_34, /* mcfpit.2 */
&__clk_0_35, /* mcfpit.3 */
&__clk_0_36, /* mcfpwm.0 */
&__clk_0_37, /* mcfeport.0 */
&__clk_0_38, /* mcfwdt.0 */
&__clk_0_40, /* sys.0 */
&__clk_0_41, /* gpio.0 */
&__clk_0_42, /* mcfrtc.0 */
&__clk_0_43, /* mcflcd.0 */
&__clk_0_44, /* mcfusb-otg.0 */
&__clk_0_45, /* mcfusb-host.0 */
&__clk_0_46, /* sdram.0 */
&__clk_0_47, /* ssi.0 */
&__clk_0_48, /* pll.0 */
&__clk_1_32, /* mdha.0 */
&__clk_1_33, /* skha.0 */
&__clk_1_34, /* rng.0 */
NULL,
static struct clk_lookup m53xx_clk_lookup[] = {
CLKDEV_INIT("flexbus", NULL, &__clk_0_2),
CLKDEV_INIT("mcfcan.0", NULL, &__clk_0_8),
CLKDEV_INIT("fec.0", NULL, &__clk_0_12),
CLKDEV_INIT("edma", NULL, &__clk_0_17),
CLKDEV_INIT("intc.0", NULL, &__clk_0_18),
CLKDEV_INIT("intc.1", NULL, &__clk_0_19),
CLKDEV_INIT("iack.0", NULL, &__clk_0_21),
CLKDEV_INIT("imx1-i2c.0", NULL, &__clk_0_22),
CLKDEV_INIT("mcfqspi.0", NULL, &__clk_0_23),
CLKDEV_INIT("mcfuart.0", NULL, &__clk_0_24),
CLKDEV_INIT("mcfuart.1", NULL, &__clk_0_25),
CLKDEV_INIT("mcfuart.2", NULL, &__clk_0_26),
CLKDEV_INIT("mcftmr.0", NULL, &__clk_0_28),
CLKDEV_INIT("mcftmr.1", NULL, &__clk_0_29),
CLKDEV_INIT("mcftmr.2", NULL, &__clk_0_30),
CLKDEV_INIT("mcftmr.3", NULL, &__clk_0_31),
CLKDEV_INIT("mcfpit.0", NULL, &__clk_0_32),
CLKDEV_INIT("mcfpit.1", NULL, &__clk_0_33),
CLKDEV_INIT("mcfpit.2", NULL, &__clk_0_34),
CLKDEV_INIT("mcfpit.3", NULL, &__clk_0_35),
CLKDEV_INIT("mcfpwm.0", NULL, &__clk_0_36),
CLKDEV_INIT("mcfeport.0", NULL, &__clk_0_37),
CLKDEV_INIT("mcfwdt.0", NULL, &__clk_0_38),
CLKDEV_INIT(NULL, "sys.0", &__clk_0_40),
CLKDEV_INIT("gpio.0", NULL, &__clk_0_41),
CLKDEV_INIT("mcfrtc.0", NULL, &__clk_0_42),
CLKDEV_INIT("mcflcd.0", NULL, &__clk_0_43),
CLKDEV_INIT("mcfusb-otg.0", NULL, &__clk_0_44),
CLKDEV_INIT("mcfusb-host.0", NULL, &__clk_0_45),
CLKDEV_INIT("sdram.0", NULL, &__clk_0_46),
CLKDEV_INIT("ssi.0", NULL, &__clk_0_47),
CLKDEV_INIT(NULL, "pll.0", &__clk_0_48),
CLKDEV_INIT("mdha.0", NULL, &__clk_1_32),
CLKDEV_INIT("skha.0", NULL, &__clk_1_33),
CLKDEV_INIT("rng.0", NULL, &__clk_1_34),
};
static struct clk * const enable_clks[] __initconst = {
@ -158,6 +156,8 @@ static void __init m53xx_clk_init(void)
/* make sure these clocks are disabled */
for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
__clk_init_disabled(disable_clks[i]);
clkdev_add_table(m53xx_clk_lookup, ARRAY_SIZE(m53xx_clk_lookup));
}
/***************************************************************************/

25
arch/m68k/coldfire/m5407.c
View File

@ -10,6 +10,7 @@
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -23,21 +24,15 @@
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcftmr0,
&clk_mcftmr1,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfi2c0,
NULL
static struct clk_lookup m5407_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
};
/***************************************************************************/
@ -63,6 +58,8 @@ void __init config_BSP(char *commandp, int size)
mcf_mapirq2imr(29, MCFINTC_EINT5);
mcf_mapirq2imr(31, MCFINTC_EINT7);
m5407_i2c_init();
clkdev_add_table(m5407_clk_lookup, ARRAY_SIZE(m5407_clk_lookup));
}
/***************************************************************************/

126
arch/m68k/coldfire/m5441x.c
View File

@ -5,6 +5,7 @@
* (C) Copyright Steven King <sfking@fdwdc.com>
*/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -78,72 +79,67 @@ DEFINE_CLK(2, "ipg.0", 0, MCF_CLK);
DEFINE_CLK(2, "ahb.0", 1, MCF_CLK);
DEFINE_CLK(2, "per.0", 2, MCF_CLK);
struct clk *mcf_clks[] = {
&__clk_0_2,
&__clk_0_8,
&__clk_0_9,
&__clk_0_14,
&__clk_0_15,
&__clk_0_17,
&__clk_0_18,
&__clk_0_19,
&__clk_0_20,
&__clk_0_22,
&__clk_0_23,
&__clk_0_24,
&__clk_0_25,
&__clk_0_26,
&__clk_0_27,
&__clk_0_28,
&__clk_0_29,
&__clk_0_30,
&__clk_0_31,
&__clk_0_32,
&__clk_0_33,
&__clk_0_34,
&__clk_0_35,
&__clk_0_37,
&__clk_0_38,
&__clk_0_39,
&__clk_0_42,
&__clk_0_43,
&__clk_0_44,
&__clk_0_45,
&__clk_0_46,
&__clk_0_47,
&__clk_0_48,
&__clk_0_49,
&__clk_0_50,
&__clk_0_51,
&__clk_0_53,
&__clk_0_54,
&__clk_0_55,
&__clk_0_56,
&__clk_0_63,
&__clk_1_2,
&__clk_1_4,
&__clk_1_5,
&__clk_1_6,
&__clk_1_7,
&__clk_1_24,
&__clk_1_25,
&__clk_1_26,
&__clk_1_27,
&__clk_1_28,
&__clk_1_29,
&__clk_1_34,
&__clk_1_36,
&__clk_1_37,
&__clk_2_0,
&__clk_2_1,
&__clk_2_2,
NULL,
static struct clk_lookup m5411x_clk_lookup[] = {
CLKDEV_INIT("flexbus", NULL, &__clk_0_2),
CLKDEV_INIT("mcfcan.0", NULL, &__clk_0_8),
CLKDEV_INIT("mcfcan.1", NULL, &__clk_0_9),
CLKDEV_INIT("imx1-i2c.1", NULL, &__clk_0_14),
CLKDEV_INIT("mcfdspi.1", NULL, &__clk_0_15),
CLKDEV_INIT("edma", NULL, &__clk_0_17),
CLKDEV_INIT("intc.0", NULL, &__clk_0_18),
CLKDEV_INIT("intc.1", NULL, &__clk_0_19),
CLKDEV_INIT("intc.2", NULL, &__clk_0_20),
CLKDEV_INIT("imx1-i2c.0", NULL, &__clk_0_22),
CLKDEV_INIT("fsl-dspi.0", NULL, &__clk_0_23),
CLKDEV_INIT("mcfuart.0", NULL, &__clk_0_24),
CLKDEV_INIT("mcfuart.1", NULL, &__clk_0_25),
CLKDEV_INIT("mcfuart.2", NULL, &__clk_0_26),
CLKDEV_INIT("mcfuart.3", NULL, &__clk_0_27),
CLKDEV_INIT("mcftmr.0", NULL, &__clk_0_28),
CLKDEV_INIT("mcftmr.1", NULL, &__clk_0_29),
CLKDEV_INIT("mcftmr.2", NULL, &__clk_0_30),
CLKDEV_INIT("mcftmr.3", NULL, &__clk_0_31),
CLKDEV_INIT("mcfpit.0", NULL, &__clk_0_32),
CLKDEV_INIT("mcfpit.1", NULL, &__clk_0_33),
CLKDEV_INIT("mcfpit.2", NULL, &__clk_0_34),
CLKDEV_INIT("mcfpit.3", NULL, &__clk_0_35),
CLKDEV_INIT("mcfeport.0", NULL, &__clk_0_37),
CLKDEV_INIT("mcfadc.0", NULL, &__clk_0_38),
CLKDEV_INIT("mcfdac.0", NULL, &__clk_0_39),
CLKDEV_INIT("mcfrtc.0", NULL, &__clk_0_42),
CLKDEV_INIT("mcfsim.0", NULL, &__clk_0_43),
CLKDEV_INIT("mcfusb-otg.0", NULL, &__clk_0_44),
CLKDEV_INIT("mcfusb-host.0", NULL, &__clk_0_45),
CLKDEV_INIT("mcfddr-sram.0", NULL, &__clk_0_46),
CLKDEV_INIT("mcfssi.0", NULL, &__clk_0_47),
CLKDEV_INIT(NULL, "pll.0", &__clk_0_48),
CLKDEV_INIT("mcfrng.0", NULL, &__clk_0_49),
CLKDEV_INIT("mcfssi.1", NULL, &__clk_0_50),
CLKDEV_INIT("sdhci-esdhc-mcf.0", NULL, &__clk_0_51),
CLKDEV_INIT("enet-fec.0", NULL, &__clk_0_53),
CLKDEV_INIT("enet-fec.1", NULL, &__clk_0_54),
CLKDEV_INIT("switch.0", NULL, &__clk_0_55),
CLKDEV_INIT("switch.1", NULL, &__clk_0_56),
CLKDEV_INIT("nand.0", NULL, &__clk_0_63),
CLKDEV_INIT("mcfow.0", NULL, &__clk_1_2),
CLKDEV_INIT("imx1-i2c.2", NULL, &__clk_1_4),
CLKDEV_INIT("imx1-i2c.3", NULL, &__clk_1_5),
CLKDEV_INIT("imx1-i2c.4", NULL, &__clk_1_6),
CLKDEV_INIT("imx1-i2c.5", NULL, &__clk_1_7),
CLKDEV_INIT("mcfuart.4", NULL, &__clk_1_24),
CLKDEV_INIT("mcfuart.5", NULL, &__clk_1_25),
CLKDEV_INIT("mcfuart.6", NULL, &__clk_1_26),
CLKDEV_INIT("mcfuart.7", NULL, &__clk_1_27),
CLKDEV_INIT("mcfuart.8", NULL, &__clk_1_28),
CLKDEV_INIT("mcfuart.9", NULL, &__clk_1_29),
CLKDEV_INIT("mcfpwm.0", NULL, &__clk_1_34),
CLKDEV_INIT(NULL, "sys.0", &__clk_1_36),
CLKDEV_INIT("gpio.0", NULL, &__clk_1_37),
CLKDEV_INIT("ipg.0", NULL, &__clk_2_0),
CLKDEV_INIT("ahb.0", NULL, &__clk_2_1),
CLKDEV_INIT("per.0", NULL, &__clk_2_2),
};
static struct clk * const enable_clks[] __initconst = {
/* make sure these clocks are enabled */
&__clk_0_15, /* dspi.1 */
@ -228,6 +224,8 @@ static void __init m5441x_clk_init(void)
/* make sure these clocks are disabled */
for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
__clk_init_disabled(disable_clks[i]);
clkdev_add_table(m5411x_clk_lookup, ARRAY_SIZE(m5411x_clk_lookup));
}
static void __init m5441x_uarts_init(void)

31
arch/m68k/coldfire/m54xx.c
View File

@ -9,6 +9,7 @@
/***************************************************************************/
#include <linux/clkdev.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/init.h>
@ -32,25 +33,17 @@
DEFINE_CLK(pll, "pll.0", MCF_CLK);
DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
DEFINE_CLK(mcfslt0, "mcfslt.0", MCF_BUSCLK);
DEFINE_CLK(mcfslt1, "mcfslt.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
DEFINE_CLK(mcfuart3, "mcfuart.3", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
&clk_sys,
&clk_mcfslt0,
&clk_mcfslt1,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfuart2,
&clk_mcfuart3,
&clk_mcfi2c0,
NULL
static struct clk_lookup m54xx_clk_lookup[] = {
CLKDEV_INIT(NULL, "pll.0", &clk_pll),
CLKDEV_INIT(NULL, "sys.0", &clk_sys),
CLKDEV_INIT("mcfslt.0", NULL, &clk_sys),
CLKDEV_INIT("mcfslt.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.2", NULL, &clk_sys),
CLKDEV_INIT("mcfuart.3", NULL, &clk_sys),
CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
};
/***************************************************************************/
@ -100,6 +93,8 @@ void __init config_BSP(char *commandp, int size)
mach_sched_init = hw_timer_init;
m54xx_uarts_init();
m54xx_i2c_init();
clkdev_add_table(m54xx_clk_lookup, ARRAY_SIZE(m54xx_clk_lookup));
}
/***************************************************************************/

5
arch/m68k/include/asm/mcfclk.h
View File

@ -15,15 +15,12 @@ struct clk_ops {
};
struct clk {
const char *name;
struct clk_ops *clk_ops;
unsigned long rate;
unsigned long enabled;
u8 slot;
};
extern struct clk *mcf_clks[];
#ifdef MCFPM_PPMCR0
extern struct clk_ops clk_ops0;
#ifdef MCFPM_PPMCR1
@ -34,7 +31,6 @@ extern struct clk_ops clk_ops2;
#define DEFINE_CLK(clk_bank, clk_name, clk_slot, clk_rate) \
static struct clk __clk_##clk_bank##_##clk_slot = { \
.name = clk_name, \
.clk_ops = &clk_ops##clk_bank, \
.rate = clk_rate, \
.slot = clk_slot, \
@ -45,7 +41,6 @@ void __clk_init_disabled(struct clk *);
#else
#define DEFINE_CLK(clk_ref, clk_name, clk_rate) \
static struct clk clk_##clk_ref = { \
.name = clk_name, \
.rate = clk_rate, \
}
#endif /* MCFPM_PPMCR0 */

6
arch/mips/Kconfig
View File

@ -201,6 +201,7 @@ config MIPS_ALCHEMY
config AR7
bool "Texas Instruments AR7"
select BOOT_ELF32
select COMMON_CLK
select DMA_NONCOHERENT
select CEVT_R4K
select CSRC_R4K
@ -215,7 +216,6 @@ config AR7
select SYS_SUPPORTS_ZBOOT_UART16550
select GPIOLIB
select VLYNQ
select HAVE_LEGACY_CLK
help
Support for the Texas Instruments AR7 System-on-a-Chip
family: TNETD7100, 7200 and 7300.
@ -332,7 +332,6 @@ config BCM63XX
select SWAP_IO_SPACE
select GPIOLIB
select MIPS_L1_CACHE_SHIFT_4
select CLKDEV_LOOKUP
select HAVE_LEGACY_CLK
help
Support for BCM63XX based boards
@ -446,7 +445,6 @@ config LANTIQ
select GPIOLIB
select SWAP_IO_SPACE
select BOOT_RAW
select CLKDEV_LOOKUP
select HAVE_LEGACY_CLK
select USE_OF
select PINCTRL
@ -630,6 +628,7 @@ config MACH_NINTENDO64
config RALINK
bool "Ralink based machines"
select CEVT_R4K
select COMMON_CLK
select CSRC_R4K
select BOOT_RAW
select DMA_NONCOHERENT
@ -642,7 +641,6 @@ config RALINK
select SYS_SUPPORTS_MIPS16
select SYS_SUPPORTS_ZBOOT
select SYS_HAS_EARLY_PRINTK
select CLKDEV_LOOKUP
select ARCH_HAS_RESET_CONTROLLER
select RESET_CONTROLLER

113
arch/mips/ar7/clock.c
View File

@ -13,7 +13,9 @@
#include <linux/gcd.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/clkdev.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <asm/addrspace.h>
#include <asm/mach-ar7/ar7.h>
@ -84,17 +86,17 @@ struct tnetd7200_clocks {
struct tnetd7200_clock usb;
};
static struct clk bus_clk = {
struct clk_rate {
u32 rate;
};
static struct clk_rate bus_clk = {
.rate = 125000000,
};
static struct clk cpu_clk = {
static struct clk_rate cpu_clk = {
.rate = 150000000,
};
static struct clk dsp_clk;
static struct clk vbus_clk;
static void approximate(int base, int target, int *prediv,
int *postdiv, int *mul)
{
@ -240,6 +242,8 @@ static void __init tnetd7300_init_clocks(void)
struct tnetd7300_clocks *clocks =
ioremap(UR8_REGS_CLOCKS,
sizeof(struct tnetd7300_clocks));
u32 dsp_clk;
struct clk *clk;
bus_clk.rate = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
&clocks->bus, bootcr, AR7_AFE_CLOCK);
@ -250,12 +254,18 @@ static void __init tnetd7300_init_clocks(void)
else
cpu_clk.rate = bus_clk.rate;
if (dsp_clk.rate == 250000000)
dsp_clk = tnetd7300_dsp_clock();
if (dsp_clk == 250000000)
tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
bootcr, dsp_clk.rate);
bootcr, dsp_clk);
iounmap(clocks);
iounmap(bootcr);
clk = clk_register_fixed_rate(NULL, "cpu", NULL, 0, cpu_clk.rate);
clkdev_create(clk, "cpu", NULL);
clk = clk_register_fixed_rate(NULL, "dsp", NULL, 0, dsp_clk);
clkdev_create(clk, "dsp", NULL);
}
static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock,
@ -327,6 +337,7 @@ static void __init tnetd7200_init_clocks(void)
int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv;
int dsp_base, dsp_mul, dsp_prediv, dsp_postdiv;
int usb_base, usb_mul, usb_prediv, usb_postdiv;
struct clk *clk;
cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr);
dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr);
@ -395,100 +406,34 @@ static void __init tnetd7200_init_clocks(void)
usb_prediv, usb_postdiv, -1, usb_mul,
TNETD7200_DEF_USB_CLK);
dsp_clk.rate = cpu_clk.rate;
iounmap(clocks);
iounmap(bootcr);
}
/*
* Linux clock API
*/
int clk_enable(struct clk *clk)
{
return 0;
clk = clk_register_fixed_rate(NULL, "cpu", NULL, 0, cpu_clk.rate);
clkdev_create(clk, "cpu", NULL);
clkdev_create(clk, "dsp", NULL);
}
EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
if (!clk)
return 0;
return clk->rate;
}
EXPORT_SYMBOL(clk_get_rate);
struct clk *clk_get(struct device *dev, const char *id)
{
if (!strcmp(id, "bus"))
return &bus_clk;
/* cpmac and vbus share the same rate */
if (!strcmp(id, "cpmac"))
return &vbus_clk;
if (!strcmp(id, "cpu"))
return &cpu_clk;
if (!strcmp(id, "dsp"))
return &dsp_clk;
if (!strcmp(id, "vbus"))
return &vbus_clk;
return ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL(clk_get);
void clk_put(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_put);
void __init ar7_init_clocks(void)
{
struct clk *clk;
switch (ar7_chip_id()) {
case AR7_CHIP_7100:
case AR7_CHIP_7200:
tnetd7200_init_clocks();
break;
case AR7_CHIP_7300:
dsp_clk.rate = tnetd7300_dsp_clock();
tnetd7300_init_clocks();
break;
default:
break;
}
clk = clk_register_fixed_rate(NULL, "bus", NULL, 0, bus_clk.rate);
clkdev_create(clk, "bus", NULL);
/* adjust vbus clock rate */
vbus_clk.rate = bus_clk.rate / 2;
clk = clk_register_fixed_factor(NULL, "vbus", "bus", 0, 1, 2);
clkdev_create(clk, "vbus", NULL);
clkdev_create(clk, "cpmac", "cpmac.1");
clkdev_create(clk, "cpmac", "cpmac.1");
}
/* dummy functions, should not be called */
long clk_round_rate(struct clk *clk, unsigned long rate)
{
WARN_ON(clk);
return 0;
}
EXPORT_SYMBOL(clk_round_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
WARN_ON(clk);
return 0;
}
EXPORT_SYMBOL(clk_set_rate);
int clk_set_parent(struct clk *clk, struct clk *parent)
{
WARN_ON(clk);
return 0;
}
EXPORT_SYMBOL(clk_set_parent);
struct clk *clk_get_parent(struct clk *clk)
{
WARN_ON(clk);
return NULL;
}
EXPORT_SYMBOL(clk_get_parent);

4
arch/mips/include/asm/mach-ar7/ar7.h
View File

@ -131,10 +131,6 @@ static inline u8 ar7_chip_rev(void)
0x14))) >> 16) & 0xff;
}
struct clk {
unsigned int rate;
};
static inline int ar7_has_high_cpmac(void)
{
u16 chip_id = ar7_chip_id();

1
arch/mips/pic32/Kconfig
View File

@ -17,7 +17,6 @@ config PIC32MZDA
select SYS_SUPPORTS_LITTLE_ENDIAN
select GPIOLIB
select COMMON_CLK
select CLKDEV_LOOKUP
select LIBFDT
select USE_OF
select PINCTRL

5
arch/mips/ralink/Kconfig
View File

@ -28,22 +28,18 @@ choice
bool "RT288x"
select MIPS_AUTO_PFN_OFFSET
select MIPS_L1_CACHE_SHIFT_4
select HAVE_LEGACY_CLK
select HAVE_PCI
config SOC_RT305X
bool "RT305x"
select HAVE_LEGACY_CLK
config SOC_RT3883
bool "RT3883"
select HAVE_LEGACY_CLK
select HAVE_PCI
config SOC_MT7620
bool "MT7620/8"
select CPU_MIPSR2_IRQ_VI
select HAVE_LEGACY_CLK
select HAVE_PCI
config SOC_MT7621
@ -54,7 +50,6 @@ choice
select SYS_SUPPORTS_MIPS_CPS
select SYS_SUPPORTS_HIGHMEM
select MIPS_GIC
select COMMON_CLK
select CLKSRC_MIPS_GIC
select HAVE_PCI if PCI_MT7621
select SOC_BUS

64
arch/mips/ralink/clk.c
View File

@ -10,80 +10,22 @@
#include <linux/export.h>
#include <linux/clkdev.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <asm/time.h>
#include "common.h"
struct clk {
struct clk_lookup cl;
unsigned long rate;
};
void ralink_clk_add(const char *dev, unsigned long rate)
{
struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
struct clk *clk = clk_register_fixed_rate(NULL, dev, NULL, 0, rate);
if (!clk)
panic("failed to add clock");
clk->cl.dev_id = dev;
clk->cl.clk = clk;
clk->rate = rate;
clkdev_add(&clk->cl);
clkdev_create(clk, NULL, "%s", dev);
}
/*
* Linux clock API
*/
int clk_enable(struct clk *clk)
{
return 0;
}
EXPORT_SYMBOL_GPL(clk_enable);
void clk_disable(struct clk *clk)
{
}
EXPORT_SYMBOL_GPL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
if (!clk)
return 0;
return clk->rate;
}
EXPORT_SYMBOL_GPL(clk_get_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
return -1;
}
EXPORT_SYMBOL_GPL(clk_set_rate);
long clk_round_rate(struct clk *clk, unsigned long rate)
{
return -1;
}
EXPORT_SYMBOL_GPL(clk_round_rate);
int clk_set_parent(struct clk *clk, struct clk *parent)
{
WARN_ON(clk);
return -1;
}
EXPORT_SYMBOL_GPL(clk_set_parent);
struct clk *clk_get_parent(struct clk *clk)
{
WARN_ON(clk);
return NULL;
}
EXPORT_SYMBOL_GPL(clk_get_parent);
void __init plat_time_init(void)
{
struct clk *clk;

1
arch/sh/Kconfig
View File

@ -14,7 +14,6 @@ config SUPERH
select ARCH_HIBERNATION_POSSIBLE if MMU
select ARCH_MIGHT_HAVE_PC_PARPORT
select ARCH_WANT_IPC_PARSE_VERSION
select CLKDEV_LOOKUP
select CPU_NO_EFFICIENT_FFS
select DMA_DECLARE_COHERENT
select GENERIC_ATOMIC64

6
drivers/clk/Kconfig
View File

@ -6,10 +6,6 @@ config HAVE_CLK
The <linux/clk.h> calls support software clock gating and
thus are a key power management tool on many systems.
config CLKDEV_LOOKUP
bool
select HAVE_CLK
config HAVE_CLK_PREPARE
bool
@ -26,7 +22,7 @@ menuconfig COMMON_CLK
bool "Common Clock Framework"
depends on !HAVE_LEGACY_CLK
select HAVE_CLK_PREPARE
select CLKDEV_LOOKUP
select HAVE_CLK
select SRCU
select RATIONAL
help

3
drivers/clk/Makefile
View File

@ -1,7 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
# common clock types
obj-$(CONFIG_HAVE_CLK) += clk-devres.o clk-bulk.o
obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
obj-$(CONFIG_HAVE_CLK) += clk-devres.o clk-bulk.o clkdev.o
obj-$(CONFIG_COMMON_CLK) += clk.o
obj-$(CONFIG_COMMON_CLK) += clk-divider.o
obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o

27
drivers/clk/clk-versaclock5.c
View File

@ -69,7 +69,10 @@
#define VC5_FEEDBACK_FRAC_DIV(n) (0x19 + (n))
#define VC5_RC_CONTROL0 0x1e
#define VC5_RC_CONTROL1 0x1f
/* Register 0x20 is factory reserved */
/* These registers are named "Unused Factory Reserved Registers" */
#define VC5_RESERVED_X0(idx) (0x20 + ((idx) * 0x10))
#define VC5_RESERVED_X0_BYPASS_SYNC BIT(7) /* bypass_sync<idx> bit */
/* Output divider control for divider 1,2,3,4 */
#define VC5_OUT_DIV_CONTROL(idx) (0x21 + ((idx) * 0x10))
@ -87,7 +90,6 @@
#define VC5_OUT_DIV_SKEW_INT(idx, n) (0x2b + ((idx) * 0x10) + (n))
#define VC5_OUT_DIV_INT(idx, n) (0x2d + ((idx) * 0x10) + (n))
#define VC5_OUT_DIV_SKEW_FRAC(idx) (0x2f + ((idx) * 0x10))
/* Registers 0x30, 0x40, 0x50 are factory reserved */
/* Clock control register for clock 1,2 */
#define VC5_CLK_OUTPUT_CFG(idx, n) (0x60 + ((idx) * 0x2) + (n))
@ -140,6 +142,8 @@
#define VC5_HAS_INTERNAL_XTAL BIT(0)
/* chip has PFD requency doubler */
#define VC5_HAS_PFD_FREQ_DBL BIT(1)
/* chip has bits to disable FOD sync */
#define VC5_HAS_BYPASS_SYNC_BIT BIT(2)
/* Supported IDT VC5 models. */
enum vc5_model {
@ -581,6 +585,23 @@ static int vc5_clk_out_prepare(struct clk_hw *hw)
unsigned int src;
int ret;
/*
* When enabling a FOD, all currently enabled FODs are briefly
* stopped in order to synchronize all of them. This causes a clock
* disruption to any unrelated chips that might be already using
* other clock outputs. Bypass the sync feature to avoid the issue,
* which is possible on the VersaClock 6E family via reserved
* registers.
*/
if (vc5->chip_info->flags & VC5_HAS_BYPASS_SYNC_BIT) {
ret = regmap_update_bits(vc5->regmap,
VC5_RESERVED_X0(hwdata->num),
VC5_RESERVED_X0_BYPASS_SYNC,
VC5_RESERVED_X0_BYPASS_SYNC);
if (ret)
return ret;
}
/*
* If the input mux is disabled, enable it first and
* select source from matching FOD.
@ -1166,7 +1187,7 @@ static const struct vc5_chip_info idt_5p49v6965_info = {
.model = IDT_VC6_5P49V6965,
.clk_fod_cnt = 4,
.clk_out_cnt = 5,
.flags = 0,
.flags = VC5_HAS_BYPASS_SYNC_BIT,
};
static const struct i2c_device_id vc5_id[] = {

28
drivers/clk/clkdev.c
View File

@ -190,34 +190,6 @@ vclkdev_create(struct clk_hw *hw, const char *con_id, const char *dev_fmt,
return cl;
}
struct clk_lookup * __ref
clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...)
{
struct clk_lookup *cl;
va_list ap;
va_start(ap, dev_fmt);
cl = vclkdev_alloc(__clk_get_hw(clk), con_id, dev_fmt, ap);
va_end(ap);
return cl;
}
EXPORT_SYMBOL(clkdev_alloc);
struct clk_lookup *
clkdev_hw_alloc(struct clk_hw *hw, const char *con_id, const char *dev_fmt, ...)
{
struct clk_lookup *cl;
va_list ap;
va_start(ap, dev_fmt);
cl = vclkdev_alloc(hw, con_id, dev_fmt, ap);
va_end(ap);
return cl;
}
EXPORT_SYMBOL(clkdev_hw_alloc);
/**
* clkdev_create - allocate and add a clkdev lookup structure
* @clk: struct clk to associate with all clk_lookups

3
drivers/clk/imx/Makefile
View File

@ -27,7 +27,8 @@ obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o
obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o
obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o
clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o
clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \
clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o
clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o
obj-$(CONFIG_CLK_IMX1) += clk-imx1.o

1
drivers/clk/imx/clk-imx8mp.c
View File

@ -556,7 +556,6 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_hw_composite_bus("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm_base + 0x9200);
hws[IMX8MP_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb_root", ccm_base + 0x9080, 0, 1);
hws[IMX8MP_CLK_IPG_AUDIO_ROOT] = imx_clk_hw_divider2("ipg_audio_root", "audio_ahb", ccm_base + 0x9180, 0, 1);
hws[IMX8MP_CLK_DRAM_ALT] = imx8m_clk_hw_composite("dram_alt", imx8mp_dram_alt_sels, ccm_base + 0xa000);
hws[IMX8MP_CLK_DRAM_APB] = imx8m_clk_hw_composite_critical("dram_apb", imx8mp_dram_apb_sels, ccm_base + 0xa080);

56
drivers/clk/imx/clk-imx8mq.c
View File

@ -358,46 +358,26 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
hws[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_hw_sscg_pll("video2_pll_out", video2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, base + 0x54, 0);
/* SYS PLL1 fixed output */
hws[IMX8MQ_SYS1_PLL_40M_CG] = imx_clk_hw_gate("sys1_pll_40m_cg", "sys1_pll_out", base + 0x30, 9);
hws[IMX8MQ_SYS1_PLL_80M_CG] = imx_clk_hw_gate("sys1_pll_80m_cg", "sys1_pll_out", base + 0x30, 11);
hws[IMX8MQ_SYS1_PLL_100M_CG] = imx_clk_hw_gate("sys1_pll_100m_cg", "sys1_pll_out", base + 0x30, 13);
hws[IMX8MQ_SYS1_PLL_133M_CG] = imx_clk_hw_gate("sys1_pll_133m_cg", "sys1_pll_out", base + 0x30, 15);
hws[IMX8MQ_SYS1_PLL_160M_CG] = imx_clk_hw_gate("sys1_pll_160m_cg", "sys1_pll_out", base + 0x30, 17);
hws[IMX8MQ_SYS1_PLL_200M_CG] = imx_clk_hw_gate("sys1_pll_200m_cg", "sys1_pll_out", base + 0x30, 19);
hws[IMX8MQ_SYS1_PLL_266M_CG] = imx_clk_hw_gate("sys1_pll_266m_cg", "sys1_pll_out", base + 0x30, 21);
hws[IMX8MQ_SYS1_PLL_400M_CG] = imx_clk_hw_gate("sys1_pll_400m_cg", "sys1_pll_out", base + 0x30, 23);
hws[IMX8MQ_SYS1_PLL_800M_CG] = imx_clk_hw_gate("sys1_pll_800m_cg", "sys1_pll_out", base + 0x30, 25);
hws[IMX8MQ_SYS1_PLL_40M] = imx_clk_hw_fixed_factor("sys1_pll_40m", "sys1_pll_40m_cg", 1, 20);
hws[IMX8MQ_SYS1_PLL_80M] = imx_clk_hw_fixed_factor("sys1_pll_80m", "sys1_pll_80m_cg", 1, 10);
hws[IMX8MQ_SYS1_PLL_100M] = imx_clk_hw_fixed_factor("sys1_pll_100m", "sys1_pll_100m_cg", 1, 8);
hws[IMX8MQ_SYS1_PLL_133M] = imx_clk_hw_fixed_factor("sys1_pll_133m", "sys1_pll_133m_cg", 1, 6);
hws[IMX8MQ_SYS1_PLL_160M] = imx_clk_hw_fixed_factor("sys1_pll_160m", "sys1_pll_160m_cg", 1, 5);
hws[IMX8MQ_SYS1_PLL_200M] = imx_clk_hw_fixed_factor("sys1_pll_200m", "sys1_pll_200m_cg", 1, 4);
hws[IMX8MQ_SYS1_PLL_266M] = imx_clk_hw_fixed_factor("sys1_pll_266m", "sys1_pll_266m_cg", 1, 3);
hws[IMX8MQ_SYS1_PLL_400M] = imx_clk_hw_fixed_factor("sys1_pll_400m", "sys1_pll_400m_cg", 1, 2);
hws[IMX8MQ_SYS1_PLL_800M] = imx_clk_hw_fixed_factor("sys1_pll_800m", "sys1_pll_800m_cg", 1, 1);
hws[IMX8MQ_SYS1_PLL_40M] = imx_clk_hw_fixed_factor("sys1_pll_40m", "sys1_pll_out", 1, 20);
hws[IMX8MQ_SYS1_PLL_80M] = imx_clk_hw_fixed_factor("sys1_pll_80m", "sys1_pll_out", 1, 10);
hws[IMX8MQ_SYS1_PLL_100M] = imx_clk_hw_fixed_factor("sys1_pll_100m", "sys1_pll_out", 1, 8);
hws[IMX8MQ_SYS1_PLL_133M] = imx_clk_hw_fixed_factor("sys1_pll_133m", "sys1_pll_out", 1, 6);
hws[IMX8MQ_SYS1_PLL_160M] = imx_clk_hw_fixed_factor("sys1_pll_160m", "sys1_pll_out", 1, 5);
hws[IMX8MQ_SYS1_PLL_200M] = imx_clk_hw_fixed_factor("sys1_pll_200m", "sys1_pll_out", 1, 4);
hws[IMX8MQ_SYS1_PLL_266M] = imx_clk_hw_fixed_factor("sys1_pll_266m", "sys1_pll_out", 1, 3);
hws[IMX8MQ_SYS1_PLL_400M] = imx_clk_hw_fixed_factor("sys1_pll_400m", "sys1_pll_out", 1, 2);
hws[IMX8MQ_SYS1_PLL_800M] = imx_clk_hw_fixed_factor("sys1_pll_800m", "sys1_pll_out", 1, 1);
/* SYS PLL2 fixed output */
hws[IMX8MQ_SYS2_PLL_50M_CG] = imx_clk_hw_gate("sys2_pll_50m_cg", "sys2_pll_out", base + 0x3c, 9);
hws[IMX8MQ_SYS2_PLL_100M_CG] = imx_clk_hw_gate("sys2_pll_100m_cg", "sys2_pll_out", base + 0x3c, 11);
hws[IMX8MQ_SYS2_PLL_125M_CG] = imx_clk_hw_gate("sys2_pll_125m_cg", "sys2_pll_out", base + 0x3c, 13);
hws[IMX8MQ_SYS2_PLL_166M_CG] = imx_clk_hw_gate("sys2_pll_166m_cg", "sys2_pll_out", base + 0x3c, 15);
hws[IMX8MQ_SYS2_PLL_200M_CG] = imx_clk_hw_gate("sys2_pll_200m_cg", "sys2_pll_out", base + 0x3c, 17);
hws[IMX8MQ_SYS2_PLL_250M_CG] = imx_clk_hw_gate("sys2_pll_250m_cg", "sys2_pll_out", base + 0x3c, 19);
hws[IMX8MQ_SYS2_PLL_333M_CG] = imx_clk_hw_gate("sys2_pll_333m_cg", "sys2_pll_out", base + 0x3c, 21);
hws[IMX8MQ_SYS2_PLL_500M_CG] = imx_clk_hw_gate("sys2_pll_500m_cg", "sys2_pll_out", base + 0x3c, 23);
hws[IMX8MQ_SYS2_PLL_1000M_CG] = imx_clk_hw_gate("sys2_pll_1000m_cg", "sys2_pll_out", base + 0x3c, 25);
hws[IMX8MQ_SYS2_PLL_50M] = imx_clk_hw_fixed_factor("sys2_pll_50m", "sys2_pll_50m_cg", 1, 20);
hws[IMX8MQ_SYS2_PLL_100M] = imx_clk_hw_fixed_factor("sys2_pll_100m", "sys2_pll_100m_cg", 1, 10);
hws[IMX8MQ_SYS2_PLL_125M] = imx_clk_hw_fixed_factor("sys2_pll_125m", "sys2_pll_125m_cg", 1, 8);
hws[IMX8MQ_SYS2_PLL_166M] = imx_clk_hw_fixed_factor("sys2_pll_166m", "sys2_pll_166m_cg", 1, 6);
hws[IMX8MQ_SYS2_PLL_200M] = imx_clk_hw_fixed_factor("sys2_pll_200m", "sys2_pll_200m_cg", 1, 5);
hws[IMX8MQ_SYS2_PLL_250M] = imx_clk_hw_fixed_factor("sys2_pll_250m", "sys2_pll_250m_cg", 1, 4);
hws[IMX8MQ_SYS2_PLL_333M] = imx_clk_hw_fixed_factor("sys2_pll_333m", "sys2_pll_333m_cg", 1, 3);
hws[IMX8MQ_SYS2_PLL_500M] = imx_clk_hw_fixed_factor("sys2_pll_500m", "sys2_pll_500m_cg", 1, 2);
hws[IMX8MQ_SYS2_PLL_1000M] = imx_clk_hw_fixed_factor("sys2_pll_1000m", "sys2_pll_1000m_cg", 1, 1);
hws[IMX8MQ_SYS2_PLL_50M] = imx_clk_hw_fixed_factor("sys2_pll_50m", "sys2_pll_out", 1, 20);
hws[IMX8MQ_SYS2_PLL_100M] = imx_clk_hw_fixed_factor("sys2_pll_100m", "sys2_pll_out", 1, 10);
hws[IMX8MQ_SYS2_PLL_125M] = imx_clk_hw_fixed_factor("sys2_pll_125m", "sys2_pll_out", 1, 8);
hws[IMX8MQ_SYS2_PLL_166M] = imx_clk_hw_fixed_factor("sys2_pll_166m", "sys2_pll_out", 1, 6);
hws[IMX8MQ_SYS2_PLL_200M] = imx_clk_hw_fixed_factor("sys2_pll_200m", "sys2_pll_out", 1, 5);
hws[IMX8MQ_SYS2_PLL_250M] = imx_clk_hw_fixed_factor("sys2_pll_250m", "sys2_pll_out", 1, 4);
hws[IMX8MQ_SYS2_PLL_333M] = imx_clk_hw_fixed_factor("sys2_pll_333m", "sys2_pll_out", 1, 3);
hws[IMX8MQ_SYS2_PLL_500M] = imx_clk_hw_fixed_factor("sys2_pll_500m", "sys2_pll_out", 1, 2);
hws[IMX8MQ_SYS2_PLL_1000M] = imx_clk_hw_fixed_factor("sys2_pll_1000m", "sys2_pll_out", 1, 1);
hws[IMX8MQ_CLK_MON_AUDIO_PLL1_DIV] = imx_clk_hw_divider("audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3);
hws[IMX8MQ_CLK_MON_AUDIO_PLL2_DIV] = imx_clk_hw_divider("audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3);

116
drivers/clk/imx/clk-imx8qm-rsrc.c Normal file
View File

@ -0,0 +1,116 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019-2021 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/firmware/imx/rsrc.h>
#include "clk-scu.h"
/* Keep sorted in the ascending order */
static const u32 imx8qm_clk_scu_rsrc_table[] = {
IMX_SC_R_A53,
IMX_SC_R_A72,
IMX_SC_R_DC_0_VIDEO0,
IMX_SC_R_DC_0_VIDEO1,
IMX_SC_R_DC_0,
IMX_SC_R_DC_0_PLL_0,
IMX_SC_R_DC_0_PLL_1,
IMX_SC_R_DC_1_VIDEO0,
IMX_SC_R_DC_1_VIDEO1,
IMX_SC_R_DC_1,
IMX_SC_R_DC_1_PLL_0,
IMX_SC_R_DC_1_PLL_1,
IMX_SC_R_SPI_0,
IMX_SC_R_SPI_1,
IMX_SC_R_SPI_2,
IMX_SC_R_SPI_3,
IMX_SC_R_UART_0,
IMX_SC_R_UART_1,
IMX_SC_R_UART_2,
IMX_SC_R_UART_3,
IMX_SC_R_UART_4,
IMX_SC_R_EMVSIM_0,
IMX_SC_R_EMVSIM_1,
IMX_SC_R_I2C_0,
IMX_SC_R_I2C_1,
IMX_SC_R_I2C_2,
IMX_SC_R_I2C_3,
IMX_SC_R_I2C_4,
IMX_SC_R_ADC_0,
IMX_SC_R_ADC_1,
IMX_SC_R_FTM_0,
IMX_SC_R_FTM_1,
IMX_SC_R_CAN_0,
IMX_SC_R_GPU_0_PID0,
IMX_SC_R_GPU_1_PID0,
IMX_SC_R_PWM_0,
IMX_SC_R_PWM_1,
IMX_SC_R_PWM_2,
IMX_SC_R_PWM_3,
IMX_SC_R_PWM_4,
IMX_SC_R_PWM_5,
IMX_SC_R_PWM_6,
IMX_SC_R_PWM_7,
IMX_SC_R_GPT_0,
IMX_SC_R_GPT_1,
IMX_SC_R_GPT_2,
IMX_SC_R_GPT_3,
IMX_SC_R_GPT_4,
IMX_SC_R_FSPI_0,
IMX_SC_R_FSPI_1,
IMX_SC_R_SDHC_0,
IMX_SC_R_SDHC_1,
IMX_SC_R_SDHC_2,
IMX_SC_R_ENET_0,
IMX_SC_R_ENET_1,
IMX_SC_R_MLB_0,
IMX_SC_R_USB_2,
IMX_SC_R_NAND,
IMX_SC_R_LVDS_0,
IMX_SC_R_LVDS_0_PWM_0,
IMX_SC_R_LVDS_0_I2C_0,
IMX_SC_R_LVDS_0_I2C_1,
IMX_SC_R_LVDS_1,
IMX_SC_R_LVDS_1_PWM_0,
IMX_SC_R_LVDS_1_I2C_0,
IMX_SC_R_LVDS_1_I2C_1,
IMX_SC_R_M4_0_I2C,
IMX_SC_R_M4_1_I2C,
IMX_SC_R_AUDIO_PLL_0,
IMX_SC_R_VPU_UART,
IMX_SC_R_VPUCORE,
IMX_SC_R_MIPI_0,
IMX_SC_R_MIPI_0_PWM_0,
IMX_SC_R_MIPI_0_I2C_0,
IMX_SC_R_MIPI_0_I2C_1,
IMX_SC_R_MIPI_1,
IMX_SC_R_MIPI_1_PWM_0,
IMX_SC_R_MIPI_1_I2C_0,
IMX_SC_R_MIPI_1_I2C_1,
IMX_SC_R_CSI_0,
IMX_SC_R_CSI_0_PWM_0,
IMX_SC_R_CSI_0_I2C_0,
IMX_SC_R_CSI_1,
IMX_SC_R_CSI_1_PWM_0,
IMX_SC_R_CSI_1_I2C_0,
IMX_SC_R_HDMI,
IMX_SC_R_HDMI_I2S,
IMX_SC_R_HDMI_I2C_0,
IMX_SC_R_HDMI_PLL_0,
IMX_SC_R_HDMI_RX,
IMX_SC_R_HDMI_RX_BYPASS,
IMX_SC_R_HDMI_RX_I2C_0,
IMX_SC_R_AUDIO_PLL_1,
IMX_SC_R_AUDIO_CLK_0,
IMX_SC_R_AUDIO_CLK_1,
IMX_SC_R_HDMI_RX_PWM_0,
IMX_SC_R_HDMI_PLL_1,
IMX_SC_R_VPU,
};
const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm = {
.rsrc = imx8qm_clk_scu_rsrc_table,
.num = ARRAY_SIZE(imx8qm_clk_scu_rsrc_table),
};

89
drivers/clk/imx/clk-imx8qxp-rsrc.c Normal file
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@ -0,0 +1,89 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019-2021 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/firmware/imx/rsrc.h>
#include "clk-scu.h"
/* Keep sorted in the ascending order */
static const u32 imx8qxp_clk_scu_rsrc_table[] = {
IMX_SC_R_DC_0_VIDEO0,
IMX_SC_R_DC_0_VIDEO1,
IMX_SC_R_DC_0,
IMX_SC_R_DC_0_PLL_0,
IMX_SC_R_DC_0_PLL_1,
IMX_SC_R_SPI_0,
IMX_SC_R_SPI_1,
IMX_SC_R_SPI_2,
IMX_SC_R_SPI_3,
IMX_SC_R_UART_0,
IMX_SC_R_UART_1,
IMX_SC_R_UART_2,
IMX_SC_R_UART_3,
IMX_SC_R_I2C_0,
IMX_SC_R_I2C_1,
IMX_SC_R_I2C_2,
IMX_SC_R_I2C_3,
IMX_SC_R_ADC_0,
IMX_SC_R_FTM_0,
IMX_SC_R_FTM_1,
IMX_SC_R_CAN_0,
IMX_SC_R_GPU_0_PID0,
IMX_SC_R_LCD_0,
IMX_SC_R_LCD_0_PWM_0,
IMX_SC_R_PWM_0,
IMX_SC_R_PWM_1,
IMX_SC_R_PWM_2,
IMX_SC_R_PWM_3,
IMX_SC_R_PWM_4,
IMX_SC_R_PWM_5,
IMX_SC_R_PWM_6,
IMX_SC_R_PWM_7,
IMX_SC_R_GPT_0,
IMX_SC_R_GPT_1,
IMX_SC_R_GPT_2,
IMX_SC_R_GPT_3,
IMX_SC_R_GPT_4,
IMX_SC_R_FSPI_0,
IMX_SC_R_FSPI_1,
IMX_SC_R_SDHC_0,
IMX_SC_R_SDHC_1,
IMX_SC_R_SDHC_2,
IMX_SC_R_ENET_0,
IMX_SC_R_ENET_1,
IMX_SC_R_MLB_0,
IMX_SC_R_USB_2,
IMX_SC_R_NAND,
IMX_SC_R_LVDS_0,
IMX_SC_R_LVDS_1,
IMX_SC_R_M4_0_I2C,
IMX_SC_R_ELCDIF_PLL,
IMX_SC_R_AUDIO_PLL_0,
IMX_SC_R_PI_0,
IMX_SC_R_PI_0_PLL,
IMX_SC_R_MIPI_0,
IMX_SC_R_MIPI_0_PWM_0,
IMX_SC_R_MIPI_0_I2C_0,
IMX_SC_R_MIPI_0_I2C_1,
IMX_SC_R_MIPI_1,
IMX_SC_R_MIPI_1_PWM_0,
IMX_SC_R_MIPI_1_I2C_0,
IMX_SC_R_MIPI_1_I2C_1,
IMX_SC_R_CSI_0,
IMX_SC_R_CSI_0_PWM_0,
IMX_SC_R_CSI_0_I2C_0,
IMX_SC_R_AUDIO_PLL_1,
IMX_SC_R_AUDIO_CLK_0,
IMX_SC_R_AUDIO_CLK_1,
IMX_SC_R_A35,
IMX_SC_R_VPU_DEC_0,
IMX_SC_R_VPU_ENC_0,
};
const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp = {
.rsrc = imx8qxp_clk_scu_rsrc_table,
.num = ARRAY_SIZE(imx8qxp_clk_scu_rsrc_table),
};

371
drivers/clk/imx/clk-imx8qxp.c
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@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
* Copyright 2018-2021 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
@ -9,12 +9,12 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "clk-scu.h"
#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/firmware/imx/rsrc.h>
static const char *dc0_sels[] = {
@ -25,159 +25,278 @@ static const char *dc0_sels[] = {
"dc0_bypass0_clk",
};
static const char * const dc1_sels[] = {
"clk_dummy",
"clk_dummy",
"dc1_pll0_clk",
"dc1_pll1_clk",
"dc1_bypass0_clk",
};
static const char * const enet0_rgmii_txc_sels[] = {
"enet0_ref_div",
"clk_dummy",
};
static const char * const enet1_rgmii_txc_sels[] = {
"enet1_ref_div",
"clk_dummy",
};
static const char * const hdmi_sels[] = {
"clk_dummy",
"hdmi_dig_pll_clk",
"clk_dummy",
"clk_dummy",
"hdmi_av_pll_clk",
};
static const char * const hdmi_rx_sels[] = {
"clk_dummy",
"hdmi_rx_dig_pll_clk",
"clk_dummy",
"clk_dummy",
"hdmi_rx_bypass_clk",
};
static const char * const lcd_pxl_sels[] = {
"clk_dummy",
"clk_dummy",
"clk_dummy",
"clk_dummy",
"lcd_pxl_bypass_div_clk",
};
static const char * const mipi_sels[] = {
"clk_dummy",
"clk_dummy",
"mipi_pll_div2_clk",
"clk_dummy",
"clk_dummy",
};
static const char * const lcd_sels[] = {
"clk_dummy",
"clk_dummy",
"clk_dummy",
"clk_dummy",
"elcdif_pll",
};
static const char * const pi_pll0_sels[] = {
"clk_dummy",
"pi_dpll_clk",
"clk_dummy",
"clk_dummy",
"clk_dummy",
};
static int imx8qxp_clk_probe(struct platform_device *pdev)
{
struct device_node *ccm_node = pdev->dev.of_node;
struct clk_hw_onecell_data *clk_data;
struct clk_hw **clks;
u32 clk_cells;
int ret, i;
const struct imx_clk_scu_rsrc_table *rsrc_table;
int ret;
ret = imx_clk_scu_init(ccm_node);
rsrc_table = of_device_get_match_data(&pdev->dev);
ret = imx_clk_scu_init(ccm_node, rsrc_table);
if (ret)
return ret;
clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws,
IMX_SCU_CLK_END), GFP_KERNEL);
if (!clk_data)
return -ENOMEM;
if (of_property_read_u32(ccm_node, "#clock-cells", &clk_cells))
return -EINVAL;
clk_data->num = IMX_SCU_CLK_END;
clks = clk_data->hws;
/* Fixed clocks */
clks[IMX_CLK_DUMMY] = clk_hw_register_fixed_rate(NULL, "dummy", NULL, 0, 0);
clks[IMX_ADMA_IPG_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "dma_ipg_clk_root", NULL, 0, 120000000);
clks[IMX_CONN_AXI_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "conn_axi_clk_root", NULL, 0, 333333333);
clks[IMX_CONN_AHB_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "conn_ahb_clk_root", NULL, 0, 166666666);
clks[IMX_CONN_IPG_CLK_ROOT] = clk_hw_register_fixed_rate(NULL, "conn_ipg_clk_root", NULL, 0, 83333333);
clks[IMX_DC_AXI_EXT_CLK] = clk_hw_register_fixed_rate(NULL, "dc_axi_ext_clk_root", NULL, 0, 800000000);
clks[IMX_DC_AXI_INT_CLK] = clk_hw_register_fixed_rate(NULL, "dc_axi_int_clk_root", NULL, 0, 400000000);
clks[IMX_DC_CFG_CLK] = clk_hw_register_fixed_rate(NULL, "dc_cfg_clk_root", NULL, 0, 100000000);
clks[IMX_MIPI_IPG_CLK] = clk_hw_register_fixed_rate(NULL, "mipi_ipg_clk_root", NULL, 0, 120000000);
clks[IMX_IMG_AXI_CLK] = clk_hw_register_fixed_rate(NULL, "img_axi_clk_root", NULL, 0, 400000000);
clks[IMX_IMG_IPG_CLK] = clk_hw_register_fixed_rate(NULL, "img_ipg_clk_root", NULL, 0, 200000000);
clks[IMX_IMG_PXL_CLK] = clk_hw_register_fixed_rate(NULL, "img_pxl_clk_root", NULL, 0, 600000000);
clks[IMX_HSIO_AXI_CLK] = clk_hw_register_fixed_rate(NULL, "hsio_axi_clk_root", NULL, 0, 400000000);
clks[IMX_HSIO_PER_CLK] = clk_hw_register_fixed_rate(NULL, "hsio_per_clk_root", NULL, 0, 133333333);
clks[IMX_LSIO_MEM_CLK] = clk_hw_register_fixed_rate(NULL, "lsio_mem_clk_root", NULL, 0, 200000000);
clks[IMX_LSIO_BUS_CLK] = clk_hw_register_fixed_rate(NULL, "lsio_bus_clk_root", NULL, 0, 100000000);
/* ARM core */
clks[IMX_A35_CLK] = imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU, clk_cells);
imx_clk_scu("a35_clk", IMX_SC_R_A35, IMX_SC_PM_CLK_CPU);
imx_clk_scu("a53_clk", IMX_SC_R_A53, IMX_SC_PM_CLK_CPU);
imx_clk_scu("a72_clk", IMX_SC_R_A72, IMX_SC_PM_CLK_CPU);
/* LSIO SS */
clks[IMX_LSIO_PWM0_CLK] = imx_clk_scu("pwm0_clk", IMX_SC_R_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_PWM1_CLK] = imx_clk_scu("pwm1_clk", IMX_SC_R_PWM_1, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_PWM2_CLK] = imx_clk_scu("pwm2_clk", IMX_SC_R_PWM_2, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_PWM3_CLK] = imx_clk_scu("pwm3_clk", IMX_SC_R_PWM_3, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_PWM4_CLK] = imx_clk_scu("pwm4_clk", IMX_SC_R_PWM_4, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_PWM5_CLK] = imx_clk_scu("pwm5_clk", IMX_SC_R_PWM_5, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_PWM6_CLK] = imx_clk_scu("pwm6_clk", IMX_SC_R_PWM_6, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_PWM7_CLK] = imx_clk_scu("pwm7_clk", IMX_SC_R_PWM_7, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_GPT0_CLK] = imx_clk_scu("gpt0_clk", IMX_SC_R_GPT_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_GPT1_CLK] = imx_clk_scu("gpt1_clk", IMX_SC_R_GPT_1, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_GPT2_CLK] = imx_clk_scu("gpt2_clk", IMX_SC_R_GPT_2, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_GPT3_CLK] = imx_clk_scu("gpt3_clk", IMX_SC_R_GPT_3, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_GPT4_CLK] = imx_clk_scu("gpt4_clk", IMX_SC_R_GPT_4, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_FSPI0_CLK] = imx_clk_scu("fspi0_clk", IMX_SC_R_FSPI_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_LSIO_FSPI1_CLK] = imx_clk_scu("fspi1_clk", IMX_SC_R_FSPI_1, IMX_SC_PM_CLK_PER, clk_cells);
imx_clk_scu("pwm0_clk", IMX_SC_R_PWM_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("pwm1_clk", IMX_SC_R_PWM_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("pwm2_clk", IMX_SC_R_PWM_2, IMX_SC_PM_CLK_PER);
imx_clk_scu("pwm3_clk", IMX_SC_R_PWM_3, IMX_SC_PM_CLK_PER);
imx_clk_scu("pwm4_clk", IMX_SC_R_PWM_4, IMX_SC_PM_CLK_PER);
imx_clk_scu("pwm5_clk", IMX_SC_R_PWM_5, IMX_SC_PM_CLK_PER);
imx_clk_scu("pwm6_clk", IMX_SC_R_PWM_6, IMX_SC_PM_CLK_PER);
imx_clk_scu("pwm7_clk", IMX_SC_R_PWM_7, IMX_SC_PM_CLK_PER);
imx_clk_scu("gpt0_clk", IMX_SC_R_GPT_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("gpt1_clk", IMX_SC_R_GPT_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("gpt2_clk", IMX_SC_R_GPT_2, IMX_SC_PM_CLK_PER);
imx_clk_scu("gpt3_clk", IMX_SC_R_GPT_3, IMX_SC_PM_CLK_PER);
imx_clk_scu("gpt4_clk", IMX_SC_R_GPT_4, IMX_SC_PM_CLK_PER);
imx_clk_scu("fspi0_clk", IMX_SC_R_FSPI_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("fspi1_clk", IMX_SC_R_FSPI_1, IMX_SC_PM_CLK_PER);
/* ADMA SS */
clks[IMX_ADMA_UART0_CLK] = imx_clk_scu("uart0_clk", IMX_SC_R_UART_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_UART1_CLK] = imx_clk_scu("uart1_clk", IMX_SC_R_UART_1, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_UART2_CLK] = imx_clk_scu("uart2_clk", IMX_SC_R_UART_2, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_UART3_CLK] = imx_clk_scu("uart3_clk", IMX_SC_R_UART_3, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_SPI0_CLK] = imx_clk_scu("spi0_clk", IMX_SC_R_SPI_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_SPI1_CLK] = imx_clk_scu("spi1_clk", IMX_SC_R_SPI_1, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_SPI2_CLK] = imx_clk_scu("spi2_clk", IMX_SC_R_SPI_2, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_SPI3_CLK] = imx_clk_scu("spi3_clk", IMX_SC_R_SPI_3, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_CAN0_CLK] = imx_clk_scu("can0_clk", IMX_SC_R_CAN_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_I2C0_CLK] = imx_clk_scu("i2c0_clk", IMX_SC_R_I2C_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_I2C1_CLK] = imx_clk_scu("i2c1_clk", IMX_SC_R_I2C_1, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_I2C2_CLK] = imx_clk_scu("i2c2_clk", IMX_SC_R_I2C_2, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_I2C3_CLK] = imx_clk_scu("i2c3_clk", IMX_SC_R_I2C_3, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_FTM0_CLK] = imx_clk_scu("ftm0_clk", IMX_SC_R_FTM_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_FTM1_CLK] = imx_clk_scu("ftm1_clk", IMX_SC_R_FTM_1, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_ADC0_CLK] = imx_clk_scu("adc0_clk", IMX_SC_R_ADC_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_PWM_CLK] = imx_clk_scu("pwm_clk", IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_ADMA_LCD_CLK] = imx_clk_scu("lcd_clk", IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER, clk_cells);
/* DMA SS */
imx_clk_scu("uart0_clk", IMX_SC_R_UART_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("uart1_clk", IMX_SC_R_UART_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("uart2_clk", IMX_SC_R_UART_2, IMX_SC_PM_CLK_PER);
imx_clk_scu("uart3_clk", IMX_SC_R_UART_3, IMX_SC_PM_CLK_PER);
imx_clk_scu("uart4_clk", IMX_SC_R_UART_4, IMX_SC_PM_CLK_PER);
imx_clk_scu("sim0_clk", IMX_SC_R_EMVSIM_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("spi0_clk", IMX_SC_R_SPI_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("spi1_clk", IMX_SC_R_SPI_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("spi2_clk", IMX_SC_R_SPI_2, IMX_SC_PM_CLK_PER);
imx_clk_scu("spi3_clk", IMX_SC_R_SPI_3, IMX_SC_PM_CLK_PER);
imx_clk_scu("can0_clk", IMX_SC_R_CAN_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("can1_clk", IMX_SC_R_CAN_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("can2_clk", IMX_SC_R_CAN_2, IMX_SC_PM_CLK_PER);
imx_clk_scu("i2c0_clk", IMX_SC_R_I2C_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("i2c1_clk", IMX_SC_R_I2C_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("i2c2_clk", IMX_SC_R_I2C_2, IMX_SC_PM_CLK_PER);
imx_clk_scu("i2c3_clk", IMX_SC_R_I2C_3, IMX_SC_PM_CLK_PER);
imx_clk_scu("i2c4_clk", IMX_SC_R_I2C_4, IMX_SC_PM_CLK_PER);
imx_clk_scu("ftm0_clk", IMX_SC_R_FTM_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("ftm1_clk", IMX_SC_R_FTM_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("adc0_clk", IMX_SC_R_ADC_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("adc1_clk", IMX_SC_R_ADC_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("pwm_clk", IMX_SC_R_LCD_0_PWM_0, IMX_SC_PM_CLK_PER);
imx_clk_scu2("lcd_clk", lcd_sels, ARRAY_SIZE(lcd_sels), IMX_SC_R_LCD_0, IMX_SC_PM_CLK_PER);
imx_clk_scu2("lcd_pxl_clk", lcd_pxl_sels, ARRAY_SIZE(lcd_pxl_sels), IMX_SC_R_LCD_0, IMX_SC_PM_CLK_MISC0);
imx_clk_scu("lcd_pxl_bypass_div_clk", IMX_SC_R_LCD_0, IMX_SC_PM_CLK_BYPASS);
imx_clk_scu("elcdif_pll", IMX_SC_R_ELCDIF_PLL, IMX_SC_PM_CLK_PLL);
/* Audio SS */
imx_clk_scu("audio_pll0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_PLL);
imx_clk_scu("audio_pll1_clk", IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_PLL);
imx_clk_scu("audio_pll_div_clk0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_MISC0);
imx_clk_scu("audio_pll_div_clk1_clk", IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_MISC0);
imx_clk_scu("audio_rec_clk0_clk", IMX_SC_R_AUDIO_PLL_0, IMX_SC_PM_CLK_MISC1);
imx_clk_scu("audio_rec_clk1_clk", IMX_SC_R_AUDIO_PLL_1, IMX_SC_PM_CLK_MISC1);
/* Connectivity */
clks[IMX_CONN_SDHC0_CLK] = imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_CONN_SDHC1_CLK] = imx_clk_scu("sdhc1_clk", IMX_SC_R_SDHC_1, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_CONN_SDHC2_CLK] = imx_clk_scu("sdhc2_clk", IMX_SC_R_SDHC_2, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_CONN_ENET0_ROOT_CLK] = imx_clk_scu("enet0_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_CONN_ENET0_BYPASS_CLK] = imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS, clk_cells);
clks[IMX_CONN_ENET0_RGMII_CLK] = imx_clk_scu("enet0_rgmii_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0, clk_cells);
clks[IMX_CONN_ENET1_ROOT_CLK] = imx_clk_scu("enet1_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_CONN_ENET1_BYPASS_CLK] = imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS, clk_cells);
clks[IMX_CONN_ENET1_RGMII_CLK] = imx_clk_scu("enet1_rgmii_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0, clk_cells);
clks[IMX_CONN_GPMI_BCH_IO_CLK] = imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS, clk_cells);
clks[IMX_CONN_GPMI_BCH_CLK] = imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_CONN_USB2_ACLK] = imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_CONN_USB2_BUS_CLK] = imx_clk_scu("usb3_bus_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MST_BUS, clk_cells);
clks[IMX_CONN_USB2_LPM_CLK] = imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC, clk_cells);
imx_clk_scu("sdhc0_clk", IMX_SC_R_SDHC_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("sdhc1_clk", IMX_SC_R_SDHC_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("sdhc2_clk", IMX_SC_R_SDHC_2, IMX_SC_PM_CLK_PER);
imx_clk_scu("enet0_root_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_PER);
imx_clk_divider_gpr_scu("enet0_ref_div", "enet0_root_clk", IMX_SC_R_ENET_0, IMX_SC_C_CLKDIV);
imx_clk_mux_gpr_scu("enet0_rgmii_txc_sel", enet0_rgmii_txc_sels, ARRAY_SIZE(enet0_rgmii_txc_sels), IMX_SC_R_ENET_0, IMX_SC_C_TXCLK);
imx_clk_scu("enet0_bypass_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_BYPASS);
imx_clk_gate_gpr_scu("enet0_ref_50_clk", "clk_dummy", IMX_SC_R_ENET_0, IMX_SC_C_DISABLE_50, true);
imx_clk_scu("enet0_rgmii_rx_clk", IMX_SC_R_ENET_0, IMX_SC_PM_CLK_MISC0);
imx_clk_scu("enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_PER);
imx_clk_divider_gpr_scu("enet1_ref_div", "enet1_root_clk", IMX_SC_R_ENET_1, IMX_SC_C_CLKDIV);
imx_clk_mux_gpr_scu("enet1_rgmii_txc_sel", enet1_rgmii_txc_sels, ARRAY_SIZE(enet1_rgmii_txc_sels), IMX_SC_R_ENET_1, IMX_SC_C_TXCLK);
imx_clk_scu("enet1_bypass_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_BYPASS);
imx_clk_gate_gpr_scu("enet1_ref_50_clk", "clk_dummy", IMX_SC_R_ENET_1, IMX_SC_C_DISABLE_50, true);
imx_clk_scu("enet1_rgmii_rx_clk", IMX_SC_R_ENET_1, IMX_SC_PM_CLK_MISC0);
imx_clk_scu("gpmi_io_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_MST_BUS);
imx_clk_scu("gpmi_bch_clk", IMX_SC_R_NAND, IMX_SC_PM_CLK_PER);
imx_clk_scu("usb3_aclk_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_PER);
imx_clk_scu("usb3_bus_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MST_BUS);
imx_clk_scu("usb3_lpm_div", IMX_SC_R_USB_2, IMX_SC_PM_CLK_MISC);
/* Display controller SS */
clks[IMX_DC0_DISP0_CLK] = imx_clk_scu2("dc0_disp0_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0, clk_cells);
clks[IMX_DC0_DISP1_CLK] = imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1, clk_cells);
clks[IMX_DC0_PLL0_CLK] = imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL, clk_cells);
clks[IMX_DC0_PLL1_CLK] = imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL, clk_cells);
clks[IMX_DC0_BYPASS0_CLK] = imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS, clk_cells);
clks[IMX_DC0_BYPASS1_CLK] = imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS, clk_cells);
imx_clk_scu2("dc0_disp0_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC0);
imx_clk_scu2("dc0_disp1_clk", dc0_sels, ARRAY_SIZE(dc0_sels), IMX_SC_R_DC_0, IMX_SC_PM_CLK_MISC1);
imx_clk_scu("dc0_pll0_clk", IMX_SC_R_DC_0_PLL_0, IMX_SC_PM_CLK_PLL);
imx_clk_scu("dc0_pll1_clk", IMX_SC_R_DC_0_PLL_1, IMX_SC_PM_CLK_PLL);
imx_clk_scu("dc0_bypass0_clk", IMX_SC_R_DC_0_VIDEO0, IMX_SC_PM_CLK_BYPASS);
imx_clk_scu("dc0_bypass1_clk", IMX_SC_R_DC_0_VIDEO1, IMX_SC_PM_CLK_BYPASS);
imx_clk_scu2("dc1_disp0_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC0);
imx_clk_scu2("dc1_disp1_clk", dc1_sels, ARRAY_SIZE(dc1_sels), IMX_SC_R_DC_1, IMX_SC_PM_CLK_MISC1);
imx_clk_scu("dc1_pll0_clk", IMX_SC_R_DC_1_PLL_0, IMX_SC_PM_CLK_PLL);
imx_clk_scu("dc1_pll1_clk", IMX_SC_R_DC_1_PLL_1, IMX_SC_PM_CLK_PLL);
imx_clk_scu("dc1_bypass0_clk", IMX_SC_R_DC_1_VIDEO0, IMX_SC_PM_CLK_BYPASS);
imx_clk_scu("dc1_bypass1_clk", IMX_SC_R_DC_1_VIDEO1, IMX_SC_PM_CLK_BYPASS);
/* MIPI-LVDS SS */
clks[IMX_MIPI0_LVDS_PIXEL_CLK] = imx_clk_scu("mipi0_lvds_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2, clk_cells);
clks[IMX_MIPI0_LVDS_BYPASS_CLK] = imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS, clk_cells);
clks[IMX_MIPI0_LVDS_PHY_CLK] = imx_clk_scu("mipi0_lvds_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3, clk_cells);
clks[IMX_MIPI0_I2C0_CLK] = imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);
clks[IMX_MIPI0_I2C1_CLK] = imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells);
clks[IMX_MIPI0_PWM0_CLK] = imx_clk_scu("mipi0_pwm0_clk", IMX_SC_R_MIPI_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_MIPI1_LVDS_PIXEL_CLK] = imx_clk_scu("mipi1_lvds_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2, clk_cells);
clks[IMX_MIPI1_LVDS_BYPASS_CLK] = imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS, clk_cells);
clks[IMX_MIPI1_LVDS_PHY_CLK] = imx_clk_scu("mipi1_lvds_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3, clk_cells);
clks[IMX_MIPI1_I2C0_CLK] = imx_clk_scu("mipi1_i2c0_clk", IMX_SC_R_MIPI_1_I2C_0, IMX_SC_PM_CLK_MISC2, clk_cells);
clks[IMX_MIPI1_I2C1_CLK] = imx_clk_scu("mipi1_i2c1_clk", IMX_SC_R_MIPI_1_I2C_1, IMX_SC_PM_CLK_MISC2, clk_cells);
clks[IMX_MIPI1_PWM0_CLK] = imx_clk_scu("mipi1_pwm0_clk", IMX_SC_R_MIPI_1_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
imx_clk_scu("mipi0_bypass_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_BYPASS);
imx_clk_scu("mipi0_pixel_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("mipi0_lvds_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2);
imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS);
imx_clk_scu("mipi0_lvds_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3);
imx_clk_scu2("mipi0_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_MST_BUS);
imx_clk_scu2("mipi0_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_SLV_BUS);
imx_clk_scu2("mipi0_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PHY);
imx_clk_scu("mipi0_i2c0_clk", IMX_SC_R_MIPI_0_I2C_0, IMX_SC_PM_CLK_MISC2);
imx_clk_scu("mipi0_i2c1_clk", IMX_SC_R_MIPI_0_I2C_1, IMX_SC_PM_CLK_MISC2);
imx_clk_scu("mipi0_pwm0_clk", IMX_SC_R_MIPI_0_PWM_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("mipi1_bypass_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_BYPASS);
imx_clk_scu("mipi1_pixel_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("mipi1_lvds_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2);
imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS);
imx_clk_scu("mipi1_lvds_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3);
imx_clk_scu2("mipi1_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_MST_BUS);
imx_clk_scu2("mipi1_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_SLV_BUS);
imx_clk_scu2("mipi1_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PHY);
imx_clk_scu("mipi1_i2c0_clk", IMX_SC_R_MIPI_1_I2C_0, IMX_SC_PM_CLK_MISC2);
imx_clk_scu("mipi1_i2c1_clk", IMX_SC_R_MIPI_1_I2C_1, IMX_SC_PM_CLK_MISC2);
imx_clk_scu("mipi1_pwm0_clk", IMX_SC_R_MIPI_1_PWM_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("lvds0_i2c0_clk", IMX_SC_R_LVDS_0_I2C_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("lvds0_i2c1_clk", IMX_SC_R_LVDS_0_I2C_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("lvds0_pwm0_clk", IMX_SC_R_LVDS_0_PWM_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("lvds1_i2c0_clk", IMX_SC_R_LVDS_1_I2C_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("lvds1_i2c1_clk", IMX_SC_R_LVDS_1_I2C_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("lvds1_pwm0_clk", IMX_SC_R_LVDS_1_PWM_0, IMX_SC_PM_CLK_PER);
/* MIPI CSI SS */
clks[IMX_CSI0_CORE_CLK] = imx_clk_scu("mipi_csi0_core_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_CSI0_ESC_CLK] = imx_clk_scu("mipi_csi0_esc_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_MISC, clk_cells);
clks[IMX_CSI0_I2C0_CLK] = imx_clk_scu("mipi_csi0_i2c0_clk", IMX_SC_R_CSI_0_I2C_0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_CSI0_PWM0_CLK] = imx_clk_scu("mipi_csi0_pwm0_clk", IMX_SC_R_CSI_0_PWM_0, IMX_SC_PM_CLK_PER, clk_cells);
imx_clk_scu("mipi_csi0_core_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("mipi_csi0_esc_clk", IMX_SC_R_CSI_0, IMX_SC_PM_CLK_MISC);
imx_clk_scu("mipi_csi0_i2c0_clk", IMX_SC_R_CSI_0_I2C_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("mipi_csi0_pwm0_clk", IMX_SC_R_CSI_0_PWM_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("mipi_csi1_core_clk", IMX_SC_R_CSI_1, IMX_SC_PM_CLK_PER);
imx_clk_scu("mipi_csi1_esc_clk", IMX_SC_R_CSI_1, IMX_SC_PM_CLK_MISC);
imx_clk_scu("mipi_csi1_i2c0_clk", IMX_SC_R_CSI_1_I2C_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("mipi_csi1_pwm0_clk", IMX_SC_R_CSI_1_PWM_0, IMX_SC_PM_CLK_PER);
/* Parallel Interface SS */
imx_clk_scu("pi_dpll_clk", IMX_SC_R_PI_0_PLL, IMX_SC_PM_CLK_PLL);
imx_clk_scu2("pi_per_div_clk", pi_pll0_sels, ARRAY_SIZE(pi_pll0_sels), IMX_SC_R_PI_0, IMX_SC_PM_CLK_PER);
imx_clk_scu("pi_mclk_div_clk", IMX_SC_R_PI_0, IMX_SC_PM_CLK_MISC0);
imx_clk_scu("pi_i2c0_div_clk", IMX_SC_R_PI_0_I2C_0, IMX_SC_PM_CLK_PER);
/* GPU SS */
clks[IMX_GPU0_CORE_CLK] = imx_clk_scu("gpu_core0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER, clk_cells);
clks[IMX_GPU0_SHADER_CLK] = imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC, clk_cells);
imx_clk_scu("gpu_core0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_PER);
imx_clk_scu("gpu_shader0_clk", IMX_SC_R_GPU_0_PID0, IMX_SC_PM_CLK_MISC);
for (i = 0; i < clk_data->num; i++) {
if (IS_ERR(clks[i]))
pr_warn("i.MX clk %u: register failed with %ld\n",
i, PTR_ERR(clks[i]));
}
imx_clk_scu("gpu_core1_clk", IMX_SC_R_GPU_1_PID0, IMX_SC_PM_CLK_PER);
imx_clk_scu("gpu_shader1_clk", IMX_SC_R_GPU_1_PID0, IMX_SC_PM_CLK_MISC);
if (clk_cells == 2) {
ret = of_clk_add_hw_provider(ccm_node, imx_scu_of_clk_src_get, imx_scu_clks);
if (ret)
imx_clk_scu_unregister();
} else {
/*
* legacy binding code path doesn't unregister here because
* it will be removed later.
*/
ret = of_clk_add_hw_provider(ccm_node, of_clk_hw_onecell_get, clk_data);
}
/* CM40 SS */
imx_clk_scu("cm40_i2c_div", IMX_SC_R_M4_0_I2C, IMX_SC_PM_CLK_PER);
imx_clk_scu("cm40_lpuart_div", IMX_SC_R_M4_0_UART, IMX_SC_PM_CLK_PER);
/* CM41 SS */
imx_clk_scu("cm41_i2c_div", IMX_SC_R_M4_1_I2C, IMX_SC_PM_CLK_PER);
/* HDMI TX SS */
imx_clk_scu("hdmi_dig_pll_clk", IMX_SC_R_HDMI_PLL_0, IMX_SC_PM_CLK_PLL);
imx_clk_scu("hdmi_av_pll_clk", IMX_SC_R_HDMI_PLL_1, IMX_SC_PM_CLK_PLL);
imx_clk_scu2("hdmi_pixel_mux_clk", hdmi_sels, ARRAY_SIZE(hdmi_sels), IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC0);
imx_clk_scu2("hdmi_pixel_link_clk", hdmi_sels, ARRAY_SIZE(hdmi_sels), IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC1);
imx_clk_scu("hdmi_ipg_clk", IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC4);
imx_clk_scu("hdmi_i2c0_clk", IMX_SC_R_HDMI_I2C_0, IMX_SC_PM_CLK_MISC2);
imx_clk_scu("hdmi_hdp_core_clk", IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC2);
imx_clk_scu2("hdmi_pxl_clk", hdmi_sels, ARRAY_SIZE(hdmi_sels), IMX_SC_R_HDMI, IMX_SC_PM_CLK_MISC3);
imx_clk_scu("hdmi_i2s_bypass_clk", IMX_SC_R_HDMI_I2S, IMX_SC_PM_CLK_BYPASS);
imx_clk_scu("hdmi_i2s_clk", IMX_SC_R_HDMI_I2S, IMX_SC_PM_CLK_MISC0);
/* HDMI RX SS */
imx_clk_scu("hdmi_rx_i2s_bypass_clk", IMX_SC_R_HDMI_RX_BYPASS, IMX_SC_PM_CLK_MISC0);
imx_clk_scu("hdmi_rx_spdif_bypass_clk", IMX_SC_R_HDMI_RX_BYPASS, IMX_SC_PM_CLK_MISC1);
imx_clk_scu("hdmi_rx_bypass_clk", IMX_SC_R_HDMI_RX_BYPASS, IMX_SC_PM_CLK_MISC2);
imx_clk_scu("hdmi_rx_i2c0_clk", IMX_SC_R_HDMI_RX_I2C_0, IMX_SC_PM_CLK_MISC2);
imx_clk_scu("hdmi_rx_pwm_clk", IMX_SC_R_HDMI_RX_PWM_0, IMX_SC_PM_CLK_MISC2);
imx_clk_scu("hdmi_rx_spdif_clk", IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC0);
imx_clk_scu2("hdmi_rx_hd_ref_clk", hdmi_rx_sels, ARRAY_SIZE(hdmi_rx_sels), IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC1);
imx_clk_scu2("hdmi_rx_hd_core_clk", hdmi_rx_sels, ARRAY_SIZE(hdmi_rx_sels), IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC2);
imx_clk_scu2("hdmi_rx_pxl_clk", hdmi_rx_sels, ARRAY_SIZE(hdmi_rx_sels), IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC3);
imx_clk_scu("hdmi_rx_i2s_clk", IMX_SC_R_HDMI_RX, IMX_SC_PM_CLK_MISC4);
ret = of_clk_add_hw_provider(ccm_node, imx_scu_of_clk_src_get, imx_scu_clks);
if (ret)
imx_clk_scu_unregister();
return ret;
}
static const struct of_device_id imx8qxp_match[] = {
{ .compatible = "fsl,scu-clk", },
{ .compatible = "fsl,imx8qxp-clk", },
{ .compatible = "fsl,imx8qxp-clk", &imx_clk_scu_rsrc_imx8qxp, },
{ .compatible = "fsl,imx8qm-clk", &imx_clk_scu_rsrc_imx8qm, },
{ /* sentinel */ }
};

310
drivers/clk/imx/clk-scu.c
View File

@ -1,11 +1,12 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
* Copyright 2018-2021 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/firmware/imx/rsrc.h>
#include <linux/arm-smccc.h>
#include <linux/bsearch.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/of_platform.h>
@ -22,6 +23,7 @@
static struct imx_sc_ipc *ccm_ipc_handle;
static struct device_node *pd_np;
static struct platform_driver imx_clk_scu_driver;
static const struct imx_clk_scu_rsrc_table *rsrc_table;
struct imx_scu_clk_node {
const char *name;
@ -48,10 +50,28 @@ struct clk_scu {
u8 clk_type;
/* for state save&restore */
struct clk_hw *parent;
u8 parent_index;
bool is_enabled;
u32 rate;
};
/*
* struct clk_gpr_scu - Description of one SCU GPR clock
* @hw: the common clk_hw
* @rsrc_id: resource ID of this SCU clock
* @gpr_id: GPR ID index to control the divider
*/
struct clk_gpr_scu {
struct clk_hw hw;
u16 rsrc_id;
u8 gpr_id;
u8 flags;
bool gate_invert;
};
#define to_clk_gpr_scu(_hw) container_of(_hw, struct clk_gpr_scu, hw)
/*
* struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
* @hdr: SCU protocol header
@ -151,7 +171,26 @@ static inline struct clk_scu *to_clk_scu(struct clk_hw *hw)
return container_of(hw, struct clk_scu, hw);
}
int imx_clk_scu_init(struct device_node *np)
static inline int imx_scu_clk_search_cmp(const void *rsrc, const void *rsrc_p)
{
return *(u32 *)rsrc - *(u32 *)rsrc_p;
}
static bool imx_scu_clk_is_valid(u32 rsrc_id)
{
void *p;
if (!rsrc_table)
return true;
p = bsearch(&rsrc_id, rsrc_table->rsrc, rsrc_table->num,
sizeof(rsrc_table->rsrc[0]), imx_scu_clk_search_cmp);
return p != NULL;
}
int imx_clk_scu_init(struct device_node *np,
const struct imx_clk_scu_rsrc_table *data)
{
u32 clk_cells;
int ret, i;
@ -170,6 +209,8 @@ int imx_clk_scu_init(struct device_node *np)
pd_np = of_find_compatible_node(NULL, NULL, "fsl,scu-pd");
if (!pd_np)
return -EINVAL;
rsrc_table = data;
}
return platform_driver_register(&imx_clk_scu_driver);
@ -234,8 +275,10 @@ static int clk_scu_atf_set_cpu_rate(struct clk_hw *hw, unsigned long rate,
struct arm_smccc_res res;
unsigned long cluster_id;
if (clk->rsrc_id == IMX_SC_R_A35)
if (clk->rsrc_id == IMX_SC_R_A35 || clk->rsrc_id == IMX_SC_R_A53)
cluster_id = 0;
else if (clk->rsrc_id == IMX_SC_R_A72)
cluster_id = 1;
else
return -EINVAL;
@ -296,6 +339,8 @@ static u8 clk_scu_get_parent(struct clk_hw *hw)
return 0;
}
clk->parent_index = msg.data.resp.parent;
return msg.data.resp.parent;
}
@ -304,6 +349,7 @@ static int clk_scu_set_parent(struct clk_hw *hw, u8 index)
struct clk_scu *clk = to_clk_scu(hw);
struct imx_sc_msg_set_clock_parent msg;
struct imx_sc_rpc_msg *hdr = &msg.hdr;
int ret;
hdr->ver = IMX_SC_RPC_VERSION;
hdr->svc = IMX_SC_RPC_SVC_PM;
@ -314,7 +360,16 @@ static int clk_scu_set_parent(struct clk_hw *hw, u8 index)
msg.clk = clk->clk_type;
msg.parent = index;
return imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
ret = imx_scu_call_rpc(ccm_ipc_handle, &msg, true);
if (ret) {
pr_err("%s: failed to set clock parent %d\n",
clk_hw_get_name(hw), ret);
return ret;
}
clk->parent_index = index;
return 0;
}
static int sc_pm_clock_enable(struct imx_sc_ipc *ipc, u16 resource,
@ -386,6 +441,12 @@ static const struct clk_ops clk_scu_cpu_ops = {
.unprepare = clk_scu_unprepare,
};
static const struct clk_ops clk_scu_pi_ops = {
.recalc_rate = clk_scu_recalc_rate,
.round_rate = clk_scu_round_rate,
.set_rate = clk_scu_set_rate,
};
struct clk_hw *__imx_clk_scu(struct device *dev, const char *name,
const char * const *parents, int num_parents,
u32 rsrc_id, u8 clk_type)
@ -404,8 +465,10 @@ struct clk_hw *__imx_clk_scu(struct device *dev, const char *name,
init.name = name;
init.ops = &clk_scu_ops;
if (rsrc_id == IMX_SC_R_A35)
if (rsrc_id == IMX_SC_R_A35 || rsrc_id == IMX_SC_R_A53 || rsrc_id == IMX_SC_R_A72)
init.ops = &clk_scu_cpu_ops;
else if (rsrc_id == IMX_SC_R_PI_0_PLL)
init.ops = &clk_scu_pi_ops;
else
init.ops = &clk_scu_ops;
init.parent_names = parents;
@ -458,15 +521,19 @@ static int imx_clk_scu_probe(struct platform_device *pdev)
struct clk_hw *hw;
int ret;
pm_runtime_set_suspended(dev);
pm_runtime_set_autosuspend_delay(dev, 50);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_enable(dev);
if (!((clk->rsrc == IMX_SC_R_A35) || (clk->rsrc == IMX_SC_R_A53) ||
(clk->rsrc == IMX_SC_R_A72))) {
pm_runtime_set_suspended(dev);
pm_runtime_set_autosuspend_delay(dev, 50);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_enable(dev);
ret = pm_runtime_get_sync(dev);
if (ret) {
pm_runtime_disable(dev);
return ret;
ret = pm_runtime_get_sync(dev);
if (ret) {
pm_genpd_remove_device(dev);
pm_runtime_disable(dev);
return ret;
}
}
hw = __imx_clk_scu(dev, clk->name, clk->parents, clk->num_parents,
@ -479,8 +546,11 @@ static int imx_clk_scu_probe(struct platform_device *pdev)
clk->hw = hw;
list_add_tail(&clk->node, &imx_scu_clks[clk->rsrc]);
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_put_autosuspend(&pdev->dev);
if (!((clk->rsrc == IMX_SC_R_A35) || (clk->rsrc == IMX_SC_R_A53) ||
(clk->rsrc == IMX_SC_R_A72))) {
pm_runtime_mark_last_busy(&pdev->dev);
pm_runtime_put_autosuspend(&pdev->dev);
}
dev_dbg(dev, "register SCU clock rsrc:%d type:%d\n", clk->rsrc,
clk->clk_type);
@ -491,10 +561,28 @@ static int imx_clk_scu_probe(struct platform_device *pdev)
static int __maybe_unused imx_clk_scu_suspend(struct device *dev)
{
struct clk_scu *clk = dev_get_drvdata(dev);
u32 rsrc_id = clk->rsrc_id;
clk->rate = clk_hw_get_rate(&clk->hw);
if ((rsrc_id == IMX_SC_R_A35) || (rsrc_id == IMX_SC_R_A53) ||
(rsrc_id == IMX_SC_R_A72))
return 0;
clk->parent = clk_hw_get_parent(&clk->hw);
/* DC SS needs to handle bypass clock using non-cached clock rate */
if (clk->rsrc_id == IMX_SC_R_DC_0_VIDEO0 ||
clk->rsrc_id == IMX_SC_R_DC_0_VIDEO1 ||
clk->rsrc_id == IMX_SC_R_DC_1_VIDEO0 ||
clk->rsrc_id == IMX_SC_R_DC_1_VIDEO1)
clk->rate = clk_scu_recalc_rate(&clk->hw, 0);
else
clk->rate = clk_hw_get_rate(&clk->hw);
clk->is_enabled = clk_hw_is_enabled(&clk->hw);
if (clk->parent)
dev_dbg(dev, "save parent %s idx %u\n", clk_hw_get_name(clk->parent),
clk->parent_index);
if (clk->rate)
dev_dbg(dev, "save rate %d\n", clk->rate);
@ -507,15 +595,27 @@ static int __maybe_unused imx_clk_scu_suspend(struct device *dev)
static int __maybe_unused imx_clk_scu_resume(struct device *dev)
{
struct clk_scu *clk = dev_get_drvdata(dev);
u32 rsrc_id = clk->rsrc_id;
int ret = 0;
if ((rsrc_id == IMX_SC_R_A35) || (rsrc_id == IMX_SC_R_A53) ||
(rsrc_id == IMX_SC_R_A72))
return 0;
if (clk->parent) {
ret = clk_scu_set_parent(&clk->hw, clk->parent_index);
dev_dbg(dev, "restore parent %s idx %u %s\n",
clk_hw_get_name(clk->parent),
clk->parent_index, !ret ? "success" : "failed");
}
if (clk->rate) {
ret = clk_scu_set_rate(&clk->hw, clk->rate, 0);
dev_dbg(dev, "restore rate %d %s\n", clk->rate,
!ret ? "success" : "failed");
}
if (clk->is_enabled) {
if (clk->is_enabled && rsrc_id != IMX_SC_R_PI_0_PLL) {
ret = clk_scu_prepare(&clk->hw);
dev_dbg(dev, "restore enabled state %s\n",
!ret ? "success" : "failed");
@ -567,6 +667,9 @@ struct clk_hw *imx_clk_scu_alloc_dev(const char *name,
struct platform_device *pdev;
int ret;
if (!imx_scu_clk_is_valid(rsrc_id))
return ERR_PTR(-EINVAL);
pdev = platform_device_alloc(name, PLATFORM_DEVID_NONE);
if (!pdev) {
pr_err("%s: failed to allocate scu clk dev rsrc %d type %d\n",
@ -605,3 +708,176 @@ void imx_clk_scu_unregister(void)
}
}
}
static unsigned long clk_gpr_div_scu_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
unsigned long rate = 0;
u32 val;
int err;
err = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
clk->gpr_id, &val);
rate = val ? parent_rate / 2 : parent_rate;
return err ? 0 : rate;
}
static long clk_gpr_div_scu_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
if (rate < *prate)
rate = *prate / 2;
else
rate = *prate;
return rate;
}
static int clk_gpr_div_scu_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
uint32_t val;
int err;
val = (rate < parent_rate) ? 1 : 0;
err = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
clk->gpr_id, val);
return err ? -EINVAL : 0;
}
static const struct clk_ops clk_gpr_div_scu_ops = {
.recalc_rate = clk_gpr_div_scu_recalc_rate,
.round_rate = clk_gpr_div_scu_round_rate,
.set_rate = clk_gpr_div_scu_set_rate,
};
static u8 clk_gpr_mux_scu_get_parent(struct clk_hw *hw)
{
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
u32 val = 0;
imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
clk->gpr_id, &val);
return (u8)val;
}
static int clk_gpr_mux_scu_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
clk->gpr_id, index);
}
static const struct clk_ops clk_gpr_mux_scu_ops = {
.get_parent = clk_gpr_mux_scu_get_parent,
.set_parent = clk_gpr_mux_scu_set_parent,
};
static int clk_gpr_gate_scu_prepare(struct clk_hw *hw)
{
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
return imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
clk->gpr_id, !clk->gate_invert);
}
static void clk_gpr_gate_scu_unprepare(struct clk_hw *hw)
{
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
int ret;
ret = imx_sc_misc_set_control(ccm_ipc_handle, clk->rsrc_id,
clk->gpr_id, clk->gate_invert);
if (ret)
pr_err("%s: clk unprepare failed %d\n", clk_hw_get_name(hw),
ret);
}
static int clk_gpr_gate_scu_is_prepared(struct clk_hw *hw)
{
struct clk_gpr_scu *clk = to_clk_gpr_scu(hw);
int ret;
u32 val;
ret = imx_sc_misc_get_control(ccm_ipc_handle, clk->rsrc_id,
clk->gpr_id, &val);
if (ret)
return ret;
return clk->gate_invert ? !val : val;
}
static const struct clk_ops clk_gpr_gate_scu_ops = {
.prepare = clk_gpr_gate_scu_prepare,
.unprepare = clk_gpr_gate_scu_unprepare,
.is_prepared = clk_gpr_gate_scu_is_prepared,
};
struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name,
int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags,
bool invert)
{
struct imx_scu_clk_node *clk_node;
struct clk_gpr_scu *clk;
struct clk_hw *hw;
struct clk_init_data init;
int ret;
if (rsrc_id >= IMX_SC_R_LAST || gpr_id >= IMX_SC_C_LAST)
return ERR_PTR(-EINVAL);
clk_node = kzalloc(sizeof(*clk_node), GFP_KERNEL);
if (!clk_node)
return ERR_PTR(-ENOMEM);
if (!imx_scu_clk_is_valid(rsrc_id))
return ERR_PTR(-EINVAL);
clk = kzalloc(sizeof(*clk), GFP_KERNEL);
if (!clk) {
kfree(clk_node);
return ERR_PTR(-ENOMEM);
}
clk->rsrc_id = rsrc_id;
clk->gpr_id = gpr_id;
clk->flags = flags;
clk->gate_invert = invert;
if (flags & IMX_SCU_GPR_CLK_GATE)
init.ops = &clk_gpr_gate_scu_ops;
if (flags & IMX_SCU_GPR_CLK_DIV)
init.ops = &clk_gpr_div_scu_ops;
if (flags & IMX_SCU_GPR_CLK_MUX)
init.ops = &clk_gpr_mux_scu_ops;
init.flags = 0;
init.name = name;
init.parent_names = parent_name;
init.num_parents = num_parents;
clk->hw.init = &init;
hw = &clk->hw;
ret = clk_hw_register(NULL, hw);
if (ret) {
kfree(clk);
kfree(clk_node);
hw = ERR_PTR(ret);
} else {
clk_node->hw = hw;
clk_node->clk_type = gpr_id;
list_add_tail(&clk_node->node, &imx_scu_clks[rsrc_id]);
}
return hw;
}

56
drivers/clk/imx/clk-scu.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
* Copyright 2018-2021 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
@ -10,10 +10,22 @@
#include <linux/firmware/imx/sci.h>
#include <linux/of.h>
#define IMX_SCU_GPR_CLK_GATE BIT(0)
#define IMX_SCU_GPR_CLK_DIV BIT(1)
#define IMX_SCU_GPR_CLK_MUX BIT(2)
struct imx_clk_scu_rsrc_table {
const u32 *rsrc;
u8 num;
};
extern struct list_head imx_scu_clks[];
extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops;
extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp;
extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm;
int imx_clk_scu_init(struct device_node *np);
int imx_clk_scu_init(struct device_node *np,
const struct imx_clk_scu_rsrc_table *data);
struct clk_hw *imx_scu_of_clk_src_get(struct of_phandle_args *clkspec,
void *data);
struct clk_hw *imx_clk_scu_alloc_dev(const char *name,
@ -31,23 +43,20 @@ struct clk_hw *__imx_clk_lpcg_scu(struct device *dev, const char *name,
void __iomem *reg, u8 bit_idx, bool hw_gate);
void imx_clk_lpcg_scu_unregister(struct clk_hw *hw);
struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name,
int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags,
bool invert);
static inline struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id,
u8 clk_type, u8 clk_cells)
u8 clk_type)
{
if (clk_cells == 2)
return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type);
else
return __imx_clk_scu(NULL, name, NULL, 0, rsrc_id, clk_type);
return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type);
}
static inline struct clk_hw *imx_clk_scu2(const char *name, const char * const *parents,
int num_parents, u32 rsrc_id, u8 clk_type,
u8 clk_cells)
int num_parents, u32 rsrc_id, u8 clk_type)
{
if (clk_cells == 2)
return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type);
else
return __imx_clk_scu(NULL, name, parents, num_parents, rsrc_id, clk_type);
return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type);
}
static inline struct clk_hw *imx_clk_lpcg_scu_dev(struct device *dev, const char *name,
@ -65,4 +74,25 @@ static inline struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *pare
return __imx_clk_lpcg_scu(NULL, name, parent_name, flags, reg,
bit_idx, hw_gate);
}
static inline struct clk_hw *imx_clk_gate_gpr_scu(const char *name, const char *parent_name,
u32 rsrc_id, u8 gpr_id, bool invert)
{
return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id,
IMX_SCU_GPR_CLK_GATE, invert);
}
static inline struct clk_hw *imx_clk_divider_gpr_scu(const char *name, const char *parent_name,
u32 rsrc_id, u8 gpr_id)
{
return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id,
IMX_SCU_GPR_CLK_DIV, 0);
}
static inline struct clk_hw *imx_clk_mux_gpr_scu(const char *name, const char * const *parent_names,
int num_parents, u32 rsrc_id, u8 gpr_id)
{
return __imx_clk_gpr_scu(name, parent_names, num_parents, rsrc_id,
gpr_id, IMX_SCU_GPR_CLK_MUX, 0);
}
#endif

4
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
View File

@ -817,10 +817,10 @@ static void __init sun8i_v3_v3s_ccu_init(struct device_node *node,
return;
}
/* Force the PLL-Audio-1x divider to 4 */
/* Force the PLL-Audio-1x divider to 1 */
val = readl(reg + SUN8I_V3S_PLL_AUDIO_REG);
val &= ~GENMASK(19, 16);
writel(val | (3 << 16), reg + SUN8I_V3S_PLL_AUDIO_REG);
writel(val, reg + SUN8I_V3S_PLL_AUDIO_REG);
sunxi_ccu_probe(node, reg, ccu_desc);
}

80
drivers/clk/tegra/clk-periph-gate.c
View File

@ -48,36 +48,45 @@ static int clk_periph_is_enabled(struct clk_hw *hw)
return state;
}
static int clk_periph_enable(struct clk_hw *hw)
static void clk_periph_enable_locked(struct clk_hw *hw)
{
struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
unsigned long flags = 0;
spin_lock_irqsave(&periph_ref_lock, flags);
gate->enable_refcnt[gate->clk_num]++;
if (gate->enable_refcnt[gate->clk_num] > 1) {
spin_unlock_irqrestore(&periph_ref_lock, flags);
return 0;
}
write_enb_set(periph_clk_to_bit(gate), gate);
udelay(2);
if (!(gate->flags & TEGRA_PERIPH_NO_RESET) &&
!(gate->flags & TEGRA_PERIPH_MANUAL_RESET)) {
if (read_rst(gate) & periph_clk_to_bit(gate)) {
udelay(5); /* reset propogation delay */
write_rst_clr(periph_clk_to_bit(gate), gate);
}
}
if (gate->flags & TEGRA_PERIPH_WAR_1005168) {
writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE);
udelay(1);
writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE);
}
}
static void clk_periph_disable_locked(struct clk_hw *hw)
{
struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
/*
* If peripheral is in the APB bus then read the APB bus to
* flush the write operation in apb bus. This will avoid the
* peripheral access after disabling clock
*/
if (gate->flags & TEGRA_PERIPH_ON_APB)
tegra_read_chipid();
write_enb_clr(periph_clk_to_bit(gate), gate);
}
static int clk_periph_enable(struct clk_hw *hw)
{
struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
unsigned long flags = 0;
spin_lock_irqsave(&periph_ref_lock, flags);
if (!gate->enable_refcnt[gate->clk_num]++)
clk_periph_enable_locked(hw);
spin_unlock_irqrestore(&periph_ref_lock, flags);
@ -91,21 +100,28 @@ static void clk_periph_disable(struct clk_hw *hw)
spin_lock_irqsave(&periph_ref_lock, flags);
gate->enable_refcnt[gate->clk_num]--;
if (gate->enable_refcnt[gate->clk_num] > 0) {
spin_unlock_irqrestore(&periph_ref_lock, flags);
return;
}
WARN_ON(!gate->enable_refcnt[gate->clk_num]);
if (--gate->enable_refcnt[gate->clk_num] == 0)
clk_periph_disable_locked(hw);
spin_unlock_irqrestore(&periph_ref_lock, flags);
}
static void clk_periph_disable_unused(struct clk_hw *hw)
{
struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw);
unsigned long flags = 0;
spin_lock_irqsave(&periph_ref_lock, flags);
/*
* If peripheral is in the APB bus then read the APB bus to
* flush the write operation in apb bus. This will avoid the
* peripheral access after disabling clock
* Some clocks are duplicated and some of them are marked as critical,
* like fuse and fuse_burn for example, thus the enable_refcnt will
* be non-zero here if the "unused" duplicate is disabled by CCF.
*/
if (gate->flags & TEGRA_PERIPH_ON_APB)
tegra_read_chipid();
write_enb_clr(periph_clk_to_bit(gate), gate);
if (!gate->enable_refcnt[gate->clk_num])
clk_periph_disable_locked(hw);
spin_unlock_irqrestore(&periph_ref_lock, flags);
}
@ -114,6 +130,7 @@ const struct clk_ops tegra_clk_periph_gate_ops = {
.is_enabled = clk_periph_is_enabled,
.enable = clk_periph_enable,
.disable = clk_periph_disable,
.disable_unused = clk_periph_disable_unused,
};
struct clk *tegra_clk_register_periph_gate(const char *name,
@ -148,9 +165,6 @@ struct clk *tegra_clk_register_periph_gate(const char *name,
gate->enable_refcnt = enable_refcnt;
gate->regs = pregs;
if (read_enb(gate) & periph_clk_to_bit(gate))
enable_refcnt[clk_num]++;
/* Data in .init is copied by clk_register(), so stack variable OK */
gate->hw.init = &init;

11
drivers/clk/tegra/clk-periph.c
View File

@ -100,6 +100,15 @@ static void clk_periph_disable(struct clk_hw *hw)
gate_ops->disable(gate_hw);
}
static void clk_periph_disable_unused(struct clk_hw *hw)
{
struct tegra_clk_periph *periph = to_clk_periph(hw);
const struct clk_ops *gate_ops = periph->gate_ops;
struct clk_hw *gate_hw = &periph->gate.hw;
gate_ops->disable_unused(gate_hw);
}
static void clk_periph_restore_context(struct clk_hw *hw)
{
struct tegra_clk_periph *periph = to_clk_periph(hw);
@ -126,6 +135,7 @@ const struct clk_ops tegra_clk_periph_ops = {
.is_enabled = clk_periph_is_enabled,
.enable = clk_periph_enable,
.disable = clk_periph_disable,
.disable_unused = clk_periph_disable_unused,
.restore_context = clk_periph_restore_context,
};
@ -135,6 +145,7 @@ static const struct clk_ops tegra_clk_periph_nodiv_ops = {
.is_enabled = clk_periph_is_enabled,
.enable = clk_periph_enable,
.disable = clk_periph_disable,
.disable_unused = clk_periph_disable_unused,
.restore_context = clk_periph_restore_context,
};

12
drivers/clk/tegra/clk-pll.c
View File

@ -558,6 +558,9 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
u32 p_div = 0;
int ret;
if (!rate)
return -EINVAL;
switch (parent_rate) {
case 12000000:
case 26000000:
@ -1131,7 +1134,8 @@ static int clk_pllu_enable(struct clk_hw *hw)
if (pll->lock)
spin_lock_irqsave(pll->lock, flags);
_clk_pll_enable(hw);
if (!clk_pll_is_enabled(hw))
_clk_pll_enable(hw);
ret = clk_pll_wait_for_lock(pll);
if (ret < 0)
@ -1748,15 +1752,13 @@ static int clk_pllu_tegra114_enable(struct clk_hw *hw)
return -EINVAL;
}
if (clk_pll_is_enabled(hw))
return 0;
input_rate = clk_hw_get_rate(__clk_get_hw(osc));
if (pll->lock)
spin_lock_irqsave(pll->lock, flags);
_clk_pll_enable(hw);
if (!clk_pll_is_enabled(hw))
_clk_pll_enable(hw);
ret = clk_pll_wait_for_lock(pll);
if (ret < 0)

6
drivers/clk/tegra/clk-tegra-periph.c
View File

@ -712,9 +712,9 @@ static struct tegra_periph_init_data periph_clks[] = {
MUX8("ndflash", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash_8),
MUX8("ndspeed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed_8),
MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi),
MUX8("extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, 0, tegra_clk_extern1),
MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, tegra_clk_extern2),
MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, tegra_clk_extern3),
MUX8("extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, TEGRA_PERIPH_NO_RESET, tegra_clk_extern1),
MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, TEGRA_PERIPH_NO_RESET, tegra_clk_extern2),
MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, TEGRA_PERIPH_NO_RESET, tegra_clk_extern3),
MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm),
MUX8("soc_therm", mux_clkm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm_8),
MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 164, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8),

18
drivers/clk/tegra/clk-tegra-super-cclk.c
View File

@ -25,6 +25,8 @@
#define SUPER_CDIV_ENB BIT(31)
#define TSENSOR_SLOWDOWN BIT(23)
static struct tegra_clk_super_mux *cclk_super;
static bool cclk_on_pllx;
@ -47,10 +49,20 @@ static int cclk_super_set_rate(struct clk_hw *hw, unsigned long rate,
static unsigned long cclk_super_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
if (cclk_super_get_parent(hw) == PLLX_INDEX)
return parent_rate;
struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
u32 val = readl_relaxed(super->reg);
unsigned int div2;
return tegra_clk_super_ops.recalc_rate(hw, parent_rate);
/* check whether thermal throttling is active */
if (val & TSENSOR_SLOWDOWN)
div2 = 1;
else
div2 = 0;
if (cclk_super_get_parent(hw) == PLLX_INDEX)
return parent_rate >> div2;
return tegra_clk_super_ops.recalc_rate(hw, parent_rate) >> div2;
}
static int cclk_super_determine_rate(struct clk_hw *hw,

4
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
View File

@ -537,7 +537,7 @@ static void get_alignment_from_dt(struct device *dev,
static int get_alignment_from_regulator(struct device *dev,
struct rail_alignment *align)
{
struct regulator *reg = devm_regulator_get(dev, "vdd-cpu");
struct regulator *reg = regulator_get(dev, "vdd-cpu");
if (IS_ERR(reg))
return PTR_ERR(reg);
@ -545,7 +545,7 @@ static int get_alignment_from_regulator(struct device *dev,
align->offset_uv = regulator_list_voltage(reg, 0);
align->step_uv = regulator_get_linear_step(reg);
devm_regulator_put(reg);
regulator_put(reg);
return 0;
}

4
drivers/clk/tegra/clk-tegra124-emc.c
View File

@ -249,8 +249,10 @@ static int emc_set_timing(struct tegra_clk_emc *tegra,
div = timing->parent_rate / (timing->rate / 2) - 2;
err = tegra->prepare_timing_change(emc, timing->rate);
if (err)
if (err) {
clk_disable_unprepare(timing->parent);
return err;
}
spin_lock_irqsave(tegra->lock, flags);

6
drivers/clk/tegra/clk-tegra20.c
View File

@ -1021,9 +1021,9 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 },
{ TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 },
{ TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 0 },
{ TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 240000000, 0 },
{ TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 240000000, 0 },
{ TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 240000000, 0 },
{ TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 0 },
{ TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 120000000, 0 },
{ TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 120000000, 0 },
{ TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 0 },
{ TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 },
{ TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },

6
drivers/clk/tegra/clk-tegra30.c
View File

@ -930,7 +930,7 @@ static void __init tegra30_super_clk_init(void)
/* CCLKG */
clk = tegra_clk_register_super_cclk("cclk_g", cclk_g_parents,
ARRAY_SIZE(cclk_g_parents),
CLK_SET_RATE_PARENT,
CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
clk_base + CCLKG_BURST_POLICY,
0, NULL);
clks[TEGRA30_CLK_CCLK_G] = clk;
@ -1006,7 +1006,7 @@ static struct tegra_periph_init_data tegra_periph_clk_list[] = {
TEGRA_INIT_DATA_MUX("dam0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, 0, TEGRA30_CLK_DAM0),
TEGRA_INIT_DATA_MUX("dam1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, 0, TEGRA30_CLK_DAM1),
TEGRA_INIT_DATA_MUX("dam2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, 0, TEGRA30_CLK_DAM2),
TEGRA_INIT_DATA_INT("3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, TEGRA_PERIPH_MANUAL_RESET, TEGRA30_CLK_GR3D2),
TEGRA_INIT_DATA_INT("3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, 0, TEGRA30_CLK_GR3D2),
TEGRA_INIT_DATA_INT("se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, 0, TEGRA30_CLK_SE),
TEGRA_INIT_DATA_MUX8("hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA30_CLK_HDMI),
TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_PWM),
@ -1245,7 +1245,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 },
{ TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 },
{ TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 },
{ TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 600000000, 0 },
{ TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 300000000, 0 },
{ TEGRA30_CLK_SPDIF_IN_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
{ TEGRA30_CLK_I2S0_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
{ TEGRA30_CLK_I2S1_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },

4
drivers/clk/tegra/clk.h
View File

@ -553,9 +553,6 @@ struct tegra_clk_periph_regs {
* Flags:
* TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed
* for this module.
* TEGRA_PERIPH_MANUAL_RESET - This flag indicates not to reset module
* after clock enable and driver for the module is responsible for
* doing reset.
* TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the
* bus to flush the write operation in apb bus. This flag indicates
* that this peripheral is in apb bus.
@ -577,7 +574,6 @@ struct tegra_clk_periph_gate {
#define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309
#define TEGRA_PERIPH_NO_RESET BIT(0)
#define TEGRA_PERIPH_MANUAL_RESET BIT(1)
#define TEGRA_PERIPH_ON_APB BIT(2)
#define TEGRA_PERIPH_WAR_1005168 BIT(3)
#define TEGRA_PERIPH_NO_DIV BIT(4)

6
drivers/clocksource/Kconfig
View File

@ -360,7 +360,7 @@ config ARM_GLOBAL_TIMER
config ARM_TIMER_SP804
bool "Support for Dual Timer SP804 module" if COMPILE_TEST
depends on GENERIC_SCHED_CLOCK && CLKDEV_LOOKUP
depends on GENERIC_SCHED_CLOCK && HAVE_CLK
select CLKSRC_MMIO
select TIMER_OF if OF
@ -570,12 +570,12 @@ config H8300_TPU
config CLKSRC_IMX_GPT
bool "Clocksource using i.MX GPT" if COMPILE_TEST
depends on (ARM || ARM64) && CLKDEV_LOOKUP
depends on (ARM || ARM64) && HAVE_CLK
select CLKSRC_MMIO
config CLKSRC_IMX_TPM
bool "Clocksource using i.MX TPM" if COMPILE_TEST
depends on (ARM || ARM64) && CLKDEV_LOOKUP
depends on (ARM || ARM64) && HAVE_CLK
select CLKSRC_MMIO
select TIMER_OF
help

4
drivers/mmc/host/Kconfig
View File

@ -329,7 +329,7 @@ config MMC_SDHCI_S3C
config MMC_SDHCI_PXAV3
tristate "Marvell MMP2 SD Host Controller support (PXAV3)"
depends on CLKDEV_LOOKUP
depends on HAVE_CLK
depends on MMC_SDHCI_PLTFM
depends on ARCH_BERLIN || ARCH_MMP || ARCH_MVEBU || COMPILE_TEST
default CPU_MMP2
@ -342,7 +342,7 @@ config MMC_SDHCI_PXAV3
config MMC_SDHCI_PXAV2
tristate "Marvell PXA9XX SD Host Controller support (PXAV2)"
depends on CLKDEV_LOOKUP
depends on HAVE_CLK
depends on MMC_SDHCI_PLTFM
depends on ARCH_MMP || COMPILE_TEST
default CPU_PXA910

5
drivers/soc/tegra/pmc.c
View File

@ -743,11 +743,6 @@ out:
return err;
}
int __weak tegra210_clk_handle_mbist_war(unsigned int id)
{
return 0;
}
static int tegra_powergate_power_up(struct tegra_powergate *pg,
bool disable_clocks)
{

2
drivers/staging/board/Kconfig
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
config STAGING_BOARD
bool "Staging Board Support"
depends on OF_ADDRESS && OF_IRQ && CLKDEV_LOOKUP
depends on OF_ADDRESS && OF_IRQ && HAVE_CLK
help
Staging board base is to support continuous upstream
in-tree development and integration of platform devices.

128
include/dt-bindings/clock/imx8-clock.h
View File

@ -7,134 +7,6 @@
#ifndef __DT_BINDINGS_CLOCK_IMX_H
#define __DT_BINDINGS_CLOCK_IMX_H
/* SCU Clocks */
#define IMX_CLK_DUMMY 0
/* CPU */
#define IMX_A35_CLK 1
/* LSIO SS */
#define IMX_LSIO_MEM_CLK 2
#define IMX_LSIO_BUS_CLK 3
#define IMX_LSIO_PWM0_CLK 10
#define IMX_LSIO_PWM1_CLK 11
#define IMX_LSIO_PWM2_CLK 12
#define IMX_LSIO_PWM3_CLK 13
#define IMX_LSIO_PWM4_CLK 14
#define IMX_LSIO_PWM5_CLK 15
#define IMX_LSIO_PWM6_CLK 16
#define IMX_LSIO_PWM7_CLK 17
#define IMX_LSIO_GPT0_CLK 18
#define IMX_LSIO_GPT1_CLK 19
#define IMX_LSIO_GPT2_CLK 20
#define IMX_LSIO_GPT3_CLK 21
#define IMX_LSIO_GPT4_CLK 22
#define IMX_LSIO_FSPI0_CLK 23
#define IMX_LSIO_FSPI1_CLK 24
/* Connectivity SS */
#define IMX_CONN_AXI_CLK_ROOT 30
#define IMX_CONN_AHB_CLK_ROOT 31
#define IMX_CONN_IPG_CLK_ROOT 32
#define IMX_CONN_SDHC0_CLK 40
#define IMX_CONN_SDHC1_CLK 41
#define IMX_CONN_SDHC2_CLK 42
#define IMX_CONN_ENET0_ROOT_CLK 43
#define IMX_CONN_ENET0_BYPASS_CLK 44
#define IMX_CONN_ENET0_RGMII_CLK 45
#define IMX_CONN_ENET1_ROOT_CLK 46
#define IMX_CONN_ENET1_BYPASS_CLK 47
#define IMX_CONN_ENET1_RGMII_CLK 48
#define IMX_CONN_GPMI_BCH_IO_CLK 49
#define IMX_CONN_GPMI_BCH_CLK 50
#define IMX_CONN_USB2_ACLK 51
#define IMX_CONN_USB2_BUS_CLK 52
#define IMX_CONN_USB2_LPM_CLK 53
/* HSIO SS */
#define IMX_HSIO_AXI_CLK 60
#define IMX_HSIO_PER_CLK 61
/* Display controller SS */
#define IMX_DC_AXI_EXT_CLK 70
#define IMX_DC_AXI_INT_CLK 71
#define IMX_DC_CFG_CLK 72
#define IMX_DC0_PLL0_CLK 80
#define IMX_DC0_PLL1_CLK 81
#define IMX_DC0_DISP0_CLK 82
#define IMX_DC0_DISP1_CLK 83
#define IMX_DC0_BYPASS0_CLK 84
#define IMX_DC0_BYPASS1_CLK 85
/* MIPI-LVDS SS */
#define IMX_MIPI_IPG_CLK 90
#define IMX_MIPI0_PIXEL_CLK 100
#define IMX_MIPI0_BYPASS_CLK 101
#define IMX_MIPI0_LVDS_PIXEL_CLK 102
#define IMX_MIPI0_LVDS_BYPASS_CLK 103
#define IMX_MIPI0_LVDS_PHY_CLK 104
#define IMX_MIPI0_I2C0_CLK 105
#define IMX_MIPI0_I2C1_CLK 106
#define IMX_MIPI0_PWM0_CLK 107
#define IMX_MIPI1_PIXEL_CLK 108
#define IMX_MIPI1_BYPASS_CLK 109
#define IMX_MIPI1_LVDS_PIXEL_CLK 110
#define IMX_MIPI1_LVDS_BYPASS_CLK 111
#define IMX_MIPI1_LVDS_PHY_CLK 112
#define IMX_MIPI1_I2C0_CLK 113
#define IMX_MIPI1_I2C1_CLK 114
#define IMX_MIPI1_PWM0_CLK 115
/* IMG SS */
#define IMX_IMG_AXI_CLK 120
#define IMX_IMG_IPG_CLK 121
#define IMX_IMG_PXL_CLK 122
/* MIPI-CSI SS */
#define IMX_CSI0_CORE_CLK 130
#define IMX_CSI0_ESC_CLK 131
#define IMX_CSI0_PWM0_CLK 132
#define IMX_CSI0_I2C0_CLK 133
/* PARALLER CSI SS */
#define IMX_PARALLEL_CSI_DPLL_CLK 140
#define IMX_PARALLEL_CSI_PIXEL_CLK 141
#define IMX_PARALLEL_CSI_MCLK_CLK 142
/* VPU SS */
#define IMX_VPU_ENC_CLK 150
#define IMX_VPU_DEC_CLK 151
/* GPU SS */
#define IMX_GPU0_CORE_CLK 160
#define IMX_GPU0_SHADER_CLK 161
/* ADMA SS */
#define IMX_ADMA_IPG_CLK_ROOT 165
#define IMX_ADMA_UART0_CLK 170
#define IMX_ADMA_UART1_CLK 171
#define IMX_ADMA_UART2_CLK 172
#define IMX_ADMA_UART3_CLK 173
#define IMX_ADMA_SPI0_CLK 174
#define IMX_ADMA_SPI1_CLK 175
#define IMX_ADMA_SPI2_CLK 176
#define IMX_ADMA_SPI3_CLK 177
#define IMX_ADMA_CAN0_CLK 178
#define IMX_ADMA_CAN1_CLK 179
#define IMX_ADMA_CAN2_CLK 180
#define IMX_ADMA_I2C0_CLK 181
#define IMX_ADMA_I2C1_CLK 182
#define IMX_ADMA_I2C2_CLK 183
#define IMX_ADMA_I2C3_CLK 184
#define IMX_ADMA_FTM0_CLK 185
#define IMX_ADMA_FTM1_CLK 186
#define IMX_ADMA_ADC0_CLK 187
#define IMX_ADMA_PWM_CLK 188
#define IMX_ADMA_LCD_CLK 189
#define IMX_SCU_CLK_END 190
/* LPCG clocks */
/* LSIO SS LPCG */

19
include/dt-bindings/clock/imx8mq-clock.h
View File

@ -405,25 +405,6 @@
#define IMX8MQ_VIDEO2_PLL1_REF_SEL 266
#define IMX8MQ_SYS1_PLL_40M_CG 267
#define IMX8MQ_SYS1_PLL_80M_CG 268
#define IMX8MQ_SYS1_PLL_100M_CG 269
#define IMX8MQ_SYS1_PLL_133M_CG 270
#define IMX8MQ_SYS1_PLL_160M_CG 271
#define IMX8MQ_SYS1_PLL_200M_CG 272
#define IMX8MQ_SYS1_PLL_266M_CG 273
#define IMX8MQ_SYS1_PLL_400M_CG 274
#define IMX8MQ_SYS1_PLL_800M_CG 275
#define IMX8MQ_SYS2_PLL_50M_CG 276
#define IMX8MQ_SYS2_PLL_100M_CG 277
#define IMX8MQ_SYS2_PLL_125M_CG 278
#define IMX8MQ_SYS2_PLL_166M_CG 279
#define IMX8MQ_SYS2_PLL_200M_CG 280
#define IMX8MQ_SYS2_PLL_250M_CG 281
#define IMX8MQ_SYS2_PLL_333M_CG 282
#define IMX8MQ_SYS2_PLL_500M_CG 283
#define IMX8MQ_SYS2_PLL_1000M_CG 284
#define IMX8MQ_CLK_GPU_CORE 285
#define IMX8MQ_CLK_GPU_SHADER 286
#define IMX8MQ_CLK_M4_CORE 287

100
include/linux/clk/tegra.h
View File

@ -123,20 +123,6 @@ static inline void tegra_cpu_clock_resume(void)
}
#endif
extern int tegra210_plle_hw_sequence_start(void);
extern bool tegra210_plle_hw_sequence_is_enabled(void);
extern void tegra210_xusb_pll_hw_control_enable(void);
extern void tegra210_xusb_pll_hw_sequence_start(void);
extern void tegra210_sata_pll_hw_control_enable(void);
extern void tegra210_sata_pll_hw_sequence_start(void);
extern void tegra210_set_sata_pll_seq_sw(bool state);
extern void tegra210_put_utmipll_in_iddq(void);
extern void tegra210_put_utmipll_out_iddq(void);
extern int tegra210_clk_handle_mbist_war(unsigned int id);
extern void tegra210_clk_emc_dll_enable(bool flag);
extern void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value);
extern void tegra210_clk_emc_update_setting(u32 emc_src_value);
struct clk;
struct tegra_emc;
@ -144,17 +130,10 @@ typedef long (tegra20_clk_emc_round_cb)(unsigned long rate,
unsigned long min_rate,
unsigned long max_rate,
void *arg);
void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb,
void *cb_arg);
int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same);
typedef int (tegra124_emc_prepare_timing_change_cb)(struct tegra_emc *emc,
unsigned long rate);
typedef void (tegra124_emc_complete_timing_change_cb)(struct tegra_emc *emc,
unsigned long rate);
void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb,
tegra124_emc_complete_timing_change_cb *complete_cb);
struct tegra210_clk_emc_config {
unsigned long rate;
@ -176,8 +155,87 @@ struct tegra210_clk_emc_provider {
const struct tegra210_clk_emc_config *config);
};
#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb,
void *cb_arg);
int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same);
#else
static inline void
tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb,
void *cb_arg)
{
}
static inline int
tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same)
{
return 0;
}
#endif
#ifdef CONFIG_TEGRA124_CLK_EMC
void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb,
tegra124_emc_complete_timing_change_cb *complete_cb);
#else
static inline void
tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb,
tegra124_emc_complete_timing_change_cb *complete_cb)
{
}
#endif
#ifdef CONFIG_ARCH_TEGRA_210_SOC
int tegra210_plle_hw_sequence_start(void);
bool tegra210_plle_hw_sequence_is_enabled(void);
void tegra210_xusb_pll_hw_control_enable(void);
void tegra210_xusb_pll_hw_sequence_start(void);
void tegra210_sata_pll_hw_control_enable(void);
void tegra210_sata_pll_hw_sequence_start(void);
void tegra210_set_sata_pll_seq_sw(bool state);
void tegra210_put_utmipll_in_iddq(void);
void tegra210_put_utmipll_out_iddq(void);
int tegra210_clk_handle_mbist_war(unsigned int id);
void tegra210_clk_emc_dll_enable(bool flag);
void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value);
void tegra210_clk_emc_update_setting(u32 emc_src_value);
int tegra210_clk_emc_attach(struct clk *clk,
struct tegra210_clk_emc_provider *provider);
void tegra210_clk_emc_detach(struct clk *clk);
#else
static inline int tegra210_plle_hw_sequence_start(void)
{
return 0;
}
static inline bool tegra210_plle_hw_sequence_is_enabled(void)
{
return false;
}
static inline int tegra210_clk_handle_mbist_war(unsigned int id)
{
return 0;
}
static inline int
tegra210_clk_emc_attach(struct clk *clk,
struct tegra210_clk_emc_provider *provider)
{
return 0;
}
static inline void tegra210_xusb_pll_hw_control_enable(void) {}
static inline void tegra210_xusb_pll_hw_sequence_start(void) {}
static inline void tegra210_sata_pll_hw_control_enable(void) {}
static inline void tegra210_sata_pll_hw_sequence_start(void) {}
static inline void tegra210_set_sata_pll_seq_sw(bool state) {}
static inline void tegra210_put_utmipll_in_iddq(void) {}
static inline void tegra210_put_utmipll_out_iddq(void) {}
static inline void tegra210_clk_emc_dll_enable(bool flag) {}
static inline void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value) {}
static inline void tegra210_clk_emc_update_setting(u32 emc_src_value) {}
static inline void tegra210_clk_emc_detach(struct clk *clk) {}
#endif
#endif /* __LINUX_CLK_TEGRA_H_ */

5
include/linux/clkdev.h
View File

@ -30,11 +30,6 @@ struct clk_lookup {
.clk = c, \
}
struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id,
const char *dev_fmt, ...) __printf(3, 4);
struct clk_lookup *clkdev_hw_alloc(struct clk_hw *hw, const char *con_id,
const char *dev_fmt, ...) __printf(3, 4);
void clkdev_add(struct clk_lookup *cl);
void clkdev_drop(struct clk_lookup *cl);

2
sound/soc/dwc/Kconfig
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
config SND_DESIGNWARE_I2S
tristate "Synopsys I2S Device Driver"
depends on CLKDEV_LOOKUP
depends on HAVE_CLK
select SND_SOC_GENERIC_DMAENGINE_PCM
help
Say Y or M if you want to add support for I2S driver for

14
sound/soc/rockchip/Kconfig
View File

@ -9,7 +9,7 @@ config SND_SOC_ROCKCHIP
config SND_SOC_ROCKCHIP_I2S
tristate "Rockchip I2S Device Driver"
depends on CLKDEV_LOOKUP && SND_SOC_ROCKCHIP
depends on HAVE_CLK && SND_SOC_ROCKCHIP
select SND_SOC_GENERIC_DMAENGINE_PCM
help
Say Y or M if you want to add support for I2S driver for
@ -18,7 +18,7 @@ config SND_SOC_ROCKCHIP_I2S
config SND_SOC_ROCKCHIP_PDM
tristate "Rockchip PDM Controller Driver"
depends on CLKDEV_LOOKUP && SND_SOC_ROCKCHIP
depends on HAVE_CLK && SND_SOC_ROCKCHIP
select SND_SOC_GENERIC_DMAENGINE_PCM
select RATIONAL
help
@ -28,7 +28,7 @@ config SND_SOC_ROCKCHIP_PDM
config SND_SOC_ROCKCHIP_SPDIF
tristate "Rockchip SPDIF Device Driver"
depends on CLKDEV_LOOKUP && SND_SOC_ROCKCHIP
depends on HAVE_CLK && SND_SOC_ROCKCHIP
select SND_SOC_GENERIC_DMAENGINE_PCM
help
Say Y or M if you want to add support for SPDIF driver for
@ -36,7 +36,7 @@ config SND_SOC_ROCKCHIP_SPDIF
config SND_SOC_ROCKCHIP_MAX98090
tristate "ASoC support for Rockchip boards using a MAX98090 codec"
depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB && CLKDEV_LOOKUP
depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB && HAVE_CLK
select SND_SOC_ROCKCHIP_I2S
select SND_SOC_MAX98090
select SND_SOC_TS3A227E
@ -47,7 +47,7 @@ config SND_SOC_ROCKCHIP_MAX98090
config SND_SOC_ROCKCHIP_RT5645
tristate "ASoC support for Rockchip boards using a RT5645/RT5650 codec"
depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB && CLKDEV_LOOKUP
depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB && HAVE_CLK
select SND_SOC_ROCKCHIP_I2S
select SND_SOC_RT5645
help
@ -56,7 +56,7 @@ config SND_SOC_ROCKCHIP_RT5645
config SND_SOC_RK3288_HDMI_ANALOG
tristate "ASoC support multiple codecs for Rockchip RK3288 boards"
depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB && CLKDEV_LOOKUP
depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB && HAVE_CLK
select SND_SOC_ROCKCHIP_I2S
select SND_SOC_HDMI_CODEC
select SND_SOC_ES8328_I2C
@ -68,7 +68,7 @@ config SND_SOC_RK3288_HDMI_ANALOG
config SND_SOC_RK3399_GRU_SOUND
tristate "ASoC support multiple codecs for Rockchip RK3399 GRU boards"
depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB && CLKDEV_LOOKUP && SPI
depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB && HAVE_CLK && SPI
select SND_SOC_ROCKCHIP_I2S
select SND_SOC_MAX98357A
select SND_SOC_RT5514