arm64: tegra: Device tree changes for v6.2-rc1
This contains many new additions, primarily for Tegra234, as well as a slew of cleanups for issues flagged by the DT validation tools. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmN7rpkTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoTT4EACggtfdoSghLUBBVuu6iFdiRuDEmEV/ BLGy80NXes+PTH4UHOopFF3vawtyiaUsN584SkkhQfjvrETLvGSFQHEyXIV+zf/h GUiRKwli615kVZdTzNjY0Dc7tb3whOdSzb3fXlLstOR7UGhlx0qOy2E9mChtT/+n Fr57ioUO6cVy241mN1mtf1E0he6ndpMRKW5vHKn4TqjcksRMr8KFncEjHcnHLds1 0i9pQhHqHLg3P1m7gVK/IZd5F8O5zE6PfIhzJi/8PirxHcp/SuAojAPSZWUN+SaG wgT5V5tN63PKvNVf5cm39KaXWKHTiPhbxMySC084a3s+ISPuOMXhgsjKBdRzGqok BwFTnMO7q8JcLq3uGA20RqhBHJDAlBLDllDeuz2BMhdqINVS70A3BtgkgUxNyxal E2eacQ/NRjf/d9awFnyLZ+OR9kYjtKiSpc3ojVbxcUEJhs1LFZ0wyL+Pl3hZ/9uy wDxQQMug5hBs7aXV7L9WD/9NmuS9EEd549r3JDRmpdpFA57fDvquh7jiERzuF+O8 Ft6ivK9BhiHbxkPUbbHb+nyiQSG4V837z5mHExka1IBHruA5l7RCe4njLLIMuCBl amI8uOvFoVLz8/MmxKXUIwUuw5sAYmbLMPLqu6DL3vpw7G+3oh9NYFgVax/JMTCL 7jrLlSxiUDgIaw== =O3Ij -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmN9RvMACgkQmmx57+YA GNkv6g/+IiRZTFZ+GPs0vRHISTlcHFJxUOoOGbimABmAEdW/ohQFyRQnY9eeytEi 1bmKxzY9z0EwMrs4I8BTDSLI+Pm8ru1up0xUP6/FjU2PXBJa7Wh2jPL20sLnCVut gWFs9AOoYpDK0wKv+Dvdjb4llIStp88ZL872a8XbI5zKXVV1qT7ZrZWSyyg4OAE+ Nm56SK/mTyCLkQh0cbENvDUfXd5/06JJRifyCcz6bVqp3IDN3r4ICaSwc26D3fqZ EuCKkc81KxBeN+ey3abq1BZ0jYB0cOAZfV5oLQ2eRIQuYxKt81+TpliS3n8oGgHN gI8HL/f9nkNEoVK12v3WgtQNd8oB43QsTCTto+F3atUV4yT0wtX+HgRPbiKJAmyI I8YeuMkr5cA1npFWNDVQlSXLsh6MRguAFZdlPcMA8Jq1/1MRg8sDgOiD3xjhStrx MwUiw4/++pOWj6wJlogsrjvNv3eJoKFW2hP6hN45ZBiOkHnvSXsud5yvuj6meHmq 8HjGbHQ91Nmeu91gugMd5tdJcpvgkAGQBJqWycwWO90fQ1mUiNPtW8HxeyAsDYyI az439eDZf+Wn5GEIq4ZAR9b5LmL/LBceOawtNYuW9/+GA55C5ms+K/DkTmO4RfxE ySQi6e0TtWad3h/b4hSKwg0UhrwXvY4hr9FNzNhOi9qLLUe/KwU= =Ptk7 -----END PGP SIGNATURE----- Merge tag 'tegra-for-6.2-arm64-dt-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt arm64: tegra: Device tree changes for v6.2-rc1 This contains many new additions, primarily for Tegra234, as well as a slew of cleanups for issues flagged by the DT validation tools. * tag 'tegra-for-6.2-arm64-dt-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (30 commits) arm64: tegra: Remove unneeded clock-names for Tegra132 PWM arm64: tegra: Fix up compatible string for SDMMC1 on Tegra234 arm64: tegra: Remove unused reset-names for QSPI arm64: tegra: Fixup pinmux node names arm64: tegra: Remove reset-names for QSPI arm64: tegra: Use correct compatible string for Tegra234 HDA arm64: tegra: Use correct compatible string for Tegra194 HDA arm64: tegra: Use vbus-gpios property arm64: tegra: Restructure Tegra210 PMC pinmux nodes arm64: tegra: Update cache properties arm64: tegra: Remove 'enable-active-low' arm64: tegra: Add dma-channel-mask in GPCDMA node arm64: tegra: Fix non-prefetchable aperture of PCIe C3 controller arm64: tegra: Add missing compatible string to Ethernet USB device arm64: tegra: Separate AON pinmux from main pinmux on Tegra194 arm64: tegra: Add ECAM aperture info for all the PCIe controllers arm64: tegra: Remove clock-names from PWM nodes arm64: tegra: Enable GTE nodes arm64: tegra: Update console for Jetson Xavier and Orin arm64: tegra: Enable PWM users on Jetson AGX Orin ... Link: https://lore.kernel.org/r/20221121171239.2041835-7-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
0294678861
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@ -62,7 +62,7 @@
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_default>;
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pinmux_default: pinmux@0 {
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pinmux_default: pinmux {
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dap_mclk1_pw4 {
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nvidia,pins = "dap_mclk1_pw4";
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nvidia,function = "extperiph1";
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@ -393,7 +393,6 @@
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reg = <0x0 0x7000a000 0x0 0x100>;
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#pwm-cells = <2>;
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clocks = <&tegra_car TEGRA124_CLK_PWM>;
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clock-names = "pwm";
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resets = <&tegra_car 17>;
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reset-names = "pwm";
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status = "disabled";
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@ -78,7 +78,8 @@
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reg = <0x0 0x2600000 0x0 0x210000>;
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resets = <&bpmp TEGRA186_RESET_GPCDMA>;
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reset-names = "gpcdma";
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
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@ -112,6 +113,7 @@
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#dma-cells = <1>;
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iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
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dma-coherent;
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dma-channel-mask = <0xfffffffe>;
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status = "okay";
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};
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@ -790,7 +792,6 @@
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compatible = "nvidia,tegra186-pwm";
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reg = <0x0 0x3280000 0x0 0x10000>;
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clocks = <&bpmp TEGRA186_CLK_PWM1>;
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clock-names = "pwm";
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resets = <&bpmp TEGRA186_RESET_PWM1>;
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reset-names = "pwm";
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status = "disabled";
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@ -801,7 +802,6 @@
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compatible = "nvidia,tegra186-pwm";
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reg = <0x0 0x3290000 0x0 0x10000>;
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clocks = <&bpmp TEGRA186_CLK_PWM2>;
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clock-names = "pwm";
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resets = <&bpmp TEGRA186_RESET_PWM2>;
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reset-names = "pwm";
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status = "disabled";
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@ -812,7 +812,6 @@
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compatible = "nvidia,tegra186-pwm";
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reg = <0x0 0x32a0000 0x0 0x10000>;
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clocks = <&bpmp TEGRA186_CLK_PWM3>;
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clock-names = "pwm";
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resets = <&bpmp TEGRA186_RESET_PWM3>;
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reset-names = "pwm";
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status = "disabled";
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@ -823,7 +822,6 @@
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compatible = "nvidia,tegra186-pwm";
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reg = <0x0 0x32c0000 0x0 0x10000>;
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clocks = <&bpmp TEGRA186_CLK_PWM5>;
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clock-names = "pwm";
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resets = <&bpmp TEGRA186_RESET_PWM5>;
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reset-names = "pwm";
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status = "disabled";
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@ -834,7 +832,6 @@
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compatible = "nvidia,tegra186-pwm";
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reg = <0x0 0x32d0000 0x0 0x10000>;
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clocks = <&bpmp TEGRA186_CLK_PWM6>;
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clock-names = "pwm";
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resets = <&bpmp TEGRA186_RESET_PWM6>;
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reset-names = "pwm";
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status = "disabled";
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@ -845,7 +842,6 @@
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compatible = "nvidia,tegra186-pwm";
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reg = <0x0 0x32e0000 0x0 0x10000>;
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clocks = <&bpmp TEGRA186_CLK_PWM7>;
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clock-names = "pwm";
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resets = <&bpmp TEGRA186_RESET_PWM7>;
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reset-names = "pwm";
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status = "disabled";
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@ -856,7 +852,6 @@
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compatible = "nvidia,tegra186-pwm";
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reg = <0x0 0x32f0000 0x0 0x10000>;
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clocks = <&bpmp TEGRA186_CLK_PWM8>;
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clock-names = "pwm";
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resets = <&bpmp TEGRA186_RESET_PWM8>;
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reset-names = "pwm";
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status = "disabled";
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@ -1274,7 +1269,6 @@
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compatible = "nvidia,tegra186-pwm";
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reg = <0x0 0xc340000 0x0 0x10000>;
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clocks = <&bpmp TEGRA186_CLK_PWM4>;
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clock-names = "pwm";
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resets = <&bpmp TEGRA186_RESET_PWM4>;
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reset-names = "pwm";
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status = "disabled";
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@ -23,7 +23,7 @@
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};
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chosen {
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bootargs = "console=ttyS0,115200n8";
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bootargs = "console=ttyTCU0,115200n8";
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stdout-path = "serial0:115200n8";
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};
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@ -2117,8 +2117,8 @@
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"usb-b-connector";
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label = "micro-USB";
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type = "micro";
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vbus-gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 1)
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GPIO_ACTIVE_LOW>;
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vbus-gpios = <&gpio TEGRA194_MAIN_GPIO(Z, 1)
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GPIO_ACTIVE_LOW>;
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};
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};
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@ -20,7 +20,7 @@
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};
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chosen {
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bootargs = "console=ttyS0,115200n8";
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bootargs = "console=ttyTCU0,115200n8";
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stdout-path = "serial0:115200n8";
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};
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@ -86,6 +86,7 @@
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interrupt-controller;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pinmux 0 0 169>;
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};
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cbb-noc@2300000 {
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@ -142,7 +143,8 @@
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reg = <0x2600000 0x210000>;
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resets = <&bpmp TEGRA194_RESET_GPCDMA>;
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reset-names = "gpcdma";
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
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@ -176,6 +178,7 @@
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#dma-cells = <1>;
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iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
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dma-coherent;
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dma-channel-mask = <0xfffffffe>;
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status = "okay";
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};
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@ -626,12 +629,10 @@
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pinmux: pinmux@2430000 {
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compatible = "nvidia,tegra194-pinmux";
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reg = <0x2430000 0x17000>,
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<0xc300000 0x4000>;
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reg = <0x2430000 0x17000>;
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status = "okay";
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pex_rst_c5_out_state: pex_rst_c5_out {
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pex_rst_c5_out_state: pinmux-pex-rst-c5-out {
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pex_rst {
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nvidia,pins = "pex_l5_rst_n_pgg1";
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nvidia,schmitt = <TEGRA_PIN_DISABLE>;
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@ -642,7 +643,7 @@
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};
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};
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clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
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clkreq_c5_bi_dir_state: pinmux-clkreq-c5-bi-dir {
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clkreq {
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nvidia,pins = "pex_l5_clkreq_n_pgg0";
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nvidia,schmitt = <TEGRA_PIN_DISABLE>;
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@ -935,7 +936,6 @@
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<&bpmp TEGRA194_CLK_QSPI0_PM>;
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clock-names = "qspi", "qspi_out";
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resets = <&bpmp TEGRA194_RESET_QSPI0>;
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reset-names = "qspi";
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status = "disabled";
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};
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@ -949,7 +949,6 @@
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<&bpmp TEGRA194_CLK_QSPI1_PM>;
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clock-names = "qspi", "qspi_out";
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resets = <&bpmp TEGRA194_RESET_QSPI1>;
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reset-names = "qspi";
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status = "disabled";
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};
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@ -958,7 +957,6 @@
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"nvidia,tegra186-pwm";
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reg = <0x3280000 0x10000>;
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clocks = <&bpmp TEGRA194_CLK_PWM1>;
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clock-names = "pwm";
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resets = <&bpmp TEGRA194_RESET_PWM1>;
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reset-names = "pwm";
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status = "disabled";
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@ -970,7 +968,6 @@
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"nvidia,tegra186-pwm";
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reg = <0x3290000 0x10000>;
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clocks = <&bpmp TEGRA194_CLK_PWM2>;
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clock-names = "pwm";
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resets = <&bpmp TEGRA194_RESET_PWM2>;
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reset-names = "pwm";
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status = "disabled";
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@ -982,7 +979,6 @@
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"nvidia,tegra186-pwm";
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reg = <0x32a0000 0x10000>;
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clocks = <&bpmp TEGRA194_CLK_PWM3>;
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clock-names = "pwm";
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resets = <&bpmp TEGRA194_RESET_PWM3>;
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reset-names = "pwm";
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status = "disabled";
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@ -994,7 +990,6 @@
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"nvidia,tegra186-pwm";
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reg = <0x32c0000 0x10000>;
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clocks = <&bpmp TEGRA194_CLK_PWM5>;
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clock-names = "pwm";
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resets = <&bpmp TEGRA194_RESET_PWM5>;
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reset-names = "pwm";
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status = "disabled";
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@ -1006,7 +1001,6 @@
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"nvidia,tegra186-pwm";
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reg = <0x32d0000 0x10000>;
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clocks = <&bpmp TEGRA194_CLK_PWM6>;
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clock-names = "pwm";
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resets = <&bpmp TEGRA194_RESET_PWM6>;
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reset-names = "pwm";
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status = "disabled";
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@ -1018,7 +1012,6 @@
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"nvidia,tegra186-pwm";
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reg = <0x32e0000 0x10000>;
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clocks = <&bpmp TEGRA194_CLK_PWM7>;
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clock-names = "pwm";
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resets = <&bpmp TEGRA194_RESET_PWM7>;
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reset-names = "pwm";
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status = "disabled";
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@ -1030,7 +1023,6 @@
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"nvidia,tegra186-pwm";
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reg = <0x32f0000 0x10000>;
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clocks = <&bpmp TEGRA194_CLK_PWM8>;
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clock-names = "pwm";
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resets = <&bpmp TEGRA194_RESET_PWM8>;
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reset-names = "pwm";
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status = "disabled";
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@ -1154,7 +1146,7 @@
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};
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hda@3510000 {
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compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
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compatible = "nvidia,tegra194-hda";
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reg = <0x3510000 0x10000>;
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interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_HDA>,
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@ -1366,6 +1358,16 @@
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status = "disabled";
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};
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hte_lic: hardware-timestamp@3aa0000 {
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compatible = "nvidia,tegra194-gte-lic";
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reg = <0x3aa0000 0x10000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,int-threshold = <1>;
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nvidia,slices = <11>;
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#timestamp-cells = <1>;
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status = "okay";
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};
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hsp_top0: hsp@3c00000 {
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compatible = "nvidia,tegra194-hsp";
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reg = <0x03c00000 0xa0000>;
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@ -1579,6 +1581,16 @@
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#mbox-cells = <2>;
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};
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hte_aon: hardware-timestamp@c1e0000 {
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compatible = "nvidia,tegra194-gte-aon";
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reg = <0xc1e0000 0x10000>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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nvidia,int-threshold = <1>;
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nvidia,slices = <3>;
|
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#timestamp-cells = <1>;
|
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status = "okay";
|
||||
};
|
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|
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gen2_i2c: i2c@c240000 {
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||||
compatible = "nvidia,tegra194-i2c";
|
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reg = <0x0c240000 0x10000>;
|
||||
|
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@ -1660,6 +1672,14 @@
|
|||
#gpio-cells = <2>;
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||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
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||||
gpio-range = <&pinmux_aon 0 0 30>;
|
||||
};
|
||||
|
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pinmux_aon: pinmux@c300000 {
|
||||
compatible = "nvidia,tegra194-pinmux-aon";
|
||||
reg = <0xc300000 0x4000>;
|
||||
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||||
status = "okay";
|
||||
};
|
||||
|
||||
pwm4: pwm@c340000 {
|
||||
|
|
@ -1667,7 +1687,6 @@
|
|||
"nvidia,tegra186-pwm";
|
||||
reg = <0xc340000 0x10000>;
|
||||
clocks = <&bpmp TEGRA194_CLK_PWM4>;
|
||||
clock-names = "pwm";
|
||||
resets = <&bpmp TEGRA194_RESET_PWM4>;
|
||||
reset-names = "pwm";
|
||||
status = "disabled";
|
||||
|
|
@ -1895,7 +1914,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
ranges = <0x15000000 0x15000000 0x01000000>;
|
||||
ranges = <0x14800000 0x14800000 0x02800000>;
|
||||
interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;
|
||||
interconnect-names = "dma-mem";
|
||||
iommus = <&smmu TEGRA194_SID_HOST1X>;
|
||||
|
|
@ -3029,36 +3048,51 @@
|
|||
};
|
||||
|
||||
l2c_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-size = <2097152>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <2048>;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&l3c>;
|
||||
};
|
||||
|
||||
l2c_1: l2-cache1 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-size = <2097152>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <2048>;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&l3c>;
|
||||
};
|
||||
|
||||
l2c_2: l2-cache2 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-size = <2097152>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <2048>;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&l3c>;
|
||||
};
|
||||
|
||||
l2c_3: l2-cache3 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-size = <2097152>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <2048>;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&l3c>;
|
||||
};
|
||||
|
||||
l3c: l3-cache {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-size = <4194304>;
|
||||
cache-line-size = <64>;
|
||||
cache-level = <3>;
|
||||
cache-sets = <4096>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1293,14 +1293,14 @@
|
|||
};
|
||||
};
|
||||
|
||||
dvfs_pwm_active_state: dvfs_pwm_active {
|
||||
dvfs_pwm_active_state: pinmux-dvfs-pwm-active {
|
||||
dvfs_pwm_pbb1 {
|
||||
nvidia,pins = "dvfs_pwm_pbb1";
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
};
|
||||
|
||||
dvfs_pwm_inactive_state: dvfs_pwm_inactive {
|
||||
dvfs_pwm_inactive_state: pinmux-dvfs-pwm-inactive {
|
||||
dvfs_pwm_pbb1 {
|
||||
nvidia,pins = "dvfs_pwm_pbb1";
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
|
|
@ -1368,6 +1368,7 @@
|
|||
#size-cells = <0>;
|
||||
|
||||
ethernet@1 {
|
||||
compatible = "usb955,9ff";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -109,14 +109,14 @@
|
|||
};
|
||||
|
||||
pinmux@700008d4 {
|
||||
dvfs_pwm_active_state: dvfs_pwm_active {
|
||||
dvfs_pwm_active_state: pinmux-dvfs-pwm-active {
|
||||
dvfs_pwm_pbb1 {
|
||||
nvidia,pins = "dvfs_pwm_pbb1";
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
};
|
||||
|
||||
dvfs_pwm_inactive_state: dvfs_pwm_inactive {
|
||||
dvfs_pwm_inactive_state: pinmux-dvfs-pwm-inactive {
|
||||
dvfs_pwm_pbb1 {
|
||||
nvidia,pins = "dvfs_pwm_pbb1";
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
|
|
|
|||
|
|
@ -554,42 +554,48 @@
|
|||
compatible = "nvidia,tegra210-pinmux";
|
||||
reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
|
||||
<0x0 0x70003000 0x0 0x294>; /* Mux registers */
|
||||
sdmmc1_3v3_drv: sdmmc1-3v3-drv {
|
||||
|
||||
sdmmc1_3v3_drv: pinmux-sdmmc1-3v3-drv {
|
||||
sdmmc1 {
|
||||
nvidia,pins = "drive_sdmmc1";
|
||||
nvidia,pull-down-strength = <0x8>;
|
||||
nvidia,pull-up-strength = <0x8>;
|
||||
};
|
||||
};
|
||||
sdmmc1_1v8_drv: sdmmc1-1v8-drv {
|
||||
|
||||
sdmmc1_1v8_drv: pinmux-sdmmc1-1v8-drv {
|
||||
sdmmc1 {
|
||||
nvidia,pins = "drive_sdmmc1";
|
||||
nvidia,pull-down-strength = <0x4>;
|
||||
nvidia,pull-up-strength = <0x3>;
|
||||
};
|
||||
};
|
||||
sdmmc2_1v8_drv: sdmmc2-1v8-drv {
|
||||
|
||||
sdmmc2_1v8_drv: pinmux-sdmmc2-1v8-drv {
|
||||
sdmmc2 {
|
||||
nvidia,pins = "drive_sdmmc2";
|
||||
nvidia,pull-down-strength = <0x10>;
|
||||
nvidia,pull-up-strength = <0x10>;
|
||||
};
|
||||
};
|
||||
sdmmc3_3v3_drv: sdmmc3-3v3-drv {
|
||||
|
||||
sdmmc3_3v3_drv: pinmux-sdmmc3-3v3-drv {
|
||||
sdmmc3 {
|
||||
nvidia,pins = "drive_sdmmc3";
|
||||
nvidia,pull-down-strength = <0x8>;
|
||||
nvidia,pull-up-strength = <0x8>;
|
||||
};
|
||||
};
|
||||
sdmmc3_1v8_drv: sdmmc3-1v8-drv {
|
||||
|
||||
sdmmc3_1v8_drv: pinmux-sdmmc3-1v8-drv {
|
||||
sdmmc3 {
|
||||
nvidia,pins = "drive_sdmmc3";
|
||||
nvidia,pull-down-strength = <0x4>;
|
||||
nvidia,pull-up-strength = <0x3>;
|
||||
};
|
||||
};
|
||||
sdmmc4_1v8_drv: sdmmc4-1v8-drv {
|
||||
|
||||
sdmmc4_1v8_drv: pinmux-sdmmc4-1v8-drv {
|
||||
sdmmc4 {
|
||||
nvidia,pins = "drive_sdmmc4";
|
||||
nvidia,pull-down-strength = <0x10>;
|
||||
|
|
@ -667,7 +673,6 @@
|
|||
reg = <0x0 0x7000a000 0x0 0x100>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_PWM>;
|
||||
clock-names = "pwm";
|
||||
resets = <&tegra_car 17>;
|
||||
reset-names = "pwm";
|
||||
status = "disabled";
|
||||
|
|
@ -912,35 +917,33 @@
|
|||
};
|
||||
};
|
||||
|
||||
sdmmc1_3v3: sdmmc1-3v3 {
|
||||
pins = "sdmmc1";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
|
||||
};
|
||||
pinmux {
|
||||
sdmmc1_3v3: sdmmc1-3v3 {
|
||||
pins = "sdmmc1";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
|
||||
};
|
||||
|
||||
sdmmc1_1v8: sdmmc1-1v8 {
|
||||
pins = "sdmmc1";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
|
||||
};
|
||||
sdmmc1_1v8: sdmmc1-1v8 {
|
||||
pins = "sdmmc1";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
|
||||
};
|
||||
|
||||
sdmmc3_3v3: sdmmc3-3v3 {
|
||||
pins = "sdmmc3";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
|
||||
};
|
||||
sdmmc3_3v3: sdmmc3-3v3 {
|
||||
pins = "sdmmc3";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
|
||||
};
|
||||
|
||||
sdmmc3_1v8: sdmmc3-1v8 {
|
||||
pins = "sdmmc3";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
|
||||
};
|
||||
sdmmc3_1v8: sdmmc3-1v8 {
|
||||
pins = "sdmmc3";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
|
||||
};
|
||||
|
||||
pex_dpd_disable: pex_en {
|
||||
pex-dpd-disable {
|
||||
pex_dpd_disable: pex-dpd-disable {
|
||||
pins = "pex-bias", "pex-clk1", "pex-clk2";
|
||||
low-power-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pex_dpd_enable: pex_dis {
|
||||
pex-dpd-enable {
|
||||
pex_dpd_enable: pex-dpd-enable {
|
||||
pins = "pex-bias", "pex-clk1", "pex-clk2";
|
||||
low-power-enable;
|
||||
};
|
||||
|
|
@ -1865,7 +1868,6 @@
|
|||
<&tegra_car TEGRA210_CLK_QSPI_PM>;
|
||||
clock-names = "qspi", "qspi_out";
|
||||
resets = <&tegra_car 211>;
|
||||
reset-names = "qspi";
|
||||
dmas = <&apbdma 5>, <&apbdma 5>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
|
|
@ -2005,6 +2007,7 @@
|
|||
|
||||
L2: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -39,7 +39,6 @@
|
|||
regulator-max-microvolt = <12000000>;
|
||||
gpio = <&gpio TEGRA234_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>;
|
||||
regulator-boot-on;
|
||||
enable-active-low;
|
||||
};
|
||||
|
||||
bus@0 {
|
||||
|
|
@ -55,6 +54,13 @@
|
|||
};
|
||||
};
|
||||
|
||||
mmc@3400000 {
|
||||
status = "okay";
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio TEGRA234_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
mmc@3460000 {
|
||||
status = "okay";
|
||||
bus-width = <8>;
|
||||
|
|
|
|||
|
|
@ -2007,6 +2007,17 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
serial@31d0000 {
|
||||
current-speed = <115200>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pwm@32a0000 {
|
||||
assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>;
|
||||
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
hda@3510000 {
|
||||
nvidia,model = "NVIDIA Jetson AGX Orin HDA";
|
||||
status = "okay";
|
||||
|
|
@ -2014,7 +2025,7 @@
|
|||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200n8";
|
||||
bootargs = "console=ttyTCU0,115200n8";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
|
|
@ -2184,4 +2195,12 @@
|
|||
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
|
||||
"p2u-5", "p2u-6", "p2u-7";
|
||||
};
|
||||
|
||||
pwm-fan {
|
||||
compatible = "pwm-fan";
|
||||
pwms = <&pwm3 0 45334>;
|
||||
|
||||
cooling-levels = <0 95 178 255>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,4 +2,18 @@
|
|||
|
||||
/ {
|
||||
compatible = "nvidia,p3737-0000";
|
||||
|
||||
bus@0 {
|
||||
pwm@3280000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pwm@32c0000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pwm@32f0000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
#include <dt-bindings/memory/tegra234-mc.h>
|
||||
#include <dt-bindings/power/tegra234-powergate.h>
|
||||
#include <dt-bindings/reset/tegra234-reset.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
|
||||
|
||||
/ {
|
||||
compatible = "nvidia,tegra234";
|
||||
|
|
@ -27,7 +28,8 @@
|
|||
reg = <0x2600000 0x210000>;
|
||||
resets = <&bpmp TEGRA234_RESET_GPCDMA>;
|
||||
reset-names = "gpcdma";
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
|
@ -60,6 +62,7 @@
|
|||
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
|
||||
dma-channel-mask = <0xfffffffe>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
|
|
@ -564,7 +567,7 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
ranges = <0x15000000 0x15000000 0x01000000>;
|
||||
ranges = <0x14800000 0x14800000 0x02000000>;
|
||||
interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>;
|
||||
interconnect-names = "dma-mem";
|
||||
iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>;
|
||||
|
|
@ -603,6 +606,42 @@
|
|||
iommus = <&smmu_niso1 TEGRA234_SID_VIC>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
nvdec@15480000 {
|
||||
compatible = "nvidia,tegra234-nvdec";
|
||||
reg = <0x15480000 0x00040000>;
|
||||
clocks = <&bpmp TEGRA234_CLK_NVDEC>,
|
||||
<&bpmp TEGRA234_CLK_FUSE>,
|
||||
<&bpmp TEGRA234_CLK_TSEC_PKA>;
|
||||
clock-names = "nvdec", "fuse", "tsec_pka";
|
||||
resets = <&bpmp TEGRA234_RESET_NVDEC>;
|
||||
reset-names = "nvdec";
|
||||
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
|
||||
interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
|
||||
<&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
|
||||
interconnect-names = "dma-mem", "write";
|
||||
iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;
|
||||
dma-coherent;
|
||||
|
||||
nvidia,memory-controller = <&mc>;
|
||||
|
||||
/*
|
||||
* Placeholder values that firmware needs to update with the real
|
||||
* offsets parsed from the microcode headers.
|
||||
*/
|
||||
nvidia,bl-manifest-offset = <0>;
|
||||
nvidia,bl-data-offset = <0>;
|
||||
nvidia,bl-code-offset = <0>;
|
||||
nvidia,os-manifest-offset = <0>;
|
||||
nvidia,os-data-offset = <0>;
|
||||
nvidia,os-code-offset = <0>;
|
||||
|
||||
/*
|
||||
* Firmware needs to set this to "okay" once the above values have
|
||||
* been updated.
|
||||
*/
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gpio: gpio@2200000 {
|
||||
|
|
@ -836,6 +875,13 @@
|
|||
dma-names = "rx", "tx";
|
||||
};
|
||||
|
||||
uarti: serial@31d0000 {
|
||||
compatible = "arm,sbsa-uart";
|
||||
reg = <0x31d0000 0x10000>;
|
||||
interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dp_aux_ch3_i2c: i2c@31e0000 {
|
||||
compatible = "nvidia,tegra194-i2c";
|
||||
reg = <0x31e0000 0x100>;
|
||||
|
|
@ -865,22 +911,79 @@
|
|||
<&bpmp TEGRA234_CLK_QSPI0_PM>;
|
||||
clock-names = "qspi", "qspi_out";
|
||||
resets = <&bpmp TEGRA234_RESET_QSPI0>;
|
||||
reset-names = "qspi";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm1: pwm@3280000 {
|
||||
compatible = "nvidia,tegra194-pwm",
|
||||
"nvidia,tegra186-pwm";
|
||||
compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
|
||||
reg = <0x3280000 0x10000>;
|
||||
clocks = <&bpmp TEGRA234_CLK_PWM1>;
|
||||
clock-names = "pwm";
|
||||
resets = <&bpmp TEGRA234_RESET_PWM1>;
|
||||
reset-names = "pwm";
|
||||
status = "disabled";
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
|
||||
pwm2: pwm@3290000 {
|
||||
compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
|
||||
reg = <0x3290000 0x10000>;
|
||||
clocks = <&bpmp TEGRA234_CLK_PWM2>;
|
||||
resets = <&bpmp TEGRA234_RESET_PWM2>;
|
||||
reset-names = "pwm";
|
||||
status = "disabled";
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
|
||||
pwm3: pwm@32a0000 {
|
||||
compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
|
||||
reg = <0x32a0000 0x10000>;
|
||||
clocks = <&bpmp TEGRA234_CLK_PWM3>;
|
||||
resets = <&bpmp TEGRA234_RESET_PWM3>;
|
||||
reset-names = "pwm";
|
||||
status = "disabled";
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
|
||||
pwm5: pwm@32c0000 {
|
||||
compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
|
||||
reg = <0x32c0000 0x10000>;
|
||||
clocks = <&bpmp TEGRA234_CLK_PWM5>;
|
||||
resets = <&bpmp TEGRA234_RESET_PWM5>;
|
||||
reset-names = "pwm";
|
||||
status = "disabled";
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
|
||||
pwm6: pwm@32d0000 {
|
||||
compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
|
||||
reg = <0x32d0000 0x10000>;
|
||||
clocks = <&bpmp TEGRA234_CLK_PWM6>;
|
||||
resets = <&bpmp TEGRA234_RESET_PWM6>;
|
||||
reset-names = "pwm";
|
||||
status = "disabled";
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
|
||||
pwm7: pwm@32e0000 {
|
||||
compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
|
||||
reg = <0x32e0000 0x10000>;
|
||||
clocks = <&bpmp TEGRA234_CLK_PWM7>;
|
||||
resets = <&bpmp TEGRA234_RESET_PWM7>;
|
||||
reset-names = "pwm";
|
||||
status = "disabled";
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
|
||||
pwm8: pwm@32f0000 {
|
||||
compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
|
||||
reg = <0x32f0000 0x10000>;
|
||||
clocks = <&bpmp TEGRA234_CLK_PWM8>;
|
||||
resets = <&bpmp TEGRA234_RESET_PWM8>;
|
||||
reset-names = "pwm";
|
||||
status = "disabled";
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
|
||||
spi@3300000 {
|
||||
compatible = "nvidia,tegra234-qspi";
|
||||
reg = <0x3300000 0x1000>;
|
||||
|
|
@ -891,7 +994,41 @@
|
|||
<&bpmp TEGRA234_CLK_QSPI1_PM>;
|
||||
clock-names = "qspi", "qspi_out";
|
||||
resets = <&bpmp TEGRA234_RESET_QSPI1>;
|
||||
reset-names = "qspi";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc@3400000 {
|
||||
compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
|
||||
reg = <0x03400000 0x20000>;
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
|
||||
<&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
|
||||
clock-names = "sdhci", "tmclk";
|
||||
assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
|
||||
<&bpmp TEGRA234_CLK_PLLC4_MUXED>;
|
||||
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>,
|
||||
<&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>;
|
||||
resets = <&bpmp TEGRA234_RESET_SDMMC1>;
|
||||
reset-names = "sdhci";
|
||||
interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>,
|
||||
<&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>;
|
||||
interconnect-names = "dma-mem", "write";
|
||||
iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>;
|
||||
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
|
||||
pinctrl-0 = <&sdmmc1_3v3>;
|
||||
pinctrl-1 = <&sdmmc1_1v8>;
|
||||
nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
|
||||
nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>;
|
||||
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
|
||||
nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
|
||||
nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
|
||||
nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
|
||||
nvidia,default-tap = <14>;
|
||||
nvidia,default-trim = <0x8>;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-ddr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -925,7 +1062,7 @@
|
|||
};
|
||||
|
||||
hda@3510000 {
|
||||
compatible = "nvidia,tegra234-hda", "nvidia,tegra30-hda";
|
||||
compatible = "nvidia,tegra234-hda";
|
||||
reg = <0x3510000 0x10000>;
|
||||
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA234_CLK_AZA_BIT>,
|
||||
|
|
@ -967,6 +1104,198 @@
|
|||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
p2u_hsio_0: phy@3e00000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03e00000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_1: phy@3e10000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03e10000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_2: phy@3e20000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03e20000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_3: phy@3e30000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03e30000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_4: phy@3e40000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03e40000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_5: phy@3e50000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03e50000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_6: phy@3e60000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03e60000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_7: phy@3e70000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03e70000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_nvhs_0: phy@3e90000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03e90000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_nvhs_1: phy@3ea0000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03ea0000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_nvhs_2: phy@3eb0000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03eb0000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_nvhs_3: phy@3ec0000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03ec0000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_nvhs_4: phy@3ed0000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03ed0000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_nvhs_5: phy@3ee0000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03ee0000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_nvhs_6: phy@3ef0000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03ef0000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_nvhs_7: phy@3f00000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03f00000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_gbe_0: phy@3f20000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03f20000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_gbe_1: phy@3f30000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03f30000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_gbe_2: phy@3f40000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03f40000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_gbe_3: phy@3f50000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03f50000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_gbe_4: phy@3f60000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03f60000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_gbe_5: phy@3f70000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03f70000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_gbe_6: phy@3f80000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03f80000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_gbe_7: phy@3f90000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03f90000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
ethernet@6800000 {
|
||||
compatible = "nvidia,tegra234-mgbe";
|
||||
reg = <0x06800000 0x10000>,
|
||||
|
|
@ -1259,198 +1588,6 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
p2u_hsio_0: phy@3e00000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03e00000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_1: phy@3e10000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03e10000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_2: phy@3e20000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03e20000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_3: phy@3e30000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03e30000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_4: phy@3e40000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03e40000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_5: phy@3e50000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03e50000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_6: phy@3e60000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03e60000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_hsio_7: phy@3e70000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03e70000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_nvhs_0: phy@3e90000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03e90000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_nvhs_1: phy@3ea0000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03ea0000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_nvhs_2: phy@3eb0000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03eb0000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_nvhs_3: phy@3ec0000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03ec0000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_nvhs_4: phy@3ed0000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03ed0000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_nvhs_5: phy@3ee0000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03ee0000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_nvhs_6: phy@3ef0000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03ef0000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_nvhs_7: phy@3f00000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03f00000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_gbe_0: phy@3f20000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03f20000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_gbe_1: phy@3f30000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03f30000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_gbe_2: phy@3f40000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03f40000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_gbe_3: phy@3f50000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03f50000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_gbe_4: phy@3f60000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03f60000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_gbe_5: phy@3f70000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03f70000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_gbe_6: phy@3f80000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03f80000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
p2u_gbe_7: phy@3f90000 {
|
||||
compatible = "nvidia,tegra234-p2u";
|
||||
reg = <0x03f90000 0x10000>;
|
||||
reg-names = "ctl";
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
hsp_aon: hsp@c150000 {
|
||||
compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
|
||||
reg = <0x0c150000 0x90000>;
|
||||
|
|
@ -1488,7 +1625,6 @@
|
|||
gen8_i2c: i2c@c250000 {
|
||||
compatible = "nvidia,tegra194-i2c";
|
||||
reg = <0xc250000 0x100>;
|
||||
nvidia,hw-instance-id = <0x7>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
clock-frequency = <400000>;
|
||||
|
|
@ -1530,6 +1666,16 @@
|
|||
gpio-controller;
|
||||
};
|
||||
|
||||
pwm4: pwm@c340000 {
|
||||
compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
|
||||
reg = <0xc340000 0x10000>;
|
||||
clocks = <&bpmp TEGRA234_CLK_PWM4>;
|
||||
resets = <&bpmp TEGRA234_RESET_PWM4>;
|
||||
reset-names = "pwm";
|
||||
status = "disabled";
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
|
||||
pmc: pmc@c360000 {
|
||||
compatible = "nvidia,tegra234-pmc";
|
||||
reg = <0x0c360000 0x10000>,
|
||||
|
|
@ -1541,6 +1687,26 @@
|
|||
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
|
||||
sdmmc1_3v3: sdmmc1-3v3 {
|
||||
pins = "sdmmc1-hv";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
|
||||
};
|
||||
|
||||
sdmmc1_1v8: sdmmc1-1v8 {
|
||||
pins = "sdmmc1-hv";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
|
||||
};
|
||||
|
||||
sdmmc3_3v3: sdmmc3-3v3 {
|
||||
pins = "sdmmc3-hv";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
|
||||
};
|
||||
|
||||
sdmmc3_1v8: sdmmc3-1v8 {
|
||||
pins = "sdmmc3-hv";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
|
||||
};
|
||||
};
|
||||
|
||||
aon-fabric@c600000 {
|
||||
|
|
@ -1576,7 +1742,7 @@
|
|||
interrupt-controller;
|
||||
};
|
||||
|
||||
smmu_iso: iommu@10000000{
|
||||
smmu_iso: iommu@10000000 {
|
||||
compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
|
||||
reg = <0x10000000 0x1000000>;
|
||||
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
|
@ -1879,8 +2045,9 @@
|
|||
reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */
|
||||
<0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */
|
||||
<0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
||||
<0x00 0x2a080000 0x0 0x00040000>; /* DBI reg space (256K) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi";
|
||||
<0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */
|
||||
<0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -1932,8 +2099,9 @@
|
|||
reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */
|
||||
<0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */
|
||||
<0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
||||
<0x00 0x2c080000 0x0 0x00040000>; /* DBI reg space (256K) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi";
|
||||
<0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */
|
||||
<0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -1965,7 +2133,7 @@
|
|||
|
||||
bus-range = <0x0 0xff>;
|
||||
|
||||
ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
|
||||
ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */
|
||||
<0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
|
||||
<0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
|
||||
|
||||
|
|
@ -1985,8 +2153,9 @@
|
|||
reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
|
||||
<0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */
|
||||
<0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
||||
<0x00 0x2e080000 0x0 0x00040000>; /* DBI reg space (256K) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi";
|
||||
<0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */
|
||||
<0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -2038,8 +2207,9 @@
|
|||
reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
|
||||
<0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
|
||||
<0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
||||
<0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi";
|
||||
<0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */
|
||||
<0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -2091,8 +2261,9 @@
|
|||
reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
|
||||
<0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
|
||||
<0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
||||
<0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi";
|
||||
<0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */
|
||||
<0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -2144,8 +2315,9 @@
|
|||
reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
|
||||
<0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
|
||||
<0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
||||
<0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi";
|
||||
<0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */
|
||||
<0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -2178,7 +2350,7 @@
|
|||
bus-range = <0x0 0xff>;
|
||||
|
||||
ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
|
||||
<0x02000000 0x0 0x40000000 0x21 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
|
||||
<0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
|
||||
<0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
|
||||
|
||||
interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>,
|
||||
|
|
@ -2197,8 +2369,9 @@
|
|||
reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
|
||||
<0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
|
||||
<0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
||||
<0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi";
|
||||
<0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
|
||||
<0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -2250,8 +2423,9 @@
|
|||
reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
|
||||
<0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
|
||||
<0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
||||
<0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi";
|
||||
<0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */
|
||||
<0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -2303,8 +2477,9 @@
|
|||
reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
|
||||
<0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
|
||||
<0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
||||
<0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi";
|
||||
<0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
|
||||
<0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -2336,7 +2511,7 @@
|
|||
|
||||
bus-range = <0x0 0xff>;
|
||||
|
||||
ranges = <0x43000000 0x27 0x40000000 0x27 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */
|
||||
ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */
|
||||
<0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
|
||||
<0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
|
||||
|
||||
|
|
@ -2356,8 +2531,9 @@
|
|||
reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
|
||||
<0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */
|
||||
<0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
||||
<0x00 0x3c080000 0x0 0x00040000>; /* DBI reg space (256K) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi";
|
||||
<0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */
|
||||
<0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -2409,8 +2585,9 @@
|
|||
reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
|
||||
<0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */
|
||||
<0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
||||
<0x00 0x3e080000 0x0 0x00040000>; /* DBI reg space (256K) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi";
|
||||
<0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */
|
||||
<0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -2442,7 +2619,7 @@
|
|||
|
||||
bus-range = <0x0 0xff>;
|
||||
|
||||
ranges = <0x43000000 0x2e 0x40000000 0x2e 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */
|
||||
ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */
|
||||
<0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
|
||||
<0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
|
||||
|
||||
|
|
@ -2905,117 +3082,150 @@
|
|||
};
|
||||
|
||||
l2c0_0: l2-cache00 {
|
||||
compatible = "cache";
|
||||
cache-size = <262144>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&l3c0>;
|
||||
};
|
||||
|
||||
l2c0_1: l2-cache01 {
|
||||
compatible = "cache";
|
||||
cache-size = <262144>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&l3c0>;
|
||||
};
|
||||
|
||||
l2c0_2: l2-cache02 {
|
||||
compatible = "cache";
|
||||
cache-size = <262144>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&l3c0>;
|
||||
};
|
||||
|
||||
l2c0_3: l2-cache03 {
|
||||
compatible = "cache";
|
||||
cache-size = <262144>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&l3c0>;
|
||||
};
|
||||
|
||||
l2c1_0: l2-cache10 {
|
||||
compatible = "cache";
|
||||
cache-size = <262144>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&l3c1>;
|
||||
};
|
||||
|
||||
l2c1_1: l2-cache11 {
|
||||
compatible = "cache";
|
||||
cache-size = <262144>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&l3c1>;
|
||||
};
|
||||
|
||||
l2c1_2: l2-cache12 {
|
||||
compatible = "cache";
|
||||
cache-size = <262144>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&l3c1>;
|
||||
};
|
||||
|
||||
l2c1_3: l2-cache13 {
|
||||
compatible = "cache";
|
||||
cache-size = <262144>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&l3c1>;
|
||||
};
|
||||
|
||||
l2c2_0: l2-cache20 {
|
||||
compatible = "cache";
|
||||
cache-size = <262144>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&l3c2>;
|
||||
};
|
||||
|
||||
l2c2_1: l2-cache21 {
|
||||
compatible = "cache";
|
||||
cache-size = <262144>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&l3c2>;
|
||||
};
|
||||
|
||||
l2c2_2: l2-cache22 {
|
||||
compatible = "cache";
|
||||
cache-size = <262144>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&l3c2>;
|
||||
};
|
||||
|
||||
l2c2_3: l2-cache23 {
|
||||
compatible = "cache";
|
||||
cache-size = <262144>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <512>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
next-level-cache = <&l3c2>;
|
||||
};
|
||||
|
||||
l3c0: l3-cache0 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-size = <2097152>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <2048>;
|
||||
cache-level = <3>;
|
||||
};
|
||||
|
||||
l3c1: l3-cache1 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-size = <2097152>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <2048>;
|
||||
cache-level = <3>;
|
||||
};
|
||||
|
||||
l3c2: l3-cache2 {
|
||||
compatible = "cache";
|
||||
cache-unified;
|
||||
cache-size = <2097152>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <2048>;
|
||||
cache-level = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue