[PATCH] x86: implement always-locked bit ops, for memory shared with an SMP hypervisor
Add "always lock'd" implementations of set_bit, clear_bit and change_bit and the corresponding test_and_ functions. Also add "always lock'd" implementation of cmpxchg. These give guaranteed strong synchronisation and are required for non-SMP kernels running on an SMP hypervisor. Signed-off-by: Ian Pratt <ian.pratt@xensource.com> Signed-off-by: Christian Limpach <Christian.Limpach@cl.cam.ac.uk> Signed-off-by: Chris Wright <chrisw@sous-sol.org> Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com> Cc: Christoph Lameter <clameter@sgi.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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Chris Wright
Linus Torvalds
parent
05f4a3ec94
commit
027a8c7e60
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#ifndef _I386_SYNC_BITOPS_H
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#define _I386_SYNC_BITOPS_H
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/*
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* Copyright 1992, Linus Torvalds.
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*/
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/*
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* These have to be done with inline assembly: that way the bit-setting
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* is guaranteed to be atomic. All bit operations return 0 if the bit
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* was cleared before the operation and != 0 if it was not.
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*
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* bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
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*/
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#define ADDR (*(volatile long *) addr)
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/**
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* sync_set_bit - Atomically set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* This function is atomic and may not be reordered. See __set_bit()
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* if you do not require the atomic guarantees.
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*
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* Note: there are no guarantees that this function will not be reordered
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* on non x86 architectures, so if you are writting portable code,
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* make sure not to rely on its reordering guarantees.
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*
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static inline void sync_set_bit(int nr, volatile unsigned long * addr)
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{
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__asm__ __volatile__("lock; btsl %1,%0"
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:"+m" (ADDR)
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:"Ir" (nr)
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: "memory");
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}
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/**
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* sync_clear_bit - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* sync_clear_bit() is atomic and may not be reordered. However, it does
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* not contain a memory barrier, so if it is used for locking purposes,
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* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
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* in order to ensure changes are visible on other processors.
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*/
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static inline void sync_clear_bit(int nr, volatile unsigned long * addr)
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{
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__asm__ __volatile__("lock; btrl %1,%0"
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:"+m" (ADDR)
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:"Ir" (nr)
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: "memory");
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}
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/**
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* sync_change_bit - Toggle a bit in memory
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* @nr: Bit to change
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* @addr: Address to start counting from
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*
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* change_bit() is atomic and may not be reordered. It may be
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* reordered on other architectures than x86.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static inline void sync_change_bit(int nr, volatile unsigned long * addr)
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{
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__asm__ __volatile__("lock; btcl %1,%0"
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:"+m" (ADDR)
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:"Ir" (nr)
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: "memory");
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}
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/**
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* sync_test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It may be reordered on other architectures than x86.
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* It also implies a memory barrier.
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*/
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static inline int sync_test_and_set_bit(int nr, volatile unsigned long * addr)
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{
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int oldbit;
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__asm__ __volatile__("lock; btsl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit),"+m" (ADDR)
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:"Ir" (nr) : "memory");
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return oldbit;
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}
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/**
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* sync_test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It can be reorderdered on other architectures other than x86.
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* It also implies a memory barrier.
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*/
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static inline int sync_test_and_clear_bit(int nr, volatile unsigned long * addr)
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{
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int oldbit;
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__asm__ __volatile__("lock; btrl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit),"+m" (ADDR)
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:"Ir" (nr) : "memory");
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return oldbit;
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}
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/**
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* sync_test_and_change_bit - Change a bit and return its old value
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* @nr: Bit to change
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int sync_test_and_change_bit(int nr, volatile unsigned long* addr)
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{
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int oldbit;
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__asm__ __volatile__("lock; btcl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit),"+m" (ADDR)
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:"Ir" (nr) : "memory");
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return oldbit;
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}
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static __always_inline int sync_const_test_bit(int nr, const volatile unsigned long *addr)
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{
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return ((1UL << (nr & 31)) &
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(((const volatile unsigned int *)addr)[nr >> 5])) != 0;
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}
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static inline int sync_var_test_bit(int nr, const volatile unsigned long * addr)
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{
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int oldbit;
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__asm__ __volatile__("btl %2,%1\n\tsbbl %0,%0"
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:"=r" (oldbit)
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:"m" (ADDR),"Ir" (nr));
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return oldbit;
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}
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#define sync_test_bit(nr,addr) \
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(__builtin_constant_p(nr) ? \
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sync_constant_test_bit((nr),(addr)) : \
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sync_var_test_bit((nr),(addr)))
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#undef ADDR
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#endif /* _I386_SYNC_BITOPS_H */
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@ -267,6 +267,9 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
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#define cmpxchg(ptr,o,n)\
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((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
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(unsigned long)(n),sizeof(*(ptr))))
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#define sync_cmpxchg(ptr,o,n)\
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((__typeof__(*(ptr)))__sync_cmpxchg((ptr),(unsigned long)(o),\
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(unsigned long)(n),sizeof(*(ptr))))
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#endif
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static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
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@ -296,6 +299,39 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
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return old;
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}
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/*
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* Always use locked operations when touching memory shared with a
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* hypervisor, since the system may be SMP even if the guest kernel
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* isn't.
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*/
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static inline unsigned long __sync_cmpxchg(volatile void *ptr,
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unsigned long old,
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unsigned long new, int size)
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{
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unsigned long prev;
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switch (size) {
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case 1:
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__asm__ __volatile__("lock; cmpxchgb %b1,%2"
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: "=a"(prev)
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: "q"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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case 2:
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__asm__ __volatile__("lock; cmpxchgw %w1,%2"
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: "=a"(prev)
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: "r"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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case 4:
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__asm__ __volatile__("lock; cmpxchgl %1,%2"
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: "=a"(prev)
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: "r"(new), "m"(*__xg(ptr)), "0"(old)
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: "memory");
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return prev;
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}
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return old;
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}
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#ifndef CONFIG_X86_CMPXCHG
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/*
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* Building a kernel capable running on 80386. It may be necessary to
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