drm/radeon: implement pci config reset for CIK (v3)
pci config reset is a low level reset that resets the entire chip from the bus interface. It can be more reliable if soft reset fails. v2: fix rebase v3: hide behind module parameter Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
4a5c8ea59f
commit
0279ed19bd
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@ -4880,6 +4880,160 @@ static void cik_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
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cik_print_gpu_status_regs(rdev);
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}
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struct kv_reset_save_regs {
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u32 gmcon_reng_execute;
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u32 gmcon_misc;
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u32 gmcon_misc3;
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};
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static void kv_save_regs_for_reset(struct radeon_device *rdev,
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struct kv_reset_save_regs *save)
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{
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save->gmcon_reng_execute = RREG32(GMCON_RENG_EXECUTE);
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save->gmcon_misc = RREG32(GMCON_MISC);
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save->gmcon_misc3 = RREG32(GMCON_MISC3);
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WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute & ~RENG_EXECUTE_ON_PWR_UP);
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WREG32(GMCON_MISC, save->gmcon_misc & ~(RENG_EXECUTE_ON_REG_UPDATE |
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STCTRL_STUTTER_EN));
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}
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static void kv_restore_regs_for_reset(struct radeon_device *rdev,
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struct kv_reset_save_regs *save)
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{
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int i;
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WREG32(GMCON_PGFSM_WRITE, 0);
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WREG32(GMCON_PGFSM_CONFIG, 0x200010ff);
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for (i = 0; i < 5; i++)
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WREG32(GMCON_PGFSM_WRITE, 0);
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WREG32(GMCON_PGFSM_WRITE, 0);
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WREG32(GMCON_PGFSM_CONFIG, 0x300010ff);
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for (i = 0; i < 5; i++)
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WREG32(GMCON_PGFSM_WRITE, 0);
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WREG32(GMCON_PGFSM_WRITE, 0x210000);
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WREG32(GMCON_PGFSM_CONFIG, 0xa00010ff);
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for (i = 0; i < 5; i++)
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WREG32(GMCON_PGFSM_WRITE, 0);
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WREG32(GMCON_PGFSM_WRITE, 0x21003);
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WREG32(GMCON_PGFSM_CONFIG, 0xb00010ff);
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for (i = 0; i < 5; i++)
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WREG32(GMCON_PGFSM_WRITE, 0);
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WREG32(GMCON_PGFSM_WRITE, 0x2b00);
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WREG32(GMCON_PGFSM_CONFIG, 0xc00010ff);
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for (i = 0; i < 5; i++)
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WREG32(GMCON_PGFSM_WRITE, 0);
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WREG32(GMCON_PGFSM_WRITE, 0);
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WREG32(GMCON_PGFSM_CONFIG, 0xd00010ff);
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for (i = 0; i < 5; i++)
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WREG32(GMCON_PGFSM_WRITE, 0);
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WREG32(GMCON_PGFSM_WRITE, 0x420000);
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WREG32(GMCON_PGFSM_CONFIG, 0x100010ff);
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for (i = 0; i < 5; i++)
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WREG32(GMCON_PGFSM_WRITE, 0);
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WREG32(GMCON_PGFSM_WRITE, 0x120202);
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WREG32(GMCON_PGFSM_CONFIG, 0x500010ff);
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for (i = 0; i < 5; i++)
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WREG32(GMCON_PGFSM_WRITE, 0);
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WREG32(GMCON_PGFSM_WRITE, 0x3e3e36);
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WREG32(GMCON_PGFSM_CONFIG, 0x600010ff);
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for (i = 0; i < 5; i++)
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WREG32(GMCON_PGFSM_WRITE, 0);
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WREG32(GMCON_PGFSM_WRITE, 0x373f3e);
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WREG32(GMCON_PGFSM_CONFIG, 0x700010ff);
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for (i = 0; i < 5; i++)
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WREG32(GMCON_PGFSM_WRITE, 0);
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WREG32(GMCON_PGFSM_WRITE, 0x3e1332);
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WREG32(GMCON_PGFSM_CONFIG, 0xe00010ff);
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WREG32(GMCON_MISC3, save->gmcon_misc3);
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WREG32(GMCON_MISC, save->gmcon_misc);
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WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute);
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}
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static void cik_gpu_pci_config_reset(struct radeon_device *rdev)
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{
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struct evergreen_mc_save save;
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struct kv_reset_save_regs kv_save = { 0 };
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u32 tmp, i;
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dev_info(rdev->dev, "GPU pci config reset\n");
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/* disable dpm? */
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/* disable cg/pg */
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cik_fini_pg(rdev);
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cik_fini_cg(rdev);
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/* Disable GFX parsing/prefetching */
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WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
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/* Disable MEC parsing/prefetching */
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WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);
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/* sdma0 */
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tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
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tmp |= SDMA_HALT;
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WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
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/* sdma1 */
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tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
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tmp |= SDMA_HALT;
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WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
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/* XXX other engines? */
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/* halt the rlc, disable cp internal ints */
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cik_rlc_stop(rdev);
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udelay(50);
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/* disable mem access */
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evergreen_mc_stop(rdev, &save);
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if (evergreen_mc_wait_for_idle(rdev)) {
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dev_warn(rdev->dev, "Wait for MC idle timed out !\n");
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}
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if (rdev->flags & RADEON_IS_IGP)
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kv_save_regs_for_reset(rdev, &kv_save);
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/* disable BM */
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pci_clear_master(rdev->pdev);
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/* reset */
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radeon_pci_config_reset(rdev);
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udelay(100);
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/* wait for asic to come out of reset */
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for (i = 0; i < rdev->usec_timeout; i++) {
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if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
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break;
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udelay(1);
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}
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/* does asic init need to be run first??? */
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if (rdev->flags & RADEON_IS_IGP)
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kv_restore_regs_for_reset(rdev, &kv_save);
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}
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/**
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* cik_asic_reset - soft reset GPU
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*
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@ -4898,10 +5052,17 @@ int cik_asic_reset(struct radeon_device *rdev)
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if (reset_mask)
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r600_set_bios_scratch_engine_hung(rdev, true);
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/* try soft reset */
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cik_gpu_soft_reset(rdev, reset_mask);
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reset_mask = cik_gpu_check_soft_reset(rdev);
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/* try pci config reset */
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if (reset_mask && radeon_hard_reset)
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cik_gpu_pci_config_reset(rdev);
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reset_mask = cik_gpu_check_soft_reset(rdev);
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if (!reset_mask)
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r600_set_bios_scratch_engine_hung(rdev, false);
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@ -724,6 +724,17 @@
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#define ATC_MISC_CG 0x3350
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#define GMCON_RENG_EXECUTE 0x3508
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#define RENG_EXECUTE_ON_PWR_UP (1 << 0)
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#define GMCON_MISC 0x350c
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#define RENG_EXECUTE_ON_REG_UPDATE (1 << 11)
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#define STCTRL_STUTTER_EN (1 << 16)
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#define GMCON_PGFSM_CONFIG 0x3538
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#define GMCON_PGFSM_WRITE 0x353c
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#define GMCON_PGFSM_READ 0x3540
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#define GMCON_MISC3 0x3544
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#define MC_SEQ_CNTL_3 0x3600
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# define CAC_EN (1 << 31)
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#define MC_SEQ_G5PDX_CTRL 0x3604
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