First round of binding update for meson clocks targeted at v4.18

-----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEE9OFZrhjz9W1fG7cb5vwPHDfy2oUFAlr76nMACgkQ5vwPHDfy
 2oVDeg//Ywa4opAx7L7YJacnMKHXjbFNblngk1n1JHZ/vFXTgzngnMXFW0Nxb7zv
 FWRqJxwKxyhr2HK7oDCZ6cQkqKF3xlUnz/gdgfZ0YBLwuavSyHctwC5FzfVGLePv
 aXJ8IKAlN3W5SE4jv8+jeSVAfRZo9NALLbxX8pKha8XI3r+rJ3BSjuTXdxCs0s05
 CQzN/3MKfl2jfOwEaDJoMDB6za5tEB4YGr8NXMiX+UARajeadZX9mztPydgK1x5n
 gX/IQ3yoHyWGSl+ISPdwBfkScjcYZSliD88lVlE/Fj/Mps1zKoWpB61hZQ3fwuAb
 Py21fyMcGvQ1725fxLIWyhnz7pfs+DSME8NwtF6DeJiQSi4PP0xTzsyAcnUD9fA9
 fX0eG7rlfDnW5UhuDhM/Q4m1KFksPXrhJTw0kiFPbGTVLOUS/QPcLZg4fB5ajLko
 OhqUcUHQidMIhwMbGUHDV8ZFfm9wmLcX+zTYb+BxKIOWZ7k7Ymx2nbtwvm91JlqR
 zu3yNH9I/xp4yrxwSbIPWUJpuHuT8hJvtnla2/oIfUu2QNgY7qfB8aluQ0PNzl5m
 ItwFYQdp7oe75UbW3YKaBFQbLDMuyRQV6SHA8T8UlaBxv70I3avahgFs2wz8K+53
 8RezGRyyHqxjj11406TXdsIVWqvRi4JK4PYWKFkUzy1a026Edu8=
 =VQUJ
 -----END PGP SIGNATURE-----

Merge tag 'for-kevin-meson-clk-bindings-v4.18-1' of https://github.com/BayLibre/clk-meson into v4.18/dt64

First round of binding update for meson clocks targeted at v4.18

# gpg: Signature made Wed May 16 01:23:15 2018 PDT
# gpg:                using RSA key F4E159AE18F3F56D5F1BB71BE6FC0F1C37F2DA85
# gpg: Can't check signature: No public key

* tag 'for-kevin-meson-clk-bindings-v4.18-1' of https://github.com/BayLibre/clk-meson:
  dt-bindings: clock: reset: Add AXG AO Clock and Reset Bindings
  dt-bindings: clock: axg-aoclkc: New binding for Meson-AXG SoC
  clk: meson: gxbb: expose VDEC_1 and VDEC_HEVC clocks
  dt-bindings: clock: meson8b: export the NAND clock

Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt

@@ -9,6 +9,7 @@ Required Properties:
 	- GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
 	- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
 	- GXM (S912) : "amlogic,meson-gxm-aoclkc"
+	- AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
 	followed by the common "amlogic,meson-gx-aoclkc"
 
 - #clock-cells: should be 1.

include/dt-bindings/clock/axg-aoclkc.h

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_AXG_AOCLK
+
+#define CLKID_AO_REMOTE		0
+#define CLKID_AO_I2C_MASTER	1
+#define CLKID_AO_I2C_SLAVE	2
+#define CLKID_AO_UART1		3
+#define CLKID_AO_UART2		4
+#define CLKID_AO_IR_BLASTER	5
+#define CLKID_AO_SAR_ADC	6
+#define CLKID_AO_CLK81		7
+#define CLKID_AO_SAR_ADC_SEL	8
+#define CLKID_AO_SAR_ADC_DIV	9
+#define CLKID_AO_SAR_ADC_CLK	10
+#define CLKID_AO_ALT_XTAL	11
+
+#endif

include/dt-bindings/clock/gxbb-clkc.h

@@ -125,5 +125,7 @@
 #define CLKID_VAPB_1		138
 #define CLKID_VAPB_SEL		139
 #define CLKID_VAPB		140
+#define CLKID_VDEC_1		153
+#define CLKID_VDEC_HEVC		156
 
 #endif /* __GXBB_CLKC_H */

include/dt-bindings/clock/meson8b-clkc.h

@@ -102,5 +102,6 @@
 #define CLKID_MPLL0		93
 #define CLKID_MPLL1		94
 #define CLKID_MPLL2		95
+#define CLKID_NAND_CLK		112
 
 #endif /* __MESON8B_CLKC_H */

include/dt-bindings/reset/axg-aoclkc.h

@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (c) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2018 Amlogic, inc.
+ * Author: Qiufang Dai <qiufang.dai@amlogic.com>
+ */
+
+#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
+
+#define RESET_AO_REMOTE		0
+#define RESET_AO_I2C_MASTER	1
+#define RESET_AO_I2C_SLAVE	2
+#define RESET_AO_UART1		3
+#define RESET_AO_UART2		4
+#define RESET_AO_IR_BLASTER	5
+
+#endif