iwlwifi: pcie: make iwl_pcie_txq_update_byte_cnt_tbl bus independent
To avoid duplicating code we need to call iwl_pcie_txq_update_byte_cnt_tbl function from non bus independent code so make it bus independent. Used spatch rule @r1@ struct iwl_trans_pcie *trans_pcie; @@ ( -trans_pcie->scd_bc_tbls +trans->txqs.scd_bc_tbls | -iwl_pcie_txq_update_byte_cnt_tbl +iwl_txq_gen1_update_byte_cnt_tbl | -iwl_pcie_txq_inval_byte_cnt_tbl +iwl_txq_gen1_inval_byte_cnt_tbl | -iwl_pcie_tfd_unmap +iwl_txq_gen1_tfd_unmap | -iwl_pcie_tfd_tb_get_addr +iwl_txq_gen1_tfd_tb_get_addr | -iwl_pcie_tfd_tb_get_len +iwl_txq_gen1_tfd_tb_get_len | -iwl_pcie_tfd_get_num_tbs +iwl_txq_gen1_tfd_get_num_tbs ) /* clean all new unused variables */ @ depends on r1@ type T; identifier i; expression E; @@ - T i = E; ... when != i Signed-off-by: Mordechay Goodstein <mordechay.goodstein@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com> Link: https://lore.kernel.org/r/iwlwifi.20200930191738.8d33e791ec8c.Ica35125ed640aa3aa1ecc38fb5e8f1600caa8df6@changeid Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
This commit is contained in:
Mordechay Goodstein
Luca Coelho
parent
20e671998c
commit
0179bfff97
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@ -918,6 +918,7 @@ struct iwl_txq {
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* @dev_cmd_offs: offset from skb->cb to iwl_device_tx_cmd pointer
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* @queue_used - bit mask of used queues
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* @queue_stopped - bit mask of stopped queues
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* @scd_bc_tbls: gen1 pointer to the byte count table of the scheduler
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*/
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struct iwl_trans_txqs {
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unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)];
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@ -941,6 +942,8 @@ struct iwl_trans_txqs {
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u16 size;
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u8 addr_size;
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} tfd;
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struct iwl_dma_ptr scd_bc_tbls;
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};
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/**
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@ -338,7 +338,6 @@ struct cont_rec {
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* count for allocating and freeing the memory.
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* @trans: pointer to the generic transport area
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* @scd_base_addr: scheduler sram base address in SRAM
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* @scd_bc_tbls: pointer to the byte count table of the scheduler
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* @kw: keep warm address
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* @pci_dev: basic pci-network driver stuff
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* @hw_base: pci hardware address support
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@ -409,7 +408,6 @@ struct iwl_trans_pcie {
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struct mutex mutex;
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u32 inta_mask;
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u32 scd_base_addr;
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struct iwl_dma_ptr scd_bc_tbls;
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struct iwl_dma_ptr kw;
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struct iwl_txq *txq_memory;
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@ -555,22 +553,6 @@ void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
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void iwl_trans_pcie_set_q_ptrs(struct iwl_trans *trans, int txq_id, int ptr);
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void iwl_trans_pcie_tx_reset(struct iwl_trans *trans);
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static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_trans *trans, void *_tfd,
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u8 idx)
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{
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if (trans->trans_cfg->use_tfh) {
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struct iwl_tfh_tfd *tfd = _tfd;
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struct iwl_tfh_tb *tb = &tfd->tbs[idx];
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return le16_to_cpu(tb->tb_len);
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} else {
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struct iwl_tfd *tfd = _tfd;
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struct iwl_tfd_tb *tb = &tfd->tbs[idx];
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return le16_to_cpu(tb->hi_n_len) >> 4;
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}
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}
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/*****************************************************
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* Error handling
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******************************************************/
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@ -2954,7 +2954,7 @@ static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
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int i;
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for (i = 0; i < trans->txqs.tfd.max_tbs; i++)
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cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
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cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i);
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return cmdlen;
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}
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@ -77,9 +77,6 @@
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#include "internal.h"
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#include "fw/api/tx.h"
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#define IWL_TX_CRC_SIZE 4
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#define IWL_TX_DELIMITER_SIZE 4
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/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
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* DMA services
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*
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@ -126,81 +123,6 @@ void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr)
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memset(ptr, 0, sizeof(*ptr));
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}
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/*
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* iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
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*/
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static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
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struct iwl_txq *txq, u16 byte_cnt,
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int num_tbs)
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{
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struct iwlagn_scd_bc_tbl *scd_bc_tbl;
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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int write_ptr = txq->write_ptr;
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int txq_id = txq->id;
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u8 sec_ctl = 0;
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u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
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__le16 bc_ent;
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struct iwl_device_tx_cmd *dev_cmd = txq->entries[txq->write_ptr].cmd;
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struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload;
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u8 sta_id = tx_cmd->sta_id;
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scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
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sec_ctl = tx_cmd->sec_ctl;
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switch (sec_ctl & TX_CMD_SEC_MSK) {
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case TX_CMD_SEC_CCM:
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len += IEEE80211_CCMP_MIC_LEN;
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break;
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case TX_CMD_SEC_TKIP:
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len += IEEE80211_TKIP_ICV_LEN;
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break;
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case TX_CMD_SEC_WEP:
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len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
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break;
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}
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if (trans->txqs.bc_table_dword)
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len = DIV_ROUND_UP(len, 4);
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if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX))
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return;
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bc_ent = cpu_to_le16(len | (sta_id << 12));
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scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
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if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
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scd_bc_tbl[txq_id].
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tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
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}
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static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
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struct iwl_txq *txq)
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{
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struct iwl_trans_pcie *trans_pcie =
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IWL_TRANS_GET_PCIE_TRANS(trans);
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struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
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int txq_id = txq->id;
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int read_ptr = txq->read_ptr;
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u8 sta_id = 0;
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__le16 bc_ent;
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struct iwl_device_tx_cmd *dev_cmd = txq->entries[read_ptr].cmd;
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struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload;
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WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
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if (txq_id != trans->txqs.cmd.q_id)
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sta_id = tx_cmd->sta_id;
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bc_ent = cpu_to_le16(1 | (sta_id << 12));
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scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
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if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
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scd_bc_tbl[txq_id].
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tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
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}
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/*
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* iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
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*/
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@ -267,35 +189,6 @@ void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
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}
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}
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static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_trans *trans,
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void *_tfd, u8 idx)
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{
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if (trans->trans_cfg->use_tfh) {
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struct iwl_tfh_tfd *tfd = _tfd;
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struct iwl_tfh_tb *tb = &tfd->tbs[idx];
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return (dma_addr_t)(le64_to_cpu(tb->addr));
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} else {
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struct iwl_tfd *tfd = _tfd;
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struct iwl_tfd_tb *tb = &tfd->tbs[idx];
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dma_addr_t addr = get_unaligned_le32(&tb->lo);
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dma_addr_t hi_len;
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if (sizeof(dma_addr_t) <= sizeof(u32))
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return addr;
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hi_len = le16_to_cpu(tb->hi_n_len) & 0xF;
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/*
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* shift by 16 twice to avoid warnings on 32-bit
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* (where this code never runs anyway due to the
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* if statement above)
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*/
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return addr | ((hi_len << 16) << 16);
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}
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}
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static inline void iwl_pcie_tfd_set_tb(struct iwl_trans *trans, void *tfd,
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u8 idx, dma_addr_t addr, u16 len)
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{
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@ -312,66 +205,6 @@ static inline void iwl_pcie_tfd_set_tb(struct iwl_trans *trans, void *tfd,
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tfd_fh->num_tbs = idx + 1;
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}
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static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_trans *trans, void *_tfd)
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{
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if (trans->trans_cfg->use_tfh) {
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struct iwl_tfh_tfd *tfd = _tfd;
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return le16_to_cpu(tfd->num_tbs) & 0x1f;
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} else {
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struct iwl_tfd *tfd = _tfd;
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return tfd->num_tbs & 0x1f;
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}
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}
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static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
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struct iwl_cmd_meta *meta,
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struct iwl_txq *txq, int index)
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{
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int i, num_tbs;
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void *tfd = iwl_txq_get_tfd(trans, txq, index);
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/* Sanity check on number of chunks */
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num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd);
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if (num_tbs > trans->txqs.tfd.max_tbs) {
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IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
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/* @todo issue fatal error, it is quite serious situation */
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return;
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}
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/* first TB is never freed - it's the bidirectional DMA data */
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for (i = 1; i < num_tbs; i++) {
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if (meta->tbs & BIT(i))
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dma_unmap_page(trans->dev,
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iwl_pcie_tfd_tb_get_addr(trans, tfd, i),
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iwl_pcie_tfd_tb_get_len(trans, tfd, i),
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DMA_TO_DEVICE);
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else
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dma_unmap_single(trans->dev,
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iwl_pcie_tfd_tb_get_addr(trans, tfd,
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i),
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iwl_pcie_tfd_tb_get_len(trans, tfd,
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i),
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DMA_TO_DEVICE);
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}
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meta->tbs = 0;
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if (trans->trans_cfg->use_tfh) {
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struct iwl_tfh_tfd *tfd_fh = (void *)tfd;
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tfd_fh->num_tbs = 0;
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} else {
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struct iwl_tfd *tfd_fh = (void *)tfd;
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tfd_fh->num_tbs = 0;
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}
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}
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/*
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* iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
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* @trans - transport private data
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@ -394,7 +227,7 @@ void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
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/* We have only q->n_window txq->entries, but we use
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* TFD_QUEUE_SIZE_MAX tfds
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*/
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iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, txq, rd_ptr);
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iwl_txq_gen1_tfd_unmap(trans, &txq->entries[idx].meta, txq, rd_ptr);
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/* free SKB */
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if (txq->entries) {
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@ -424,7 +257,7 @@ static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
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if (reset)
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memset(tfd, 0, trans->txqs.tfd.size);
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num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd);
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num_tbs = iwl_txq_gen1_tfd_get_num_tbs(trans, tfd);
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/* Each TFD can point to a maximum max_tbs Tx buffers */
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if (num_tbs >= trans->txqs.tfd.max_tbs) {
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@ -579,7 +412,7 @@ void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
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NULL, clear_dwords);
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iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
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trans_pcie->scd_bc_tbls.dma >> 10);
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trans->txqs.scd_bc_tbls.dma >> 10);
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/* The chain extension of the SCD doesn't work well. This feature is
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* enabled by default by the HW, so we need to disable it manually.
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@ -744,7 +577,7 @@ void iwl_pcie_tx_free(struct iwl_trans *trans)
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iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
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iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
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iwl_pcie_free_dma_ptr(trans, &trans->txqs.scd_bc_tbls);
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}
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/*
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@ -770,7 +603,7 @@ static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
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goto error;
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}
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ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
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ret = iwl_pcie_alloc_dma_ptr(trans, &trans->txqs.scd_bc_tbls,
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bc_tbls_size);
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if (ret) {
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IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
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@ -971,7 +804,7 @@ void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
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txq->entries[read_ptr].skb = NULL;
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if (!trans->trans_cfg->use_tfh)
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iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
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iwl_txq_gen1_inval_byte_cnt_tbl(trans, txq);
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iwl_pcie_txq_free_tfd(trans, txq);
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}
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@ -1528,8 +1361,8 @@ static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
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copy_size - tb0_size,
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DMA_TO_DEVICE);
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if (dma_mapping_error(trans->dev, phys_addr)) {
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iwl_pcie_tfd_unmap(trans, out_meta, txq,
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txq->write_ptr);
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iwl_txq_gen1_tfd_unmap(trans, out_meta, txq,
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txq->write_ptr);
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idx = -ENOMEM;
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goto out;
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}
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@ -1552,8 +1385,8 @@ static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
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phys_addr = dma_map_single(trans->dev, (void *)data,
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cmdlen[i], DMA_TO_DEVICE);
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if (dma_mapping_error(trans->dev, phys_addr)) {
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iwl_pcie_tfd_unmap(trans, out_meta, txq,
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txq->write_ptr);
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iwl_txq_gen1_tfd_unmap(trans, out_meta, txq,
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txq->write_ptr);
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idx = -ENOMEM;
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goto out;
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}
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@ -1633,7 +1466,7 @@ void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
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group_id = cmd->hdr.group_id;
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cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0);
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iwl_pcie_tfd_unmap(trans, meta, txq, index);
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iwl_txq_gen1_tfd_unmap(trans, meta, txq, index);
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/* Input error checking is done when commands are added to queue. */
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if (meta->flags & CMD_WANT_SKB) {
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@ -2241,8 +2074,9 @@ int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
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tfd = iwl_txq_get_tfd(trans, txq, txq->write_ptr);
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/* Set up entry for this TFD in Tx byte-count array */
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iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len),
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iwl_pcie_tfd_get_num_tbs(trans, tfd));
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iwl_txq_gen1_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len),
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iwl_txq_gen1_tfd_get_num_tbs(trans,
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tfd));
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wait_write_ptr = ieee80211_has_morefrags(fc);
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@ -2273,7 +2107,7 @@ int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
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spin_unlock(&txq->lock);
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return 0;
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out_err:
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iwl_pcie_tfd_unmap(trans, out_meta, txq, txq->write_ptr);
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iwl_txq_gen1_tfd_unmap(trans, out_meta, txq, txq->write_ptr);
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spin_unlock(&txq->lock);
|
||||
return -1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1373,3 +1373,157 @@ error:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static inline dma_addr_t iwl_txq_gen1_tfd_tb_get_addr(struct iwl_trans *trans,
|
||||
void *_tfd, u8 idx)
|
||||
{
|
||||
struct iwl_tfd *tfd;
|
||||
struct iwl_tfd_tb *tb;
|
||||
dma_addr_t addr;
|
||||
dma_addr_t hi_len;
|
||||
|
||||
if (trans->trans_cfg->use_tfh) {
|
||||
struct iwl_tfh_tfd *tfd = _tfd;
|
||||
struct iwl_tfh_tb *tb = &tfd->tbs[idx];
|
||||
|
||||
return (dma_addr_t)(le64_to_cpu(tb->addr));
|
||||
}
|
||||
|
||||
tfd = _tfd;
|
||||
tb = &tfd->tbs[idx];
|
||||
addr = get_unaligned_le32(&tb->lo);
|
||||
|
||||
if (sizeof(dma_addr_t) <= sizeof(u32))
|
||||
return addr;
|
||||
|
||||
hi_len = le16_to_cpu(tb->hi_n_len) & 0xF;
|
||||
|
||||
/*
|
||||
* shift by 16 twice to avoid warnings on 32-bit
|
||||
* (where this code never runs anyway due to the
|
||||
* if statement above)
|
||||
*/
|
||||
return addr | ((hi_len << 16) << 16);
|
||||
}
|
||||
|
||||
void iwl_txq_gen1_tfd_unmap(struct iwl_trans *trans,
|
||||
struct iwl_cmd_meta *meta,
|
||||
struct iwl_txq *txq, int index)
|
||||
{
|
||||
int i, num_tbs;
|
||||
void *tfd = iwl_txq_get_tfd(trans, txq, index);
|
||||
|
||||
/* Sanity check on number of chunks */
|
||||
num_tbs = iwl_txq_gen1_tfd_get_num_tbs(trans, tfd);
|
||||
|
||||
if (num_tbs > trans->txqs.tfd.max_tbs) {
|
||||
IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
|
||||
/* @todo issue fatal error, it is quite serious situation */
|
||||
return;
|
||||
}
|
||||
|
||||
/* first TB is never freed - it's the bidirectional DMA data */
|
||||
|
||||
for (i = 1; i < num_tbs; i++) {
|
||||
if (meta->tbs & BIT(i))
|
||||
dma_unmap_page(trans->dev,
|
||||
iwl_txq_gen1_tfd_tb_get_addr(trans,
|
||||
tfd, i),
|
||||
iwl_txq_gen1_tfd_tb_get_len(trans,
|
||||
tfd, i),
|
||||
DMA_TO_DEVICE);
|
||||
else
|
||||
dma_unmap_single(trans->dev,
|
||||
iwl_txq_gen1_tfd_tb_get_addr(trans,
|
||||
tfd, i),
|
||||
iwl_txq_gen1_tfd_tb_get_len(trans,
|
||||
tfd, i),
|
||||
DMA_TO_DEVICE);
|
||||
}
|
||||
|
||||
meta->tbs = 0;
|
||||
|
||||
if (trans->trans_cfg->use_tfh) {
|
||||
struct iwl_tfh_tfd *tfd_fh = (void *)tfd;
|
||||
|
||||
tfd_fh->num_tbs = 0;
|
||||
} else {
|
||||
struct iwl_tfd *tfd_fh = (void *)tfd;
|
||||
|
||||
tfd_fh->num_tbs = 0;
|
||||
}
|
||||
}
|
||||
|
||||
#define IWL_TX_CRC_SIZE 4
|
||||
#define IWL_TX_DELIMITER_SIZE 4
|
||||
|
||||
/*
|
||||
* iwl_txq_gen1_update_byte_cnt_tbl - Set up entry in Tx byte-count array
|
||||
*/
|
||||
void iwl_txq_gen1_update_byte_cnt_tbl(struct iwl_trans *trans,
|
||||
struct iwl_txq *txq, u16 byte_cnt,
|
||||
int num_tbs)
|
||||
{
|
||||
struct iwlagn_scd_bc_tbl *scd_bc_tbl;
|
||||
int write_ptr = txq->write_ptr;
|
||||
int txq_id = txq->id;
|
||||
u8 sec_ctl = 0;
|
||||
u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
|
||||
__le16 bc_ent;
|
||||
struct iwl_device_tx_cmd *dev_cmd = txq->entries[txq->write_ptr].cmd;
|
||||
struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload;
|
||||
u8 sta_id = tx_cmd->sta_id;
|
||||
|
||||
scd_bc_tbl = trans->txqs.scd_bc_tbls.addr;
|
||||
|
||||
sec_ctl = tx_cmd->sec_ctl;
|
||||
|
||||
switch (sec_ctl & TX_CMD_SEC_MSK) {
|
||||
case TX_CMD_SEC_CCM:
|
||||
len += IEEE80211_CCMP_MIC_LEN;
|
||||
break;
|
||||
case TX_CMD_SEC_TKIP:
|
||||
len += IEEE80211_TKIP_ICV_LEN;
|
||||
break;
|
||||
case TX_CMD_SEC_WEP:
|
||||
len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
|
||||
break;
|
||||
}
|
||||
if (trans->txqs.bc_table_dword)
|
||||
len = DIV_ROUND_UP(len, 4);
|
||||
|
||||
if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX))
|
||||
return;
|
||||
|
||||
bc_ent = cpu_to_le16(len | (sta_id << 12));
|
||||
|
||||
scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
|
||||
|
||||
if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
|
||||
scd_bc_tbl[txq_id].tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] =
|
||||
bc_ent;
|
||||
}
|
||||
|
||||
void iwl_txq_gen1_inval_byte_cnt_tbl(struct iwl_trans *trans,
|
||||
struct iwl_txq *txq)
|
||||
{
|
||||
struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans->txqs.scd_bc_tbls.addr;
|
||||
int txq_id = txq->id;
|
||||
int read_ptr = txq->read_ptr;
|
||||
u8 sta_id = 0;
|
||||
__le16 bc_ent;
|
||||
struct iwl_device_tx_cmd *dev_cmd = txq->entries[read_ptr].cmd;
|
||||
struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload;
|
||||
|
||||
WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
|
||||
|
||||
if (txq_id != trans->txqs.cmd.q_id)
|
||||
sta_id = tx_cmd->sta_id;
|
||||
|
||||
bc_ent = cpu_to_le16(1 | (sta_id << 12));
|
||||
|
||||
scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
|
||||
|
||||
if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
|
||||
scd_bc_tbl[txq_id].tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] =
|
||||
bc_ent;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -185,4 +185,46 @@ int iwl_txq_gen2_init(struct iwl_trans *trans, int txq_id, int queue_size);
|
|||
struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len,
|
||||
struct sk_buff *skb);
|
||||
#endif
|
||||
static inline u8 iwl_txq_gen1_tfd_get_num_tbs(struct iwl_trans *trans,
|
||||
void *_tfd)
|
||||
{
|
||||
struct iwl_tfd *tfd;
|
||||
|
||||
if (trans->trans_cfg->use_tfh) {
|
||||
struct iwl_tfh_tfd *tfd = _tfd;
|
||||
|
||||
return le16_to_cpu(tfd->num_tbs) & 0x1f;
|
||||
}
|
||||
|
||||
tfd = (struct iwl_tfd *)_tfd;
|
||||
return tfd->num_tbs & 0x1f;
|
||||
}
|
||||
|
||||
static inline u16 iwl_txq_gen1_tfd_tb_get_len(struct iwl_trans *trans,
|
||||
void *_tfd, u8 idx)
|
||||
{
|
||||
struct iwl_tfd *tfd;
|
||||
struct iwl_tfd_tb *tb;
|
||||
|
||||
if (trans->trans_cfg->use_tfh) {
|
||||
struct iwl_tfh_tfd *tfd = _tfd;
|
||||
struct iwl_tfh_tb *tb = &tfd->tbs[idx];
|
||||
|
||||
return le16_to_cpu(tb->tb_len);
|
||||
}
|
||||
|
||||
tfd = (struct iwl_tfd *)_tfd;
|
||||
tb = &tfd->tbs[idx];
|
||||
|
||||
return le16_to_cpu(tb->hi_n_len) >> 4;
|
||||
}
|
||||
|
||||
void iwl_txq_gen1_tfd_unmap(struct iwl_trans *trans,
|
||||
struct iwl_cmd_meta *meta,
|
||||
struct iwl_txq *txq, int index);
|
||||
void iwl_txq_gen1_inval_byte_cnt_tbl(struct iwl_trans *trans,
|
||||
struct iwl_txq *txq);
|
||||
void iwl_txq_gen1_update_byte_cnt_tbl(struct iwl_trans *trans,
|
||||
struct iwl_txq *txq, u16 byte_cnt,
|
||||
int num_tbs);
|
||||
#endif /* __iwl_trans_queue_tx_h__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue