ASoC: fsl-sai: Convert to use regmap framework's endianness method.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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@ -18,9 +18,8 @@ Required properties:
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- pinctrl-names: Must contain a "default" entry.
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- pinctrl-NNN: One property must exist for each entry in pinctrl-names.
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See ../pinctrl/pinctrl-bindings.txt for details of the property values.
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- big-endian-regs: If this property is absent, the little endian mode will
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be in use as default, or the big endian mode will be in use for all the
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device registers.
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- big-endian: Boolean property, required if all the FTM_PWM registers
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are big-endian rather than little-endian.
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- big-endian-data: If this property is absent, the little endian mode will
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be in use as default, or the big endian mode will be in use for all the
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fifo data.
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@ -38,6 +37,6 @@ sai2: sai@40031000 {
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dma-names = "tx", "rx";
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dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>,
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<&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>;
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big-endian-regs;
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big-endian;
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big-endian-data;
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};
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@ -539,7 +539,7 @@ static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
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}
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}
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static struct regmap_config fsl_sai_regmap_config = {
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static const struct regmap_config fsl_sai_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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@ -568,10 +568,6 @@ static int fsl_sai_probe(struct platform_device *pdev)
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if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx6sx-sai"))
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sai->sai_on_imx = true;
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sai->big_endian_regs = of_property_read_bool(np, "big-endian-regs");
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if (sai->big_endian_regs)
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fsl_sai_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;
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sai->big_endian_data = of_property_read_bool(np, "big-endian-data");
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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@ -131,7 +131,6 @@ struct fsl_sai {
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struct clk *bus_clk;
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struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
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bool big_endian_regs;
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bool big_endian_data;
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bool is_dsp_mode;
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bool sai_on_imx;
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