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net: dsa: mv88e6xx: fix supported_interfaces setup in mv88e6250_phylink_get_caps() 

[ Upstream commit a4e3899065ffa87d49dc20e8c17501edbc189692 ]

With the recent PHYLINK changes requiring supported_interfaces to be set,
MV88E6250 family switches like the 88E6020 fail to probe - cmode is
never initialized on these devices, so mv88e6250_phylink_get_caps() does
not set any supported_interfaces flags.

Instead of a cmode, on 88E6250 we have a read-only port mode value that
encodes similar information. There is no reason to bother mapping port
mode to the cmodes of other switch models; instead we introduce a
mv88e6250_setup_supported_interfaces() that is called directly from
mv88e6250_phylink_get_caps().

Fixes: de5c9bf40c ("net: phylink: require supported_interfaces to be filled")
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Link: https://lore.kernel.org/r/20240417103737.166651-1-matthias.schiffer@ew.tq-group.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Matthias Schiffer 2024-04-17 12:37:37 +02:00 committed by Greg Kroah-Hartman
parent b50bb50392
commit 0142cbb87c
2 changed files with 71 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
drivers/net/dsa/mv88e6xxx/chip.c
View File

@ -566,13 +566,61 @@ static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported)
phy_interface_set_rgmii(supported);
}
static void
mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip *chip, int port,
struct phylink_config *config)
{
unsigned long *supported = config->supported_interfaces;
int err;
u16 reg;
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);
if (err) {
dev_err(chip->dev, "p%d: failed to read port status\n", port);
return;
}
switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) {
case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY:
case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY:
case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY:
case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY:
__set_bit(PHY_INTERFACE_MODE_REVMII, supported);
break;
case MV88E6250_PORT_STS_PORTMODE_MII_HALF:
case MV88E6250_PORT_STS_PORTMODE_MII_FULL:
__set_bit(PHY_INTERFACE_MODE_MII, supported);
break;
case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY:
case MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY:
case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY:
case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY:
__set_bit(PHY_INTERFACE_MODE_REVRMII, supported);
break;
case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL:
case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL:
__set_bit(PHY_INTERFACE_MODE_RMII, supported);
break;
case MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII:
__set_bit(PHY_INTERFACE_MODE_RGMII, supported);
break;
default:
dev_err(chip->dev,
"p%d: invalid port mode in status register: %04x\n",
port, reg);
}
}
static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
struct phylink_config *config)
{
unsigned long *supported = config->supported_interfaces;
/* Translate the default cmode */
mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
if (!mv88e6xxx_phy_is_internal(chip, port))
mv88e6250_setup_supported_interfaces(chip, port, config);
config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
}

23
drivers/net/dsa/mv88e6xxx/port.h
View File

@ -25,10 +25,25 @@
#define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900
#define MV88E6250_PORT_STS_PORTMODE_PHY_10_FULL 0x0a00
#define MV88E6250_PORT_STS_PORTMODE_PHY_100_FULL 0x0b00
#define MV88E6250_PORT_STS_PORTMODE_MII_10_HALF 0x0c00
#define MV88E6250_PORT_STS_PORTMODE_MII_100_HALF 0x0d00
#define MV88E6250_PORT_STS_PORTMODE_MII_10_FULL 0x0e00
#define MV88E6250_PORT_STS_PORTMODE_MII_100_FULL 0x0f00
/* - Modes with PHY suffix use output instead of input clock
* - Modes without RMII or RGMII use MII
* - Modes without speed do not have a fixed speed specified in the manual
* ("DC to x MHz" - variable clock support?)
*/
#define MV88E6250_PORT_STS_PORTMODE_MII_DISABLED 0x0000
#define MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII 0x0100
#define MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY 0x0200
#define MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY 0x0400
#define MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL 0x0600
#define MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL 0x0700
#define MV88E6250_PORT_STS_PORTMODE_MII_HALF 0x0800
#define MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY 0x0900
#define MV88E6250_PORT_STS_PORTMODE_MII_FULL 0x0a00
#define MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY 0x0b00
#define MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY 0x0c00
#define MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY 0x0d00
#define MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY 0x0e00
#define MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY 0x0f00
#define MV88E6XXX_PORT_STS_LINK 0x0800
#define MV88E6XXX_PORT_STS_DUPLEX 0x0400
#define MV88E6XXX_PORT_STS_SPEED_MASK 0x0300