dt-bindings: net: dsa: Add documentation for NXP SJA1105 driver
Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Vladimir Oltean
David S. Miller
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4759209732
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013fe01d45
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NXP SJA1105 switch driver
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=========================
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Required properties:
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- compatible:
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Must be one of:
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- "nxp,sja1105e"
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- "nxp,sja1105t"
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- "nxp,sja1105p"
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- "nxp,sja1105q"
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- "nxp,sja1105r"
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- "nxp,sja1105s"
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Although the device ID could be detected at runtime, explicit bindings
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are required in order to be able to statically check their validity.
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For example, SGMII can only be specified on port 4 of R and S devices,
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and the non-SGMII devices, while pin-compatible, are not equal in terms
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of support for RGMII internal delays (supported on P/Q/R/S, but not on
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E/T).
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Optional properties:
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- sja1105,role-mac:
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- sja1105,role-phy:
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Boolean properties that can be assigned under each port node. By
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default (unless otherwise specified) a port is configured as MAC if it
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is driving a PHY (phy-handle is present) or as PHY if it is PHY-less
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(fixed-link specified, presumably because it is connected to a MAC).
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The effect of this property (in either its implicit or explicit form)
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is:
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- In the case of MII or RMII it specifies whether the SJA1105 port is a
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clock source or sink for this interface (not applicable for RGMII
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where there is a Tx and an Rx clock).
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- In the case of RGMII it affects the behavior regarding internal
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delays:
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1. If sja1105,role-mac is specified, and the phy-mode property is one
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of "rgmii-id", "rgmii-txid" or "rgmii-rxid", then the entity
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designated to apply the delay/clock skew necessary for RGMII
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is the PHY. The SJA1105 MAC does not apply any internal delays.
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2. If sja1105,role-phy is specified, and the phy-mode property is one
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of the above, the designated entity to apply the internal delays
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is the SJA1105 MAC (if hardware-supported). This is only supported
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by the second-generation (P/Q/R/S) hardware. On a first-generation
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E or T device, it is an error to specify an RGMII phy-mode other
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than "rgmii" for a port that is in fixed-link mode. In that case,
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the clock skew must either be added by the MAC at the other end of
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the fixed-link, or by PCB serpentine traces on the board.
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These properties are required, for example, in the case where SJA1105
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ports are at both ends of a MII/RMII PHY-less setup. One end would need
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to have sja1105,role-mac, while the other sja1105,role-phy.
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See Documentation/devicetree/bindings/net/dsa/dsa.txt for the list of standard
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DSA required and optional properties.
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Other observations
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------------------
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The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944) of at least
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one half of t_CLK. At an SPI frequency of 1MHz, this means a minimum
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cs_sck_delay of 500ns. Ensuring that this SPI timing requirement is observed
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depends on the SPI bus master driver.
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Example
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-------
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Ethernet switch connected via SPI to the host, CPU port wired to enet2:
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arch/arm/boot/dts/ls1021a-tsn.dts:
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/* SPI controller of the LS1021 */
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&dspi0 {
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sja1105@1 {
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reg = <0x1>;
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nxp,sja1105t";
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spi-max-frequency = <4000000>;
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fsl,spi-cs-sck-delay = <1000>;
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fsl,spi-sck-cs-delay = <1000>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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/* ETH5 written on chassis */
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label = "swp5";
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phy-handle = <&rgmii_phy6>;
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phy-mode = "rgmii-id";
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reg = <0>;
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/* Implicit "sja1105,role-mac;" */
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};
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port@1 {
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/* ETH2 written on chassis */
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label = "swp2";
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phy-handle = <&rgmii_phy3>;
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phy-mode = "rgmii-id";
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reg = <1>;
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/* Implicit "sja1105,role-mac;" */
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};
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port@2 {
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/* ETH3 written on chassis */
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label = "swp3";
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phy-handle = <&rgmii_phy4>;
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phy-mode = "rgmii-id";
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reg = <2>;
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/* Implicit "sja1105,role-mac;" */
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};
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port@3 {
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/* ETH4 written on chassis */
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phy-handle = <&rgmii_phy5>;
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label = "swp4";
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phy-mode = "rgmii-id";
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reg = <3>;
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/* Implicit "sja1105,role-mac;" */
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};
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port@4 {
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/* Internal port connected to eth2 */
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ethernet = <&enet2>;
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phy-mode = "rgmii";
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reg = <4>;
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/* Implicit "sja1105,role-phy;" */
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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};
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/* MDIO controller of the LS1021 */
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&mdio0 {
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/* BCM5464 */
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rgmii_phy3: ethernet-phy@3 {
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reg = <0x3>;
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};
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rgmii_phy4: ethernet-phy@4 {
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reg = <0x4>;
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};
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rgmii_phy5: ethernet-phy@5 {
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reg = <0x5>;
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};
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rgmii_phy6: ethernet-phy@6 {
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reg = <0x6>;
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};
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};
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/* Ethernet master port of the LS1021 */
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&enet2 {
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phy-connection-type = "rgmii";
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status = "ok";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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