drm/amd/display: Force delay after DP receive power up
[Why] Some sprcified monitor scalar cannot recognize timing change on demand. Once the link phy disable and enable during a short period then the Sink protection mechanism could keep the screen in blank and cannot be recoverred. [How] To add 100ms delay between enable link phy and link training. Signed-off-by: Martin Tsai <martin.tsai@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1559,9 +1559,10 @@ bool perform_link_training_with_retries(
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pipe_ctx->clock_source->id,
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link_setting);
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if (stream->sink_patches.dppowerup_delay > 0) {
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int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;
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if ((link && link->dc->debug.dppowerup_delay > 0) || stream->sink_patches.dppowerup_delay > 0) {
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int delay_dp_power_up_in_ms =
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(link->dc->debug.dppowerup_delay >= stream->sink_patches.dppowerup_delay) ?
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link->dc->debug.dppowerup_delay : stream->sink_patches.dppowerup_delay;
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msleep(delay_dp_power_up_in_ms);
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}
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@ -498,6 +498,7 @@ struct dc_debug_options {
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bool usbc_combo_phy_reset_wa;
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bool disable_dsc;
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bool enable_dram_clock_change_one_display_vactive;
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unsigned int dppowerup_delay;
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};
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struct dc_debug_data {
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