soc/tegra: pmc: Fix reset sources and levels
Commit5f84bb1a40
("soc/tegra: pmc: Add sysfs entries for reset info") added support for reading the Tegra reset source and level from sysfs. However, there are a few issues with this commit which are ... 1. The number of reset sources for Tegra210 is defined as 5 but it should be 6. 2. The number of reset sources for Tegra186 is defined as 13 but it should be 15. 3. The SoC data variables num_reset_sources and num_reset_levels are defined but never used. Fix the above by ... 1. Removing the reset source 'AOTAG' from the tegra30_reset_sources because this is only applicable for Tegra210. 2. Adding a new tegra210_reset_sources structure for Tegra210 reset sources. 3. Correct the number of reset sources for Tegra210 and Tegra186 by using the ARRAY_SIZE macro. 4. Updating the functions reset_reason_show() and reset_level_show() to check whether the value read is valid. While we are at it clean-up these functions to remove an unnecessary u32 variable. Fixes:5f84bb1a40
("soc/tegra: pmc: Add sysfs entries for reset info") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
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7fe5719b43
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00cdaa1b81
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@ -268,6 +268,14 @@ static const char * const tegra186_reset_levels[] = {
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};
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};
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static const char * const tegra30_reset_sources[] = {
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static const char * const tegra30_reset_sources[] = {
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"POWER_ON_RESET",
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"WATCHDOG",
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"SENSOR",
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"SW_MAIN",
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"LP0"
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};
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static const char * const tegra210_reset_sources[] = {
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"POWER_ON_RESET",
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"POWER_ON_RESET",
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"WATCHDOG",
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"WATCHDOG",
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"SENSOR",
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"SENSOR",
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@ -1736,13 +1744,16 @@ static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)
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static ssize_t reset_reason_show(struct device *dev,
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static ssize_t reset_reason_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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struct device_attribute *attr, char *buf)
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{
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{
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u32 value, rst_src;
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u32 value;
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value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
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value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
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rst_src = (value & pmc->soc->regs->rst_source_mask) >>
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value &= pmc->soc->regs->rst_source_mask;
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pmc->soc->regs->rst_source_shift;
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value >>= pmc->soc->regs->rst_source_shift;
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return sprintf(buf, "%s\n", pmc->soc->reset_sources[rst_src]);
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if (WARN_ON(value >= pmc->soc->num_reset_sources))
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return sprintf(buf, "%s\n", "UNKNOWN");
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return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
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}
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}
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static DEVICE_ATTR_RO(reset_reason);
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static DEVICE_ATTR_RO(reset_reason);
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@ -1750,13 +1761,16 @@ static DEVICE_ATTR_RO(reset_reason);
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static ssize_t reset_level_show(struct device *dev,
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static ssize_t reset_level_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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struct device_attribute *attr, char *buf)
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{
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{
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u32 value, rst_lvl;
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u32 value;
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value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
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value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
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rst_lvl = (value & pmc->soc->regs->rst_level_mask) >>
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value &= pmc->soc->regs->rst_level_mask;
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pmc->soc->regs->rst_level_shift;
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value >>= pmc->soc->regs->rst_level_shift;
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return sprintf(buf, "%s\n", pmc->soc->reset_levels[rst_lvl]);
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if (WARN_ON(value >= pmc->soc->num_reset_levels))
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return sprintf(buf, "%s\n", "UNKNOWN");
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return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
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}
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}
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static DEVICE_ATTR_RO(reset_level);
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static DEVICE_ATTR_RO(reset_level);
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@ -2212,7 +2226,7 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = {
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.init = tegra20_pmc_init,
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.init = tegra20_pmc_init,
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.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
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.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
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.reset_sources = tegra30_reset_sources,
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.reset_sources = tegra30_reset_sources,
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.num_reset_sources = 5,
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.num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
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.reset_levels = NULL,
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.reset_levels = NULL,
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.num_reset_levels = 0,
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.num_reset_levels = 0,
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};
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};
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@ -2263,7 +2277,7 @@ static const struct tegra_pmc_soc tegra114_pmc_soc = {
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.init = tegra20_pmc_init,
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.init = tegra20_pmc_init,
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.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
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.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
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.reset_sources = tegra30_reset_sources,
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.reset_sources = tegra30_reset_sources,
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.num_reset_sources = 5,
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.num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
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.reset_levels = NULL,
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.reset_levels = NULL,
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.num_reset_levels = 0,
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.num_reset_levels = 0,
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};
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};
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@ -2374,7 +2388,7 @@ static const struct tegra_pmc_soc tegra124_pmc_soc = {
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.init = tegra20_pmc_init,
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.init = tegra20_pmc_init,
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.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
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.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
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.reset_sources = tegra30_reset_sources,
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.reset_sources = tegra30_reset_sources,
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.num_reset_sources = 5,
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.num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
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.reset_levels = NULL,
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.reset_levels = NULL,
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.num_reset_levels = 0,
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.num_reset_levels = 0,
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};
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};
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@ -2479,8 +2493,8 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {
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.regs = &tegra20_pmc_regs,
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.regs = &tegra20_pmc_regs,
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.init = tegra20_pmc_init,
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.init = tegra20_pmc_init,
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.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
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.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
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.reset_sources = tegra30_reset_sources,
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.reset_sources = tegra210_reset_sources,
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.num_reset_sources = 5,
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.num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
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.reset_levels = NULL,
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.reset_levels = NULL,
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.num_reset_levels = 0,
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.num_reset_levels = 0,
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};
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};
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@ -2605,9 +2619,9 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = {
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.init = NULL,
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.init = NULL,
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.setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
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.setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
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.reset_sources = tegra186_reset_sources,
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.reset_sources = tegra186_reset_sources,
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.num_reset_sources = 14,
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.num_reset_sources = ARRAY_SIZE(tegra186_reset_sources),
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.reset_levels = tegra186_reset_levels,
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.reset_levels = tegra186_reset_levels,
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.num_reset_levels = 3,
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.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
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.num_wake_events = ARRAY_SIZE(tegra186_wake_events),
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.num_wake_events = ARRAY_SIZE(tegra186_wake_events),
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.wake_events = tegra186_wake_events,
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.wake_events = tegra186_wake_events,
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};
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};
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