Qualcomm ARM Based Device Tree Updates for v3.18
* Added APQ8084 dt support for clocks, serial, pinctrl, and IFC6540 board * Added IPQ8064 dt support for basic SoC and AP148 board * Added APQ8064 dt support for pinctrl, reset, SDHC, and multimedia clocks * Added PMIC 8058 dt support on MSM8660, enables PMIC based power key, keypad, rtc, and vibrator * Added PMIC 8921 dt support on MSM8960, enables PMIC based power key, keypad, and rtc -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: GPGTools - https://gpgtools.org iQIcBAABCgAGBQJUE0thAAoJEF9hYXeAcXzB1LcQAJNWsOLCGdq966OZDs6gC78k +aCfW4EtoqgzC3auNVkgeAhz35p0GkmNTMBOoEpAH1UF7lavUM3v7EpKr29b2iKw tcfcvYddgHcfXuVVoR+QE/cf8Z36utQN5fdEJgmwWD4RQJGdfXrSP1dZQ7PVMCt+ LIVMEdD70Jc404FqQnUW0jLG9f7vOyM62HcuDGjh7l1HHA0I36476zFGlTzym+tn NrNJV1BZHcCgIq2iVUMyCj+rlB4QTrNd8xLwddA3vV02xgyFmpWVEnX0MJVACpwl uIRWZe3IlNSdMsEE0mAHBjuuyjdDtnR52V7OEepd8XqA9js4RwltlFIpeXysVEcq e8yzpAY4AgXy11oKWPH0zR9ErpxKr/VWXEuB+XW3oqgFs9t29GcCttf6zXwOdtIf p958ARd3KfPVFcSr3OHsqWXLBBI9IKoS42v8KLZ8k54WBg4Pc/pcsDSvOAu65D5o CTF/ECfBOHGnrbXmFWIIprLWsbakEzbknb8OuETP44h1FNEWZJIak3HusWKhJLSQ OBnI9/jPTGeKYepb0Zf5ZoRfZ55oAfa8Jx1YJEjzcfIuIPfogD3EACtElQa3wwhO MowBggkdc6HxEdCc98qHPlvQtMUjTzC0MteII0/M+/ZPvXHSEzFp1NAGZwoj1y4Y 6UMGNmhnRBv83NKqo2lE =L0k9 -----END PGP SIGNATURE----- Merge tag 'qcom-dt-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/dt Merge "qcom DT changes for v3.18" from Kumar Gala: Qualcomm ARM Based Device Tree Updates for v3.18 * Added APQ8084 dt support for clocks, serial, pinctrl, and IFC6540 board * Added IPQ8064 dt support for basic SoC and AP148 board * Added APQ8064 dt support for pinctrl, reset, SDHC, and multimedia clocks * Added PMIC 8058 dt support on MSM8660, enables PMIC based power key, keypad, rtc, and vibrator * Added PMIC 8921 dt support on MSM8960, enables PMIC based power key, keypad, and rtc * tag 'qcom-dt-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom: ARM: DT: QCOM: apq8064: Add dma support for sdcc node ARM: DT: apq8064: Add sdcc support via mcci driver. ARM: dts: qcom: Add 8064 multimedia clock controller node ARM: DT: APQ8064: Add node for ps_hold function in pinctrl ARM: DT: APQ8064: Add pinctrl support ARM: dts: qcom: Add TLMM DT node for APQ8084 ARM: dts: qcom: Add initial IFC6540 board device tree ARM: dts: msm: Add 8058 PMIC to ssbi bus ARM: dts: msm: Add 8921 PMIC to ssbi bus ARM: qcom: Add initial IPQ8064 SoC and AP148 device trees ARM: dts: qcom: Add APQ8084 serial port DT node ARM: dts: qcom: Add APQ8084 Global Clock Controller DT node Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
007c7fdbdf
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@ -346,7 +346,9 @@ dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
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dtb-$(CONFIG_ARCH_QCOM) += \
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qcom-apq8064-ifc6410.dtb \
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qcom-apq8074-dragonboard.dtb \
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qcom-apq8084-ifc6540.dtb \
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qcom-apq8084-mtp.dtb \
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qcom-ipq8064-ap148.dtb \
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qcom-msm8660-surf.dtb \
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qcom-msm8960-cdp.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += \
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@ -12,5 +12,17 @@
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status = "ok";
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};
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};
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amba {
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/* eMMC */
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sdcc1: sdcc@12400000 {
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status = "okay";
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};
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/* External micro SD card */
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sdcc3: sdcc@12180000 {
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status = "okay";
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};
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};
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};
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};
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@ -2,7 +2,9 @@
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/qcom,gcc-msm8960.h>
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#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Qualcomm APQ8064";
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@ -70,6 +72,27 @@
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ranges;
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compatible = "simple-bus";
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tlmm_pinmux: pinctrl@800000 {
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compatible = "qcom,apq8064-pinctrl";
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reg = <0x800000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&ps_hold>;
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ps_hold: ps_hold {
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mux {
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pins = "gpio78";
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function = "ps_hold";
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};
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};
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};
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intc: interrupt-controller@2000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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@ -166,5 +189,85 @@
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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mmcc: clock-controller@4000000 {
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compatible = "qcom,mmcc-apq8064";
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reg = <0x4000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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/* Temporary fixed regulator */
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vsdcc_fixed: vsdcc-regulator {
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compatible = "regulator-fixed";
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regulator-name = "SDCC Power";
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regulator-min-microvolt = <2700000>;
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regulator-max-microvolt = <2700000>;
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regulator-always-on;
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};
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sdcc1bam:dma@12402000{
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compatible = "qcom,bam-v1.3.0";
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reg = <0x12402000 0x8000>;
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interrupts = <0 98 0>;
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clocks = <&gcc SDC1_H_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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};
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sdcc3bam:dma@12182000{
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compatible = "qcom,bam-v1.3.0";
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reg = <0x12182000 0x8000>;
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interrupts = <0 96 0>;
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clocks = <&gcc SDC3_H_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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};
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amba {
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compatible = "arm,amba-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sdcc1: sdcc@12400000 {
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status = "disabled";
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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reg = <0x12400000 0x2000>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cmd_irq";
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clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
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clock-names = "mclk", "apb_pclk";
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bus-width = <8>;
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max-frequency = <96000000>;
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non-removable;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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vmmc-supply = <&vsdcc_fixed>;
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dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
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dma-names = "tx", "rx";
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};
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sdcc3: sdcc@12180000 {
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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status = "disabled";
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reg = <0x12180000 0x2000>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cmd_irq";
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clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
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clock-names = "mclk", "apb_pclk";
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bus-width = <4>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <192000000>;
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no-1-8-v;
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vmmc-supply = <&vsdcc_fixed>;
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dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
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dma-names = "tx", "rx";
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};
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};
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};
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};
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@ -0,0 +1,23 @@
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#include "qcom-apq8084.dtsi"
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/ {
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model = "Qualcomm APQ8084/IFC6540";
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compatible = "qcom,apq8084-ifc6540", "qcom,apq8084";
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soc {
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serial@f995e000 {
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status = "okay";
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};
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sdhci@f9824900 {
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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sdhci@f98a4900 {
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cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>;
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bus-width = <4>;
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};
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};
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};
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@ -3,4 +3,10 @@
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/ {
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model = "Qualcomm APQ 8084-MTP";
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compatible = "qcom,apq8084-mtp", "qcom,apq8084";
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soc {
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serial@f995e000 {
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status = "okay";
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};
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};
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};
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@ -2,6 +2,9 @@
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/qcom,gcc-apq8084.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Qualcomm APQ 8084";
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compatible = "qcom,apq8084";
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@ -175,5 +178,53 @@
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compatible = "qcom,pshold";
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reg = <0xfc4ab000 0x4>;
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};
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gcc: clock-controller@fc400000 {
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compatible = "qcom,gcc-apq8084";
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#clock-cells = <1>;
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#reset-cells = <1>;
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reg = <0xfc400000 0x4000>;
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};
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tlmm: pinctrl@fd510000 {
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compatible = "qcom,apq8084-pinctrl";
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reg = <0xfd510000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 208 0>;
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};
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serial@f995e000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0xf995e000 0x1000>;
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interrupts = <0 114 0x0>;
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clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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sdhci@f9824900 {
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compatible = "qcom,sdhci-msm-v4";
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reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
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reg-names = "hc_mem", "core_mem";
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interrupts = <0 123 0>, <0 138 0>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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sdhci@f98a4900 {
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compatible = "qcom,sdhci-msm-v4";
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reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
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reg-names = "hc_mem", "core_mem";
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interrupts = <0 125 0>, <0 221 0>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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};
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};
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@ -0,0 +1,85 @@
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#include "qcom-ipq8064-v1.0.dtsi"
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/ {
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model = "Qualcomm IPQ8064/AP148";
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compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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rsvd@41200000 {
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reg = <0x41200000 0x300000>;
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no-map;
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};
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};
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soc {
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pinmux@800000 {
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i2c4_pins: i2c4_pinmux {
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pins = "gpio12", "gpio13";
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function = "gsbi4";
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bias-disable;
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};
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spi_pins: spi_pins {
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mux {
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pins = "gpio18", "gpio19", "gpio21";
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function = "gsbi5";
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drive-strength = <10>;
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bias-none;
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};
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};
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};
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gsbi@16300000 {
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qcom,mode = <GSBI_PROT_I2C_UART>;
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status = "ok";
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serial@16340000 {
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status = "ok";
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};
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i2c4: i2c@16380000 {
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status = "ok";
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clock-frequency = <200000>;
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pinctrl-0 = <&i2c4_pins>;
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pinctrl-names = "default";
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};
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};
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gsbi5: gsbi@1a200000 {
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qcom,mode = <GSBI_PROT_SPI>;
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status = "ok";
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spi4: spi@1a280000 {
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status = "ok";
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spi-max-frequency = <50000000>;
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pinctrl-0 = <&spi_pins>;
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pinctrl-names = "default";
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cs-gpios = <&qcom_pinmux 20 0>;
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flash: m25p80@0 {
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compatible = "s25fl256s1";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <50000000>;
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reg = <0>;
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partition@0 {
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label = "rootfs";
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reg = <0x0 0x1000000>;
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};
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partition@1 {
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label = "scratch";
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reg = <0x1000000 0x1000000>;
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};
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};
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};
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};
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};
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};
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@ -0,0 +1 @@
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#include "qcom-ipq8064.dtsi"
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@ -0,0 +1,250 @@
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/dts-v1/;
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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/ {
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model = "Qualcomm IPQ8064";
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compatible = "qcom,ipq8064";
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interrupt-parent = <&intc>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc0>;
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qcom,saw = <&saw0>;
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};
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cpu@1 {
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compatible = "qcom,krait";
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enable-method = "qcom,kpss-acc-v1";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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qcom,acc = <&acc1>;
|
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qcom,saw = <&saw1>;
|
||||
};
|
||||
|
||||
L2: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu-pmu {
|
||||
compatible = "qcom,krait-pmu";
|
||||
interrupts = <1 10 0x304>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
nss@40000000 {
|
||||
reg = <0x40000000 0x1000000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
smem@41000000 {
|
||||
reg = <0x41000000 0x200000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
compatible = "simple-bus";
|
||||
|
||||
qcom_pinmux: pinmux@800000 {
|
||||
compatible = "qcom,ipq8064-pinctrl";
|
||||
reg = <0x800000 0x4000>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0 32 0x4>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@2000000 {
|
||||
compatible = "qcom,msm-qgic2";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x02000000 0x1000>,
|
||||
<0x02002000 0x1000>;
|
||||
};
|
||||
|
||||
timer@200a000 {
|
||||
compatible = "qcom,kpss-timer", "qcom,msm-timer";
|
||||
interrupts = <1 1 0x301>,
|
||||
<1 2 0x301>,
|
||||
<1 3 0x301>;
|
||||
reg = <0x0200a000 0x100>;
|
||||
clock-frequency = <25000000>,
|
||||
<32768>;
|
||||
cpu-offset = <0x80000>;
|
||||
};
|
||||
|
||||
acc0: clock-controller@2088000 {
|
||||
compatible = "qcom,kpss-acc-v1";
|
||||
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
|
||||
};
|
||||
|
||||
acc1: clock-controller@2098000 {
|
||||
compatible = "qcom,kpss-acc-v1";
|
||||
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
|
||||
};
|
||||
|
||||
saw0: regulator@2089000 {
|
||||
compatible = "qcom,saw2";
|
||||
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
|
||||
regulator;
|
||||
};
|
||||
|
||||
saw1: regulator@2099000 {
|
||||
compatible = "qcom,saw2";
|
||||
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
|
||||
regulator;
|
||||
};
|
||||
|
||||
gsbi2: gsbi@12480000 {
|
||||
compatible = "qcom,gsbi-v1.0.0";
|
||||
reg = <0x12480000 0x100>;
|
||||
clocks = <&gcc GSBI2_H_CLK>;
|
||||
clock-names = "iface";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
serial@12490000 {
|
||||
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
||||
reg = <0x12490000 0x1000>,
|
||||
<0x12480000 0x1000>;
|
||||
interrupts = <0 195 0x0>;
|
||||
clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@124a0000 {
|
||||
compatible = "qcom,i2c-qup-v1.1.1";
|
||||
reg = <0x124a0000 0x1000>;
|
||||
interrupts = <0 196 0>;
|
||||
|
||||
clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
gsbi4: gsbi@16300000 {
|
||||
compatible = "qcom,gsbi-v1.0.0";
|
||||
reg = <0x16300000 0x100>;
|
||||
clocks = <&gcc GSBI4_H_CLK>;
|
||||
clock-names = "iface";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
serial@16340000 {
|
||||
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
||||
reg = <0x16340000 0x1000>,
|
||||
<0x16300000 0x1000>;
|
||||
interrupts = <0 152 0x0>;
|
||||
clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@16380000 {
|
||||
compatible = "qcom,i2c-qup-v1.1.1";
|
||||
reg = <0x16380000 0x1000>;
|
||||
interrupts = <0 153 0>;
|
||||
|
||||
clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
gsbi5: gsbi@1a200000 {
|
||||
compatible = "qcom,gsbi-v1.0.0";
|
||||
reg = <0x1a200000 0x100>;
|
||||
clocks = <&gcc GSBI5_H_CLK>;
|
||||
clock-names = "iface";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
status = "disabled";
|
||||
|
||||
serial@1a240000 {
|
||||
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
||||
reg = <0x1a240000 0x1000>,
|
||||
<0x1a200000 0x1000>;
|
||||
interrupts = <0 154 0x0>;
|
||||
clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@1a280000 {
|
||||
compatible = "qcom,i2c-qup-v1.1.1";
|
||||
reg = <0x1a280000 0x1000>;
|
||||
interrupts = <0 155 0>;
|
||||
|
||||
clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
spi@1a280000 {
|
||||
compatible = "qcom,spi-qup-v1.1.1";
|
||||
reg = <0x1a280000 0x1000>;
|
||||
interrupts = <0 155 0>;
|
||||
|
||||
clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,ssbi@500000 {
|
||||
compatible = "qcom,ssbi";
|
||||
reg = <0x00500000 0x1000>;
|
||||
qcom,controller-type = "pmic-arbiter";
|
||||
};
|
||||
|
||||
gcc: clock-controller@900000 {
|
||||
compatible = "qcom,gcc-ipq8064";
|
||||
reg = <0x00900000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,3 +1,5 @@
|
|||
#include <dt-bindings/input/input.h>
|
||||
|
||||
#include "qcom-msm8660.dtsi"
|
||||
|
||||
/ {
|
||||
|
|
@ -14,3 +16,31 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmicintc {
|
||||
keypad@148 {
|
||||
linux,keymap = <
|
||||
MATRIX_KEY(0, 0, KEY_FN_F1)
|
||||
MATRIX_KEY(0, 1, KEY_UP)
|
||||
MATRIX_KEY(0, 2, KEY_LEFT)
|
||||
MATRIX_KEY(0, 3, KEY_VOLUMEUP)
|
||||
MATRIX_KEY(1, 0, KEY_FN_F2)
|
||||
MATRIX_KEY(1, 1, KEY_RIGHT)
|
||||
MATRIX_KEY(1, 2, KEY_DOWN)
|
||||
MATRIX_KEY(1, 3, KEY_VOLUMEDOWN)
|
||||
MATRIX_KEY(2, 3, KEY_ENTER)
|
||||
MATRIX_KEY(4, 0, KEY_CAMERA_FOCUS)
|
||||
MATRIX_KEY(4, 1, KEY_UP)
|
||||
MATRIX_KEY(4, 2, KEY_LEFT)
|
||||
MATRIX_KEY(4, 3, KEY_HOME)
|
||||
MATRIX_KEY(4, 4, KEY_FN_F3)
|
||||
MATRIX_KEY(5, 0, KEY_CAMERA)
|
||||
MATRIX_KEY(5, 1, KEY_RIGHT)
|
||||
MATRIX_KEY(5, 2, KEY_DOWN)
|
||||
MATRIX_KEY(5, 3, KEY_BACK)
|
||||
MATRIX_KEY(5, 4, KEY_MENU)
|
||||
>;
|
||||
keypad,num-rows = <6>;
|
||||
keypad,num-columns = <5>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -103,6 +103,48 @@
|
|||
compatible = "qcom,ssbi";
|
||||
reg = <0x500000 0x1000>;
|
||||
qcom,controller-type = "pmic-arbiter";
|
||||
|
||||
pmicintc: pmic@0 {
|
||||
compatible = "qcom,pm8058";
|
||||
interrupt-parent = <&msmgpio>;
|
||||
interrupts = <88 8>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pwrkey@1c {
|
||||
compatible = "qcom,pm8058-pwrkey";
|
||||
reg = <0x1c>;
|
||||
interrupt-parent = <&pmicintc>;
|
||||
interrupts = <50 1>, <51 1>;
|
||||
debounce = <15625>;
|
||||
pull-up;
|
||||
};
|
||||
|
||||
keypad@148 {
|
||||
compatible = "qcom,pm8058-keypad";
|
||||
reg = <0x148>;
|
||||
interrupt-parent = <&pmicintc>;
|
||||
interrupts = <74 1>, <75 1>;
|
||||
debounce = <15>;
|
||||
scan-delay = <32>;
|
||||
row-hold = <91500>;
|
||||
};
|
||||
|
||||
rtc@11d {
|
||||
compatible = "qcom,pm8058-rtc";
|
||||
interrupt-parent = <&pmicintc>;
|
||||
interrupts = <39 1>;
|
||||
reg = <0x11d>;
|
||||
allow-set-time;
|
||||
};
|
||||
|
||||
vibrator@4a {
|
||||
compatible = "qcom,pm8058-vib";
|
||||
reg = <0x4a>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,3 +1,5 @@
|
|||
#include <dt-bindings/input/input.h>
|
||||
|
||||
#include "qcom-msm8960.dtsi"
|
||||
|
||||
/ {
|
||||
|
|
@ -14,3 +16,16 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmicintc {
|
||||
keypad@148 {
|
||||
linux,keymap = <
|
||||
MATRIX_KEY(0, 0, KEY_VOLUMEUP)
|
||||
MATRIX_KEY(0, 1, KEY_VOLUMEDOWN)
|
||||
MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS)
|
||||
MATRIX_KEY(0, 3, KEY_CAMERA)
|
||||
>;
|
||||
keypad,num-rows = <1>;
|
||||
keypad,num-columns = <5>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -143,6 +143,43 @@
|
|||
compatible = "qcom,ssbi";
|
||||
reg = <0x500000 0x1000>;
|
||||
qcom,controller-type = "pmic-arbiter";
|
||||
|
||||
pmicintc: pmic@0 {
|
||||
compatible = "qcom,pm8921";
|
||||
interrupt-parent = <&msmgpio>;
|
||||
interrupts = <104 8>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pwrkey@1c {
|
||||
compatible = "qcom,pm8921-pwrkey";
|
||||
reg = <0x1c>;
|
||||
interrupt-parent = <&pmicintc>;
|
||||
interrupts = <50 1>, <51 1>;
|
||||
debounce = <15625>;
|
||||
pull-up;
|
||||
};
|
||||
|
||||
keypad@148 {
|
||||
compatible = "qcom,pm8921-keypad";
|
||||
reg = <0x148>;
|
||||
interrupt-parent = <&pmicintc>;
|
||||
interrupts = <74 1>, <75 1>;
|
||||
debounce = <15>;
|
||||
scan-delay = <32>;
|
||||
row-hold = <91500>;
|
||||
};
|
||||
|
||||
rtc@11d {
|
||||
compatible = "qcom,pm8921-rtc";
|
||||
interrupt-parent = <&pmicintc>;
|
||||
interrupts = <39 1>;
|
||||
reg = <0x11d>;
|
||||
allow-set-time;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rng@1a500000 {
|
||||
|
|
|
|||
|
|
@ -18,6 +18,8 @@ static const char * const qcom_dt_match[] __initconst = {
|
|||
"qcom,apq8064",
|
||||
"qcom,apq8074-dragonboard",
|
||||
"qcom,apq8084",
|
||||
"qcom,ipq8062",
|
||||
"qcom,ipq8064",
|
||||
"qcom,msm8660-surf",
|
||||
"qcom,msm8960-cdp",
|
||||
NULL
|
||||
|
|
|
|||
Loading…
Reference in New Issue