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!227 [linux-5.4/next] Fix some xHCI issues for Zhaoxin CPUs 

Merge pull request !227 from LeoLiu-oc/linux-5.4-next-09-10-11-12-xhci
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刘诗 2024-09-20 08:16:22 +00:00 committed by Gitee
parent b650f3d75f b35f54c488
commit 007360a952
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GPG Key ID: 173E9B9CA92EEF8F
4 changed files with 67 additions and 38 deletions
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39
drivers/usb/host/xhci-mem.c
View File

@ -2133,7 +2133,7 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
{
u32 temp, port_offset, port_count;
int i;
u8 major_revision, minor_revision;
u8 major_revision, minor_revision, tmp_minor_revision;
struct xhci_hub *rhub;
struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
struct xhci_port_cap *port_cap;
@ -2153,6 +2153,15 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
*/
if (minor_revision > 0x00 && minor_revision < 0x10)
minor_revision <<= 4;
/*
* Some zhaoxin's xHCI controller that follow usb3.1 spec
* but only support Gen1.
*/
if (xhci->quirks & XHCI_ZHAOXIN_HOST) {
tmp_minor_revision = minor_revision;
minor_revision = 0;
}
} else if (major_revision <= 0x02) {
rhub = &xhci->usb2_rhub;
} else {
@ -2162,10 +2171,6 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
/* Ignoring port protocol we can't understand. FIXME */
return;
}
rhub->maj_rev = XHCI_EXT_PORT_MAJOR(temp);
if (rhub->min_rev < minor_revision)
rhub->min_rev = minor_revision;
/* Port offset and count in the third dword, see section 7.2 */
temp = readl(addr + 2);
@ -2184,8 +2189,6 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
if (xhci->num_port_caps > max_caps)
return;
port_cap->maj_rev = major_revision;
port_cap->min_rev = minor_revision;
port_cap->psi_count = XHCI_EXT_PORT_PSIC(temp);
if (port_cap->psi_count) {
@ -2206,6 +2209,11 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
XHCI_EXT_PORT_PSIV(port_cap->psi[i - 1])))
port_cap->psi_uid_count++;
if (xhci->quirks & XHCI_ZHAOXIN_HOST &&
major_revision == 0x03 &&
XHCI_EXT_PORT_PSIV(port_cap->psi[i]) >= 5)
minor_revision = tmp_minor_revision;
xhci_dbg(xhci, "PSIV:%d PSIE:%d PLT:%d PFD:%d LP:%d PSIM:%d\n",
XHCI_EXT_PORT_PSIV(port_cap->psi[i]),
XHCI_EXT_PORT_PSIE(port_cap->psi[i]),
@ -2215,6 +2223,15 @@ static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
XHCI_EXT_PORT_PSIM(port_cap->psi[i]));
}
}
rhub->maj_rev = major_revision;
if (rhub->min_rev < minor_revision)
rhub->min_rev = minor_revision;
port_cap->maj_rev = major_revision;
port_cap->min_rev = minor_revision;
/* cache usb2 port capabilities */
if (major_revision < 0x03 && xhci->num_ext_caps < max_caps)
xhci->ext_caps[xhci->num_ext_caps++] = temp;
@ -2456,8 +2473,12 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
* and our use of dma addresses in the trb_address_map radix tree needs
* TRB_SEGMENT_SIZE alignment, so we pick the greater alignment need.
*/
xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, xhci->page_size);
if (xhci->quirks & XHCI_ZHAOXIN_TRB_FETCH)
xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
TRB_SEGMENT_SIZE * 2, TRB_SEGMENT_SIZE * 2, xhci->page_size * 2);
else
xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, xhci->page_size);
/* See Table 46 and Note on Figure 55 */
xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,

13
drivers/usb/host/xhci-pci.c
View File

@ -322,6 +322,19 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8))
xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
if (pdev->vendor == PCI_VENDOR_ID_ZHAOXIN) {
xhci->quirks |= XHCI_ZHAOXIN_HOST;
xhci->quirks |= XHCI_LPM_SUPPORT;
if (pdev->device == 0x9202) {
xhci->quirks |= XHCI_RESET_ON_RESUME;
xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH;
}
if (pdev->device == 0x9203)
xhci->quirks |= XHCI_ZHAOXIN_TRB_FETCH;
}
if (xhci->quirks & XHCI_RESET_ON_RESUME)
xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
"QUIRK: Resetting on resume");

51
drivers/usb/host/xhci.c
View File

@ -4711,7 +4711,7 @@ static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
}
}
if (xhci->quirks & XHCI_INTEL_HOST)
if (xhci->quirks & (XHCI_INTEL_HOST | XHCI_ZHAOXIN_HOST))
timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
else
timeout_ns = udev->u1_params.sel;
@ -4775,7 +4775,7 @@ static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
}
}
if (xhci->quirks & XHCI_INTEL_HOST)
if (xhci->quirks & (XHCI_INTEL_HOST | XHCI_ZHAOXIN_HOST))
timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
else
timeout_ns = udev->u2_params.sel;
@ -4848,38 +4848,31 @@ static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
return 0;
}
static int xhci_check_intel_tier_policy(struct usb_device *udev,
enum usb3_link_state state)
{
struct usb_device *parent;
unsigned int num_hubs;
if (state == USB3_LPM_U2)
return 0;
/* Don't enable U1 if the device is on a 2nd tier hub or lower. */
for (parent = udev->parent, num_hubs = 0; parent->parent;
parent = parent->parent)
num_hubs++;
if (num_hubs < 2)
return 0;
dev_dbg(&udev->dev, "Disabling U1 link state for device"
" below second-tier hub.\n");
dev_dbg(&udev->dev, "Plug device into first-tier hub "
"to decrease power consumption.\n");
return -E2BIG;
}
static int xhci_check_tier_policy(struct xhci_hcd *xhci,
struct usb_device *udev,
enum usb3_link_state state)
{
if (xhci->quirks & XHCI_INTEL_HOST)
return xhci_check_intel_tier_policy(udev, state);
else
struct usb_device *parent = udev->parent;
int tier = 1; /* roothub is tier1 */
if (state == USB3_LPM_U2)
return 0;
while (parent) {
parent = parent->parent;
tier++;
}
if (xhci->quirks & XHCI_INTEL_HOST && tier > 3)
goto fail;
if (xhci->quirks & XHCI_ZHAOXIN_HOST && tier > 2)
goto fail;
return 0;
fail:
dev_dbg(&udev->dev, "Tier policy prevents U1/U2 LPM states for devices at tier %d\n",
tier);
return -E2BIG;
}
/* Returns the U1 or U2 timeout that should be enabled.

2
drivers/usb/host/xhci.h
View File

@ -1885,6 +1885,8 @@ struct xhci_hcd {
#define XHCI_SKIP_PHY_INIT BIT_ULL(37)
#define XHCI_DISABLE_SPARSE BIT_ULL(38)
#define XHCI_NO_SOFT_RETRY BIT_ULL(40)
#define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45)
#define XHCI_ZHAOXIN_HOST BIT_ULL(46)
unsigned int num_active_eps;
unsigned int limit_active_eps;