drm/amdgpu: update latest IP discovery table structures
Add new tables. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
1d5eee7dd6
commit
005835233a
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@ -27,15 +27,19 @@
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#define PSP_HEADER_SIZE 256
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#define BINARY_SIGNATURE 0x28211407
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#define DISCOVERY_TABLE_SIGNATURE 0x53445049
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#define GC_TABLE_ID 0x4347
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#define HARVEST_TABLE_SIGNATURE 0x56524148
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#define VCN_INFO_TABLE_ID 0x004E4356
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#define MALL_INFO_TABLE_ID 0x4D414C4C
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typedef enum
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{
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IP_DISCOVERY = 0,
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GC,
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HARVEST_INFO,
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TABLE_4,
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VCN_INFO,
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MALL_INFO,
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RESERVED_1,
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RESERVED_2,
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TOTAL_TABLES = 6
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} table;
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@ -96,6 +100,24 @@ typedef struct ip
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uint32_t base_address[]; /* variable number of Addresses */
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} ip;
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typedef struct ip_v3
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{
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uint16_t hw_id; /* Hardware ID */
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uint8_t instance_number; /* Instance number for the IP */
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uint8_t num_base_address; /* Number of base addresses*/
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uint8_t major; /* Hardware ID.major version */
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uint8_t minor; /* Hardware ID.minor version */
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uint8_t revision; /* Hardware ID.revision version */
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#if defined(__BIG_ENDIAN)
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uint8_t variant : 4; /* HW variant */
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uint8_t sub_revision : 4; /* HCID Sub-Revision */
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#else
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uint8_t sub_revision : 4; /* HCID Sub-Revision */
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uint8_t variant : 4; /* HW variant */
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#endif
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uint32_t base_address[1]; /* Base Address list. Corresponds to the num_base_address field*/
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} ip_v3;
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typedef struct die_header
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{
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uint16_t die_id;
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@ -108,7 +130,11 @@ typedef struct ip_structure
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struct die
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{
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die_header *die_header;
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ip *ip_list;
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union
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{
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ip *ip_list;
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ip_v3 *ip_v3_list;
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}; /* IP list. Variable size*/
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} die;
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} ip_structure;
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@ -170,6 +196,40 @@ struct gc_info_v1_1 {
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uint32_t gc_num_tcps;
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};
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struct gc_info_v1_2 {
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struct gpu_info_header header;
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uint32_t gc_num_se;
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uint32_t gc_num_wgp0_per_sa;
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uint32_t gc_num_wgp1_per_sa;
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uint32_t gc_num_rb_per_se;
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uint32_t gc_num_gl2c;
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uint32_t gc_num_gprs;
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uint32_t gc_num_max_gs_thds;
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uint32_t gc_gs_table_depth;
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uint32_t gc_gsprim_buff_depth;
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uint32_t gc_parameter_cache_depth;
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uint32_t gc_double_offchip_lds_buffer;
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uint32_t gc_wave_size;
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uint32_t gc_max_waves_per_simd;
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uint32_t gc_max_scratch_slots_per_cu;
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uint32_t gc_lds_size;
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uint32_t gc_num_sc_per_se;
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uint32_t gc_num_sa_per_se;
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uint32_t gc_num_packer_per_sc;
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uint32_t gc_num_gl2a;
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uint32_t gc_num_tcp_per_sa;
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uint32_t gc_num_sdp_interface;
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uint32_t gc_num_tcps;
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uint32_t gc_num_tcp_per_wpg;
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uint32_t gc_tcp_l1_size;
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uint32_t gc_num_sqc_per_wgp;
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uint32_t gc_l1_instruction_cache_size_per_sqc;
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uint32_t gc_l1_data_cache_size_per_sqc;
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uint32_t gc_gl1c_per_sa;
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uint32_t gc_gl1c_size_per_instance;
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uint32_t gc_gl2c_per_gpu;
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};
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struct gc_info_v2_0 {
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struct gpu_info_header header;
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@ -208,6 +268,54 @@ typedef struct harvest_table {
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harvest_info list[32];
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} harvest_table;
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struct mall_info_header {
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uint32_t table_id; /* table ID */
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uint16_t version_major; /* table version */
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uint16_t version_minor; /* table version */
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uint32_t size_bytes; /* size of the entire header+data in bytes */
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};
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struct mall_info_v1_0 {
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struct mall_info_header header;
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uint32_t mall_size_per_m;
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uint32_t m_s_present;
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uint32_t m_half_use;
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uint32_t m_mall_config;
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uint32_t reserved[5];
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};
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#define VCN_INFO_TABLE_MAX_NUM_INSTANCES 4
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struct vcn_info_header {
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uint32_t table_id; /* table ID */
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uint16_t version_major; /* table version */
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uint16_t version_minor; /* table version */
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uint32_t size_bytes; /* size of the entire header+data in bytes */
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};
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struct vcn_instance_info_v1_0
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{
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uint32_t instance_num; /* VCN IP instance number. 0 - VCN0; 1 - VCN1 etc*/
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union _fuse_data {
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struct {
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uint32_t av1_disabled : 1;
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uint32_t vp9_disabled : 1;
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uint32_t hevc_disabled : 1;
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uint32_t h264_disabled : 1;
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uint32_t reserved : 28;
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} bits;
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uint32_t all_bits;
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} fuse_data;
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uint32_t reserved[2];
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};
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struct vcn_info_v1_0 {
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struct vcn_info_header header;
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uint32_t num_of_instances; /* number of entries used in instance_info below*/
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struct vcn_instance_info_v1_0 instance_info[VCN_INFO_TABLE_MAX_NUM_INSTANCES];
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uint32_t reserved[4];
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};
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#pragma pack()
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#endif
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