pinctrl: bcm2835: Fix ints for GPIOs 28-31 & 46-53
Contrary to the documentation, the BCM2835 GPIO controller actually has four interrupt lines - one each for the three IRQ groups and one common. Confusingly, the GPIO interrupt groups don't correspond directly with the GPIO control banks. Instead, GPIOs 0-27 generate IRQ GPIO0, 28-45 IRQ GPIO1 and 46-53 IRQ GPIO2. Awkwardly, the GPIOs for IRQ GPIO1 straddle two 32-entry GPIO banks, so split out a function to process the interrupts for a single GPIO bank. Cc: Stefan Wahren <stefan.wahren@i2se.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Phil Elwell <phil@raspberrypi.org> Acked-by: Eric Anholt <eric@anholt.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -47,6 +47,7 @@
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#define MODULE_NAME "pinctrl-bcm2835"
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#define BCM2835_NUM_GPIOS 54
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#define BCM2835_NUM_BANKS 2
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#define BCM2835_NUM_IRQS 3
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#define BCM2835_PIN_BITMAP_SZ \
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DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
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@ -88,13 +89,13 @@ enum bcm2835_pinconf_pull {
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struct bcm2835_gpio_irqdata {
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struct bcm2835_pinctrl *pc;
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int bank;
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int irqgroup;
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};
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struct bcm2835_pinctrl {
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struct device *dev;
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void __iomem *base;
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int irq[BCM2835_NUM_BANKS];
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int irq[BCM2835_NUM_IRQS];
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/* note: locking assumes each bank will have its own unsigned long */
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unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
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@ -105,7 +106,7 @@ struct bcm2835_pinctrl {
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struct gpio_chip gpio_chip;
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struct pinctrl_gpio_range gpio_range;
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struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_BANKS];
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struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_IRQS];
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spinlock_t irq_lock[BCM2835_NUM_BANKS];
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};
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@ -391,17 +392,16 @@ static struct gpio_chip bcm2835_gpio_chip = {
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.can_sleep = false,
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};
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static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id)
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static int bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
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unsigned int bank, u32 mask)
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{
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struct bcm2835_gpio_irqdata *irqdata = dev_id;
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struct bcm2835_pinctrl *pc = irqdata->pc;
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int bank = irqdata->bank;
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unsigned long events;
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unsigned offset;
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unsigned gpio;
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unsigned int type;
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events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
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events &= mask;
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events &= pc->enabled_irq_map[bank];
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for_each_set_bit(offset, &events, 32) {
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gpio = (32 * bank) + offset;
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@ -409,7 +409,30 @@ static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id)
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generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio));
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}
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return events ? IRQ_HANDLED : IRQ_NONE;
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return (events != 0);
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}
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static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id)
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{
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struct bcm2835_gpio_irqdata *irqdata = dev_id;
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struct bcm2835_pinctrl *pc = irqdata->pc;
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int handled = 0;
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switch (irqdata->irqgroup) {
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case 0: /* IRQ0 covers GPIOs 0-27 */
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handled = bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
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break;
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case 1: /* IRQ1 covers GPIOs 28-45 */
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handled = bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000) |
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bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
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break;
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case 2: /* IRQ2 covers GPIOs 46-53 */
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handled = bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
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break;
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}
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return handled ? IRQ_HANDLED : IRQ_NONE;
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}
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static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
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@ -1000,8 +1023,6 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
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for (i = 0; i < BCM2835_NUM_BANKS; i++) {
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unsigned long events;
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unsigned offset;
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int len;
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char *name;
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/* clear event detection flags */
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bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
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@ -1016,10 +1037,15 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
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for_each_set_bit(offset, &events, 32)
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bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
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spin_lock_init(&pc->irq_lock[i]);
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}
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for (i = 0; i < BCM2835_NUM_IRQS; i++) {
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int len;
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char *name;
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pc->irq[i] = irq_of_parse_and_map(np, i);
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pc->irq_data[i].pc = pc;
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pc->irq_data[i].bank = i;
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spin_lock_init(&pc->irq_lock[i]);
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pc->irq_data[i].irqgroup = i;
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len = strlen(dev_name(pc->dev)) + 16;
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name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
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