2019-06-04 16:11:33 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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2011-08-09 23:15:17 +08:00
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/*
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2020-07-08 17:34:51 +08:00
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* Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
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2011-08-09 23:15:17 +08:00
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*/
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2018-01-12 08:04:03 +08:00
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#include <dt-bindings/bus/ti-sysc.h>
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#include <dt-bindings/clock/omap4.h>
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2013-05-31 20:32:56 +08:00
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#include <dt-bindings/gpio/gpio.h>
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2013-05-31 20:32:57 +08:00
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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2013-05-31 20:32:59 +08:00
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#include <dt-bindings/pinctrl/omap.h>
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2017-12-08 23:17:27 +08:00
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#include <dt-bindings/clock/omap4.h>
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2011-08-09 23:15:17 +08:00
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/ {
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compatible = "ti,omap4430", "ti,omap4";
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2015-03-11 23:43:49 +08:00
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interrupt-parent = <&wakeupgen>;
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2016-08-31 18:35:19 +08:00
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#address-cells = <1>;
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#size-cells = <1>;
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2016-12-19 22:44:35 +08:00
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chosen { };
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2011-08-09 23:15:17 +08:00
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aliases {
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2013-10-17 04:21:03 +08:00
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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i2c3 = &i2c4;
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2021-03-08 17:30:45 +08:00
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mmc0 = &mmc1;
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mmc1 = &mmc2;
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mmc2 = &mmc3;
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mmc3 = &mmc4;
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mmc4 = &mmc5;
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2011-12-14 19:55:46 +08:00
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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2020-07-10 07:19:46 +08:00
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rproc0 = &dsp;
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rproc1 = &ipu;
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2011-08-09 23:15:17 +08:00
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};
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2011-08-16 17:49:08 +08:00
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cpus {
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2013-04-19 01:35:59 +08:00
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#address-cells = <1>;
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#size-cells = <0>;
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2011-08-16 17:49:08 +08:00
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cpu@0 {
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compatible = "arm,cortex-a9";
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2013-04-19 01:35:59 +08:00
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device_type = "cpu";
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2012-07-04 20:27:34 +08:00
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next-level-cache = <&L2>;
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2013-04-19 01:35:59 +08:00
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reg = <0x0>;
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2014-01-30 02:19:17 +08:00
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clocks = <&dpll_mpu_ck>;
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clock-names = "cpu";
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clock-latency = <300000>; /* From omap-cpufreq driver */
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2011-08-16 17:49:08 +08:00
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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2013-04-19 01:35:59 +08:00
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device_type = "cpu";
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2012-07-04 20:27:34 +08:00
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next-level-cache = <&L2>;
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2013-04-19 01:35:59 +08:00
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reg = <0x1>;
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2011-08-16 17:49:08 +08:00
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};
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};
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2017-08-30 23:19:38 +08:00
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/*
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* Note that 4430 needs cross trigger interface (CTI) supported
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* before we can configure the interrupts. This means sampling
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* events are not supported for pmu. Note that 4460 does not use
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* CTI, see also 4460.dtsi.
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*/
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pmu {
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compatible = "arm,cortex-a9-pmu";
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ti,hwmods = "debugss";
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};
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2012-09-03 23:56:32 +08:00
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gic: interrupt-controller@48241000 {
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compatible = "arm,cortex-a9-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x48241000 0x1000>,
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<0x48240100 0x0100>;
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2015-03-11 23:43:49 +08:00
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interrupt-parent = <&gic>;
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2012-09-03 23:56:32 +08:00
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};
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2020-06-26 16:06:19 +08:00
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L2: cache-controller@48242000 {
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2012-07-04 20:27:34 +08:00
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compatible = "arm,pl310-cache";
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reg = <0x48242000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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2013-07-22 18:52:36 +08:00
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local-timer@48240600 {
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2012-07-04 21:02:32 +08:00
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compatible = "arm,cortex-a9-twd-timer";
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2014-04-08 04:05:39 +08:00
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clocks = <&mpu_periphclk>;
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2012-07-04 21:02:32 +08:00
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reg = <0x48240600 0x20>;
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2016-03-17 22:19:06 +08:00
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
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2015-03-11 23:43:49 +08:00
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interrupt-parent = <&gic>;
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};
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wakeupgen: interrupt-controller@48281000 {
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compatible = "ti,omap4-wugen-mpu";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x48281000 0x1000>;
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interrupt-parent = <&gic>;
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2012-07-04 21:02:32 +08:00
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};
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2011-08-09 23:15:17 +08:00
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/*
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2014-03-28 18:11:37 +08:00
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* The soc node represents the soc top level view. It is used for IPs
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2011-08-09 23:15:17 +08:00
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* that are not memory mapped in the MPU view or for the MPU itself.
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*/
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soc {
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compatible = "ti,omap-infra";
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2011-08-16 17:49:08 +08:00
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mpu {
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compatible = "ti,omap4-mpu";
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ti,hwmods = "mpu";
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2014-09-11 00:04:04 +08:00
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sram = <&ocmcram>;
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2011-08-16 17:49:08 +08:00
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};
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2011-08-09 23:15:17 +08:00
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};
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/*
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* XXX: Use a flat representation of the OMAP4 interconnect.
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* The real OMAP interconnect network is quite complex.
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2014-03-28 18:11:39 +08:00
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* Since it will not bring real advantage to represent that in DT for
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2011-08-09 23:15:17 +08:00
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* the moment, just use a fake OCP bus entry to represent the whole bus
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* hierarchy.
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*/
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ocp {
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2011-08-12 19:48:47 +08:00
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compatible = "ti,omap4-l3-noc", "simple-bus";
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2011-08-09 23:15:17 +08:00
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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2011-08-12 19:48:47 +08:00
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ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
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2013-02-26 20:06:14 +08:00
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reg = <0x44000000 0x1000>,
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<0x44800000 0x2000>,
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<0x45000000 0x1000>;
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2013-05-31 20:32:57 +08:00
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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2011-08-09 23:15:17 +08:00
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2018-07-06 14:19:37 +08:00
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l4_wkup: interconnect@4a300000 {
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};
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2017-08-30 23:19:39 +08:00
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2018-07-06 14:19:37 +08:00
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l4_cfg: interconnect@4a000000 {
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};
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2017-08-30 23:19:39 +08:00
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2018-07-06 14:19:37 +08:00
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l4_per: interconnect@48000000 {
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2014-02-19 22:56:40 +08:00
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};
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2019-04-10 00:00:53 +08:00
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l4_abe: interconnect@40100000 {
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};
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2019-10-03 00:43:16 +08:00
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ocmcram: sram@40304000 {
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2014-09-11 00:04:03 +08:00
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compatible = "mmio-sram";
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reg = <0x40304000 0xa000>; /* 40k */
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};
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2020-11-19 20:19:01 +08:00
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target-module@50000000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x50000000 4>,
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<0x50000010 4>,
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<0x50000014 4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,syss-mask = <1>;
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2013-10-15 15:07:50 +08:00
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ti,no-idle-on-init;
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2020-11-19 20:19:01 +08:00
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clocks = <&l3_2_clkctrl OMAP4_GPMC_CLKCTRL 0>;
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2014-02-26 18:38:09 +08:00
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clock-names = "fck";
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2020-11-19 20:19:01 +08:00
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
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<0x00000000 0x00000000 0x40000000>; /* data */
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gpmc: gpmc@50000000 {
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compatible = "ti,omap4430-gpmc";
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reg = <0x50000000 0x1000>;
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#address-cells = <2>;
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#size-cells = <1>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&sdma 4>;
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dma-names = "rxtx";
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gpmc,num-cs = <8>;
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gpmc,num-waitpins = <4>;
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clocks = <&l3_div_ck>;
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clock-names = "fck";
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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2013-02-23 05:33:31 +08:00
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};
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2017-10-11 05:14:50 +08:00
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target-module@52000000 {
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2017-12-14 08:36:47 +08:00
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compatible = "ti,sysc-omap4", "ti,sysc";
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2017-10-11 05:14:50 +08:00
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ti,hwmods = "iss";
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reg = <0x52000000 0x4>,
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<0x52000010 0x4>;
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reg-names = "rev", "sysc";
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2018-01-12 08:04:03 +08:00
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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ti,sysc-delay-us = <2>;
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2021-03-10 20:04:29 +08:00
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power-domains = <&prm_cam>;
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2018-01-12 08:04:03 +08:00
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clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
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clock-names = "fck";
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2017-10-11 05:14:50 +08:00
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x52000000 0x1000000>;
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/* No child device binding, driver in staging */
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};
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2019-12-12 20:51:20 +08:00
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target-module@55082000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x55082000 0x4>,
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<0x55082010 0x4>,
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<0x55082014 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
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SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
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clock-names = "fck";
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resets = <&prm_core 2>;
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reset-names = "rstctrl";
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ranges = <0x0 0x55082000 0x100>;
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#size-cells = <1>;
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#address-cells = <1>;
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mmu_ipu: mmu@0 {
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compatible = "ti,omap4-iommu";
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reg = <0x0 0x100>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <0>;
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ti,iommu-bus-err-back;
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};
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2014-03-06 08:24:18 +08:00
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};
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2019-12-12 20:51:20 +08:00
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2017-10-11 05:14:50 +08:00
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target-module@4012c000 {
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2017-12-14 08:36:47 +08:00
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compatible = "ti,sysc-omap4", "ti,sysc";
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2017-10-11 05:14:50 +08:00
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reg = <0x4012c000 0x4>,
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<0x4012c010 0x4>;
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reg-names = "rev", "sysc";
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2018-01-12 08:04:03 +08:00
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ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
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clock-names = "fck";
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2017-10-11 05:14:50 +08:00
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
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<0x4902c000 0x4902c000 0x1000>; /* L3 */
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/* No child device binding or driver in mainline */
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};
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2021-03-10 20:04:29 +08:00
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target-module@4e000000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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2013-12-17 18:02:21 +08:00
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ti,hwmods = "dmm";
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2021-03-10 20:04:29 +08:00
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reg = <0x4e000000 0x4>,
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<0x4e000010 0x4>;
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reg-names = "rev", "sysc";
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|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
|
|
|
<SYSC_IDLE_NO>,
|
|
|
|
|
<SYSC_IDLE_SMART>;
|
|
|
|
|
ranges = <0x0 0x4e000000 0x2000000>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
|
|
|
|
|
dmm@0 {
|
|
|
|
|
compatible = "ti,omap4-dmm";
|
|
|
|
|
reg = <0 0x800>;
|
|
|
|
|
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
};
|
2013-12-17 18:02:21 +08:00
|
|
|
};
|
|
|
|
|
|
2012-01-20 23:05:26 +08:00
|
|
|
emif1: emif@4c000000 {
|
|
|
|
|
compatible = "ti,emif-4d";
|
2012-09-05 17:38:23 +08:00
|
|
|
reg = <0x4c000000 0x100>;
|
2013-05-31 20:32:57 +08:00
|
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
2012-01-20 23:05:26 +08:00
|
|
|
ti,hwmods = "emif1";
|
2013-10-15 15:07:50 +08:00
|
|
|
ti,no-idle-on-init;
|
2012-01-20 23:05:26 +08:00
|
|
|
phy-type = <1>;
|
|
|
|
|
hw-caps-read-idle-ctrl;
|
|
|
|
|
hw-caps-ll-interface;
|
|
|
|
|
hw-caps-temp-alert;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
emif2: emif@4d000000 {
|
|
|
|
|
compatible = "ti,emif-4d";
|
2012-09-05 17:38:23 +08:00
|
|
|
reg = <0x4d000000 0x100>;
|
2013-05-31 20:32:57 +08:00
|
|
|
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
2012-01-20 23:05:26 +08:00
|
|
|
ti,hwmods = "emif2";
|
2013-10-15 15:07:50 +08:00
|
|
|
ti,no-idle-on-init;
|
2012-01-20 23:05:26 +08:00
|
|
|
phy-type = <1>;
|
|
|
|
|
hw-caps-read-idle-ctrl;
|
|
|
|
|
hw-caps-ll-interface;
|
|
|
|
|
hw-caps-temp-alert;
|
|
|
|
|
};
|
2012-10-02 09:46:13 +08:00
|
|
|
|
2020-07-10 07:19:44 +08:00
|
|
|
dsp: dsp {
|
|
|
|
|
compatible = "ti,omap4-dsp";
|
|
|
|
|
ti,bootreg = <&scm_conf 0x304 0>;
|
|
|
|
|
iommus = <&mmu_dsp>;
|
|
|
|
|
resets = <&prm_tesla 0>;
|
|
|
|
|
clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
|
|
|
|
|
firmware-name = "omap4-dsp-fw.xe64T";
|
|
|
|
|
mboxes = <&mailbox &mbox_dsp>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2020-07-10 07:19:45 +08:00
|
|
|
ipu: ipu@55020000 {
|
|
|
|
|
compatible = "ti,omap4-ipu";
|
|
|
|
|
reg = <0x55020000 0x10000>;
|
|
|
|
|
reg-names = "l2ram";
|
|
|
|
|
iommus = <&mmu_ipu>;
|
|
|
|
|
resets = <&prm_core 0>, <&prm_core 1>;
|
|
|
|
|
clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
|
|
|
|
|
firmware-name = "omap4-ipu-fw.xem3";
|
|
|
|
|
mboxes = <&mailbox &mbox_ipu>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2019-12-13 01:46:12 +08:00
|
|
|
aes1_target: target-module@4b501000 {
|
|
|
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
|
|
|
reg = <0x4b501080 0x4>,
|
|
|
|
|
<0x4b501084 0x4>,
|
|
|
|
|
<0x4b501088 0x4>;
|
|
|
|
|
reg-names = "rev", "sysc", "syss";
|
|
|
|
|
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
|
|
|
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
|
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
|
|
|
<SYSC_IDLE_NO>,
|
|
|
|
|
<SYSC_IDLE_SMART>,
|
|
|
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
|
|
|
ti,syss-mask = <1>;
|
|
|
|
|
/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
|
|
|
|
|
clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0x0 0x4b501000 0x1000>;
|
|
|
|
|
|
|
|
|
|
aes1: aes@0 {
|
|
|
|
|
compatible = "ti,omap4-aes";
|
|
|
|
|
reg = <0 0xa0>;
|
|
|
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dmas = <&sdma 111>, <&sdma 110>;
|
|
|
|
|
dma-names = "tx", "rx";
|
|
|
|
|
};
|
2017-06-13 21:45:48 +08:00
|
|
|
};
|
|
|
|
|
|
2019-12-13 01:46:12 +08:00
|
|
|
aes2_target: target-module@4b701000 {
|
|
|
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
|
|
|
reg = <0x4b701080 0x4>,
|
|
|
|
|
<0x4b701084 0x4>,
|
|
|
|
|
<0x4b701088 0x4>;
|
|
|
|
|
reg-names = "rev", "sysc", "syss";
|
|
|
|
|
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
|
|
|
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
|
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
|
|
|
<SYSC_IDLE_NO>,
|
|
|
|
|
<SYSC_IDLE_SMART>,
|
|
|
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
|
|
|
ti,syss-mask = <1>;
|
|
|
|
|
/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
|
|
|
|
|
clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0x0 0x4b701000 0x1000>;
|
|
|
|
|
|
|
|
|
|
aes2: aes@0 {
|
|
|
|
|
compatible = "ti,omap4-aes";
|
|
|
|
|
reg = <0 0xa0>;
|
|
|
|
|
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dmas = <&sdma 114>, <&sdma 113>;
|
|
|
|
|
dma-names = "tx", "rx";
|
|
|
|
|
};
|
2013-09-25 04:23:33 +08:00
|
|
|
};
|
2014-03-03 22:50:22 +08:00
|
|
|
|
2019-12-13 01:46:12 +08:00
|
|
|
sham_target: target-module@4b100000 {
|
|
|
|
|
compatible = "ti,sysc-omap3-sham", "ti,sysc";
|
|
|
|
|
reg = <0x4b100100 0x4>,
|
|
|
|
|
<0x4b100110 0x4>,
|
|
|
|
|
<0x4b100114 0x4>;
|
|
|
|
|
reg-names = "rev", "sysc", "syss";
|
|
|
|
|
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
|
|
|
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
|
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
|
|
|
<SYSC_IDLE_NO>,
|
|
|
|
|
<SYSC_IDLE_SMART>;
|
|
|
|
|
ti,syss-mask = <1>;
|
|
|
|
|
/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
|
|
|
|
|
clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0x0 0x4b100000 0x1000>;
|
|
|
|
|
|
|
|
|
|
sham: sham@0 {
|
|
|
|
|
compatible = "ti,omap4-sham";
|
|
|
|
|
reg = <0 0x300>;
|
|
|
|
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dmas = <&sdma 119>;
|
|
|
|
|
dma-names = "rx";
|
|
|
|
|
};
|
2017-06-13 21:45:49 +08:00
|
|
|
};
|
|
|
|
|
|
2014-03-03 22:50:22 +08:00
|
|
|
abb_mpu: regulator-abb-mpu {
|
|
|
|
|
compatible = "ti,abb-v2";
|
|
|
|
|
regulator-name = "abb_mpu";
|
|
|
|
|
#address-cells = <0>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,tranxdone-status-mask = <0x80>;
|
|
|
|
|
clocks = <&sys_clkin_ck>;
|
|
|
|
|
ti,settling-time = <50>;
|
|
|
|
|
ti,clock-cycles = <16>;
|
|
|
|
|
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
abb_iva: regulator-abb-iva {
|
|
|
|
|
compatible = "ti,abb-v2";
|
|
|
|
|
regulator-name = "abb_iva";
|
|
|
|
|
#address-cells = <0>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,tranxdone-status-mask = <0x80000000>;
|
|
|
|
|
clocks = <&sys_clkin_ck>;
|
|
|
|
|
ti,settling-time = <50>;
|
|
|
|
|
ti,clock-cycles = <16>;
|
|
|
|
|
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
2012-08-21 20:34:50 +08:00
|
|
|
|
2020-03-11 05:02:48 +08:00
|
|
|
sgx_module: target-module@56000000 {
|
2017-12-14 08:36:47 +08:00
|
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
2019-11-25 01:43:16 +08:00
|
|
|
reg = <0x5600fe00 0x4>,
|
|
|
|
|
<0x5600fe10 0x4>;
|
2017-10-11 05:14:50 +08:00
|
|
|
reg-names = "rev", "sysc";
|
2018-01-12 08:04:03 +08:00
|
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
|
|
|
<SYSC_IDLE_NO>,
|
|
|
|
|
<SYSC_IDLE_SMART>,
|
|
|
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
|
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
|
|
|
<SYSC_IDLE_NO>,
|
|
|
|
|
<SYSC_IDLE_SMART>,
|
|
|
|
|
<SYSC_IDLE_SMART_WKUP>;
|
2021-03-10 20:04:28 +08:00
|
|
|
power-domains = <&prm_gfx>;
|
2018-01-12 08:04:03 +08:00
|
|
|
clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
|
|
|
|
|
clock-names = "fck";
|
2017-10-11 05:14:50 +08:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0 0x56000000 0x2000000>;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Closed source PowerVR driver, no child device
|
|
|
|
|
* binding or driver in mainline
|
|
|
|
|
*/
|
|
|
|
|
};
|
|
|
|
|
|
2020-03-05 00:10:37 +08:00
|
|
|
/*
|
|
|
|
|
* DSS is only using l3 mapping without l4 as noted in the TRM
|
|
|
|
|
* "10.1.3 DSS Register Manual" for omap4460.
|
|
|
|
|
*/
|
|
|
|
|
target-module@58000000 {
|
|
|
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
|
|
|
reg = <0x58000000 4>,
|
|
|
|
|
<0x58000014 4>;
|
|
|
|
|
reg-names = "rev", "syss";
|
|
|
|
|
ti,syss-mask = <1>;
|
2020-11-19 20:18:08 +08:00
|
|
|
power-domains = <&prm_dss>;
|
2020-03-05 00:10:37 +08:00
|
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
|
|
|
|
|
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
|
|
|
|
|
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>,
|
|
|
|
|
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
|
|
|
|
|
clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
|
2012-08-21 20:34:50 +08:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
2020-03-05 00:10:37 +08:00
|
|
|
ranges = <0 0x58000000 0x1000000>;
|
2012-08-21 20:34:50 +08:00
|
|
|
|
2020-03-05 00:10:37 +08:00
|
|
|
dss: dss@0 {
|
|
|
|
|
compatible = "ti,omap4-dss";
|
|
|
|
|
reg = <0 0x80>;
|
2012-08-21 20:34:50 +08:00
|
|
|
status = "disabled";
|
2020-03-05 00:10:37 +08:00
|
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
|
2012-08-21 20:34:50 +08:00
|
|
|
clock-names = "fck";
|
2020-03-05 00:10:37 +08:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0 0 0x1000000>;
|
|
|
|
|
|
2020-03-05 00:10:37 +08:00
|
|
|
target-module@1000 {
|
|
|
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
|
|
|
reg = <0x1000 0x4>,
|
|
|
|
|
<0x1010 0x4>,
|
|
|
|
|
<0x1014 0x4>;
|
|
|
|
|
reg-names = "rev", "sysc", "syss";
|
|
|
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
|
|
|
<SYSC_IDLE_NO>,
|
|
|
|
|
<SYSC_IDLE_SMART>;
|
|
|
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
|
|
|
<SYSC_IDLE_NO>,
|
|
|
|
|
<SYSC_IDLE_SMART>;
|
|
|
|
|
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
|
|
|
|
SYSC_OMAP2_ENAWAKEUP |
|
|
|
|
|
SYSC_OMAP2_SOFTRESET |
|
|
|
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
|
|
|
ti,syss-mask = <1>;
|
|
|
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
|
|
|
|
|
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
|
|
|
|
|
clock-names = "fck", "sys_clk";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0 0x1000 0x1000>;
|
|
|
|
|
|
|
|
|
|
dispc@0 {
|
|
|
|
|
compatible = "ti,omap4-dispc";
|
|
|
|
|
reg = <0 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
};
|
2020-03-05 00:10:37 +08:00
|
|
|
};
|
|
|
|
|
|
2020-03-05 00:10:37 +08:00
|
|
|
target-module@2000 {
|
|
|
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
|
|
|
reg = <0x2000 0x4>,
|
|
|
|
|
<0x2010 0x4>,
|
|
|
|
|
<0x2014 0x4>;
|
|
|
|
|
reg-names = "rev", "sysc", "syss";
|
|
|
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
|
|
|
<SYSC_IDLE_NO>,
|
|
|
|
|
<SYSC_IDLE_SMART>;
|
|
|
|
|
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
|
|
|
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
|
|
|
ti,syss-mask = <1>;
|
|
|
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
|
|
|
|
|
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
|
|
|
|
|
clock-names = "fck", "sys_clk";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0 0x2000 0x1000>;
|
|
|
|
|
|
|
|
|
|
rfbi: encoder@0 {
|
|
|
|
|
reg = <0 0x1000>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
|
|
|
|
|
clock-names = "fck", "ick";
|
|
|
|
|
};
|
2020-03-05 00:10:37 +08:00
|
|
|
};
|
|
|
|
|
|
2020-03-05 00:10:38 +08:00
|
|
|
target-module@3000 {
|
|
|
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
|
|
|
reg = <0x3000 0x4>;
|
|
|
|
|
reg-names = "rev";
|
|
|
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
|
|
|
|
|
clock-names = "sys_clk";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0 0x3000 0x1000>;
|
|
|
|
|
|
|
|
|
|
venc: encoder@0 {
|
|
|
|
|
compatible = "ti,omap4-venc";
|
|
|
|
|
reg = <0 0x1000>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
};
|
2020-03-05 00:10:37 +08:00
|
|
|
};
|
|
|
|
|
|
2020-03-05 00:10:38 +08:00
|
|
|
target-module@4000 {
|
|
|
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
|
|
|
reg = <0x4000 0x4>,
|
|
|
|
|
<0x4010 0x4>,
|
|
|
|
|
<0x4014 0x4>;
|
|
|
|
|
reg-names = "rev", "sysc", "syss";
|
|
|
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
|
|
|
<SYSC_IDLE_NO>,
|
|
|
|
|
<SYSC_IDLE_SMART>;
|
|
|
|
|
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
|
|
|
|
SYSC_OMAP2_ENAWAKEUP |
|
|
|
|
|
SYSC_OMAP2_SOFTRESET |
|
|
|
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
|
|
|
ti,syss-mask = <1>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0 0x4000 0x1000>;
|
|
|
|
|
|
|
|
|
|
dsi1: encoder@0 {
|
|
|
|
|
compatible = "ti,omap4-dsi";
|
|
|
|
|
reg = <0 0x200>,
|
|
|
|
|
<0x200 0x40>,
|
|
|
|
|
<0x300 0x20>;
|
|
|
|
|
reg-names = "proto", "phy", "pll";
|
|
|
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
|
|
|
|
|
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
|
|
|
|
|
clock-names = "fck", "sys_clk";
|
2020-07-16 20:57:31 +08:00
|
|
|
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2020-03-05 00:10:38 +08:00
|
|
|
};
|
2020-03-05 00:10:37 +08:00
|
|
|
};
|
|
|
|
|
|
2020-03-05 00:10:39 +08:00
|
|
|
target-module@5000 {
|
|
|
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
|
|
|
reg = <0x5000 0x4>,
|
|
|
|
|
<0x5010 0x4>,
|
|
|
|
|
<0x5014 0x4>;
|
|
|
|
|
reg-names = "rev", "sysc", "syss";
|
|
|
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
|
|
|
<SYSC_IDLE_NO>,
|
|
|
|
|
<SYSC_IDLE_SMART>;
|
|
|
|
|
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
|
|
|
|
SYSC_OMAP2_ENAWAKEUP |
|
|
|
|
|
SYSC_OMAP2_SOFTRESET |
|
|
|
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
|
|
|
ti,syss-mask = <1>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0 0x5000 0x1000>;
|
|
|
|
|
|
|
|
|
|
dsi2: encoder@0 {
|
|
|
|
|
compatible = "ti,omap4-dsi";
|
|
|
|
|
reg = <0 0x200>,
|
|
|
|
|
<0x200 0x40>,
|
|
|
|
|
<0x300 0x20>;
|
|
|
|
|
reg-names = "proto", "phy", "pll";
|
|
|
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
|
|
|
|
|
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
|
|
|
|
|
clock-names = "fck", "sys_clk";
|
2020-07-16 20:57:31 +08:00
|
|
|
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2020-03-05 00:10:39 +08:00
|
|
|
};
|
2020-03-05 00:10:37 +08:00
|
|
|
};
|
|
|
|
|
|
2020-03-05 00:10:39 +08:00
|
|
|
target-module@6000 {
|
|
|
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
|
|
|
reg = <0x6000 0x4>,
|
|
|
|
|
<0x6010 0x4>;
|
|
|
|
|
reg-names = "rev", "sysc";
|
|
|
|
|
/*
|
|
|
|
|
* Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP
|
|
|
|
|
* but HDMI audio will fail with them.
|
|
|
|
|
*/
|
|
|
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
|
|
|
<SYSC_IDLE_NO>;
|
|
|
|
|
ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
|
2020-03-05 00:10:37 +08:00
|
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
|
2020-03-05 00:10:39 +08:00
|
|
|
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
|
|
|
|
|
clock-names = "fck", "dss_clk";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0 0x6000 0x2000>;
|
|
|
|
|
|
|
|
|
|
hdmi: encoder@0 {
|
|
|
|
|
compatible = "ti,omap4-hdmi";
|
|
|
|
|
reg = <0 0x200>,
|
|
|
|
|
<0x200 0x100>,
|
|
|
|
|
<0x300 0x100>,
|
|
|
|
|
<0x400 0x1000>;
|
|
|
|
|
reg-names = "wp", "pll", "phy", "core";
|
|
|
|
|
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
|
|
|
|
|
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
|
|
|
|
|
clock-names = "fck", "sys_clk";
|
|
|
|
|
dmas = <&sdma 76>;
|
|
|
|
|
dma-names = "audio_tx";
|
|
|
|
|
};
|
2020-03-05 00:10:37 +08:00
|
|
|
};
|
2012-08-21 20:34:50 +08:00
|
|
|
};
|
|
|
|
|
};
|
2020-11-19 20:18:54 +08:00
|
|
|
|
|
|
|
|
iva_hd_target: target-module@5a000000 {
|
|
|
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
|
|
|
reg = <0x5a05a400 0x4>,
|
|
|
|
|
<0x5a05a410 0x4>;
|
|
|
|
|
reg-names = "rev", "sysc";
|
|
|
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
|
|
|
<SYSC_IDLE_NO>,
|
|
|
|
|
<SYSC_IDLE_SMART>;
|
|
|
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
|
|
|
<SYSC_IDLE_NO>,
|
|
|
|
|
<SYSC_IDLE_SMART>;
|
|
|
|
|
power-domains = <&prm_ivahd>;
|
|
|
|
|
resets = <&prm_ivahd 2>;
|
|
|
|
|
reset-names = "rstctrl";
|
|
|
|
|
clocks = <&ivahd_clkctrl OMAP4_IVA_CLKCTRL 0>;
|
|
|
|
|
clock-names = "fck";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0x5a000000 0x5a000000 0x1000000>,
|
|
|
|
|
<0x5b000000 0x5b000000 0x1000000>;
|
|
|
|
|
|
|
|
|
|
iva {
|
|
|
|
|
compatible = "ti,ivahd";
|
|
|
|
|
};
|
|
|
|
|
};
|
2011-08-09 23:15:17 +08:00
|
|
|
};
|
|
|
|
|
};
|
2013-07-18 17:42:02 +08:00
|
|
|
|
2018-07-06 14:19:37 +08:00
|
|
|
#include "omap4-l4.dtsi"
|
2019-04-10 00:00:53 +08:00
|
|
|
#include "omap4-l4-abe.dtsi"
|
2017-12-08 23:17:27 +08:00
|
|
|
#include "omap44xx-clocks.dtsi"
|
2019-10-10 16:21:05 +08:00
|
|
|
|
|
|
|
|
&prm {
|
2020-11-12 20:21:52 +08:00
|
|
|
prm_mpu: prm@300 {
|
|
|
|
|
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
|
|
|
|
reg = <0x300 0x100>;
|
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
2019-10-10 16:21:05 +08:00
|
|
|
prm_tesla: prm@400 {
|
|
|
|
|
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
|
|
|
|
reg = <0x400 0x100>;
|
|
|
|
|
#reset-cells = <1>;
|
2020-11-12 20:21:52 +08:00
|
|
|
#power-domain-cells = <0>;
|
2019-10-10 16:21:05 +08:00
|
|
|
};
|
|
|
|
|
|
2020-07-02 23:45:13 +08:00
|
|
|
prm_abe: prm@500 {
|
|
|
|
|
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
|
|
|
|
reg = <0x500 0x100>;
|
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
2020-11-12 20:21:52 +08:00
|
|
|
prm_always_on_core: prm@600 {
|
|
|
|
|
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
|
|
|
|
reg = <0x600 0x100>;
|
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
2019-10-10 16:21:05 +08:00
|
|
|
prm_core: prm@700 {
|
|
|
|
|
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
|
|
|
|
reg = <0x700 0x100>;
|
|
|
|
|
#reset-cells = <1>;
|
2020-11-12 20:21:52 +08:00
|
|
|
#power-domain-cells = <0>;
|
2019-10-10 16:21:05 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
prm_ivahd: prm@f00 {
|
|
|
|
|
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
|
|
|
|
reg = <0xf00 0x100>;
|
|
|
|
|
#reset-cells = <1>;
|
2020-11-12 20:21:52 +08:00
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
prm_cam: prm@1000 {
|
|
|
|
|
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
|
|
|
|
reg = <0x1000 0x100>;
|
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
prm_dss: prm@1100 {
|
|
|
|
|
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
|
|
|
|
reg = <0x1100 0x100>;
|
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
prm_gfx: prm@1200 {
|
|
|
|
|
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
|
|
|
|
reg = <0x1200 0x100>;
|
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
prm_l3init: prm@1300 {
|
|
|
|
|
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
|
|
|
|
reg = <0x1300 0x100>;
|
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
prm_l4per: prm@1400 {
|
|
|
|
|
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
|
|
|
|
reg = <0x1400 0x100>;
|
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
prm_cefuse: prm@1600 {
|
|
|
|
|
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
|
|
|
|
reg = <0x1600 0x100>;
|
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
prm_wkup: prm@1700 {
|
|
|
|
|
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
|
|
|
|
reg = <0x1700 0x100>;
|
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
prm_emu: prm@1900 {
|
|
|
|
|
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
|
|
|
|
reg = <0x1900 0x100>;
|
|
|
|
|
#power-domain-cells = <0>;
|
2019-10-10 16:21:05 +08:00
|
|
|
};
|
|
|
|
|
|
2020-11-19 20:18:08 +08:00
|
|
|
prm_dss: prm@1100 {
|
|
|
|
|
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
|
|
|
|
reg = <0x1100 0x40>;
|
|
|
|
|
#power-domain-cells = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
2019-10-10 16:21:05 +08:00
|
|
|
prm_device: prm@1b00 {
|
|
|
|
|
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
|
|
|
|
|
reg = <0x1b00 0x40>;
|
|
|
|
|
#reset-cells = <1>;
|
|
|
|
|
};
|
|
|
|
|
};
|
2020-05-08 00:59:31 +08:00
|
|
|
|
|
|
|
|
/* Preferred always-on timer for clockevent */
|
|
|
|
|
&timer1_target {
|
|
|
|
|
ti,no-reset-on-init;
|
|
|
|
|
ti,no-idle;
|
|
|
|
|
timer@0 {
|
|
|
|
|
assigned-clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>;
|
2020-06-13 01:23:40 +08:00
|
|
|
assigned-clock-parents = <&sys_32k_ck>;
|
2020-05-08 00:59:31 +08:00
|
|
|
};
|
|
|
|
|
};
|
