2019-06-04 16:10:53 +08:00
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// SPDX-License-Identifier: GPL-2.0-only
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2015-09-30 20:55:47 +08:00
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/*
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* i.MX6 OCOTP fusebox driver
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*
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* Copyright (c) 2015 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
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*
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2020-11-27 18:28:37 +08:00
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* Copyright 2019 NXP
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*
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2015-09-30 20:55:47 +08:00
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* Based on the barebox ocotp driver,
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* Copyright (c) 2010 Baruch Siach <baruch@tkos.co.il>,
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* Orex Computed Radiography
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*
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2017-03-31 20:44:55 +08:00
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* Write support based on the fsl_otp driver,
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* Copyright (C) 2010-2013 Freescale Semiconductor, Inc
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2015-09-30 20:55:47 +08:00
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*/
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2016-06-02 19:05:11 +08:00
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#include <linux/clk.h>
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2015-09-30 20:55:47 +08:00
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/nvmem-provider.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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2017-03-31 20:44:55 +08:00
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#include <linux/delay.h>
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2015-09-30 20:55:47 +08:00
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2017-03-31 20:44:54 +08:00
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#define IMX_OCOTP_OFFSET_B0W0 0x400 /* Offset from base address of the
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* OTP Bank0 Word0
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*/
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#define IMX_OCOTP_OFFSET_PER_WORD 0x10 /* Offset between the start addr
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* of two consecutive OTP words.
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*/
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2017-03-31 20:44:55 +08:00
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2017-03-31 20:44:54 +08:00
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#define IMX_OCOTP_ADDR_CTRL 0x0000
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2017-03-31 20:44:55 +08:00
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#define IMX_OCOTP_ADDR_CTRL_SET 0x0004
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2017-03-31 20:44:54 +08:00
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#define IMX_OCOTP_ADDR_CTRL_CLR 0x0008
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2017-03-31 20:44:55 +08:00
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#define IMX_OCOTP_ADDR_TIMING 0x0010
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2017-10-24 17:54:29 +08:00
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#define IMX_OCOTP_ADDR_DATA0 0x0020
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#define IMX_OCOTP_ADDR_DATA1 0x0030
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#define IMX_OCOTP_ADDR_DATA2 0x0040
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#define IMX_OCOTP_ADDR_DATA3 0x0050
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2017-03-31 20:44:54 +08:00
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2019-06-26 18:27:28 +08:00
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#define IMX_OCOTP_BM_CTRL_ADDR 0x000000FF
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2017-03-31 20:44:55 +08:00
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#define IMX_OCOTP_BM_CTRL_BUSY 0x00000100
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2017-03-31 20:44:54 +08:00
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#define IMX_OCOTP_BM_CTRL_ERROR 0x00000200
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2017-03-31 20:44:55 +08:00
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#define IMX_OCOTP_BM_CTRL_REL_SHADOWS 0x00000400
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2017-03-31 20:44:54 +08:00
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2020-03-10 21:22:44 +08:00
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#define IMX_OCOTP_BM_CTRL_ADDR_8MP 0x000001FF
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#define IMX_OCOTP_BM_CTRL_BUSY_8MP 0x00000200
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#define IMX_OCOTP_BM_CTRL_ERROR_8MP 0x00000400
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#define IMX_OCOTP_BM_CTRL_REL_SHADOWS_8MP 0x00000800
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2020-01-09 18:40:16 +08:00
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#define IMX_OCOTP_BM_CTRL_DEFAULT \
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{ \
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.bm_addr = IMX_OCOTP_BM_CTRL_ADDR, \
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.bm_busy = IMX_OCOTP_BM_CTRL_BUSY, \
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.bm_error = IMX_OCOTP_BM_CTRL_ERROR, \
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.bm_rel_shadows = IMX_OCOTP_BM_CTRL_REL_SHADOWS,\
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}
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2020-03-10 21:22:44 +08:00
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#define IMX_OCOTP_BM_CTRL_8MP \
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{ \
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.bm_addr = IMX_OCOTP_BM_CTRL_ADDR_8MP, \
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.bm_busy = IMX_OCOTP_BM_CTRL_BUSY_8MP, \
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.bm_error = IMX_OCOTP_BM_CTRL_ERROR_8MP, \
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.bm_rel_shadows = IMX_OCOTP_BM_CTRL_REL_SHADOWS_8MP,\
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}
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2019-06-26 18:27:30 +08:00
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#define TIMING_STROBE_PROG_US 10 /* Min time to blow a fuse */
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#define TIMING_STROBE_READ_NS 37 /* Min time before read */
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#define TIMING_RELAX_NS 17
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2017-10-24 17:54:31 +08:00
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#define DEF_FSOURCE 1001 /* > 1000 ns */
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#define DEF_STROBE_PROG 10000 /* IPG clocks */
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2017-03-31 20:44:55 +08:00
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#define IMX_OCOTP_WR_UNLOCK 0x3E770000
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2017-03-31 20:44:54 +08:00
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#define IMX_OCOTP_READ_LOCKED_VAL 0xBADABADA
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2017-03-31 20:44:55 +08:00
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static DEFINE_MUTEX(ocotp_mutex);
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2015-09-30 20:55:47 +08:00
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struct ocotp_priv {
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struct device *dev;
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2016-06-02 19:05:11 +08:00
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struct clk *clk;
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2015-09-30 20:55:47 +08:00
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void __iomem *base;
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2017-10-24 17:54:28 +08:00
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const struct ocotp_params *params;
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2017-03-31 20:44:55 +08:00
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struct nvmem_config *config;
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2015-09-30 20:55:47 +08:00
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};
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2020-01-09 18:40:16 +08:00
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struct ocotp_ctrl_reg {
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u32 bm_addr;
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u32 bm_busy;
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u32 bm_error;
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u32 bm_rel_shadows;
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};
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2017-10-24 17:54:31 +08:00
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struct ocotp_params {
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unsigned int nregs;
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unsigned int bank_address_words;
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void (*set_timing)(struct ocotp_priv *priv);
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2020-01-09 18:40:16 +08:00
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struct ocotp_ctrl_reg ctrl;
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2017-10-24 17:54:31 +08:00
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};
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2020-01-09 18:40:16 +08:00
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static int imx_ocotp_wait_for_busy(struct ocotp_priv *priv, u32 flags)
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2017-03-31 20:44:55 +08:00
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{
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int count;
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u32 c, mask;
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2020-01-09 18:40:16 +08:00
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u32 bm_ctrl_busy, bm_ctrl_error;
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void __iomem *base = priv->base;
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2017-03-31 20:44:55 +08:00
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2020-01-09 18:40:16 +08:00
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bm_ctrl_busy = priv->params->ctrl.bm_busy;
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bm_ctrl_error = priv->params->ctrl.bm_error;
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mask = bm_ctrl_busy | bm_ctrl_error | flags;
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2017-03-31 20:44:55 +08:00
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for (count = 10000; count >= 0; count--) {
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c = readl(base + IMX_OCOTP_ADDR_CTRL);
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if (!(c & mask))
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break;
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cpu_relax();
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}
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if (count < 0) {
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/* HW_OCOTP_CTRL[ERROR] will be set under the following
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* conditions:
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* - A write is performed to a shadow register during a shadow
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* reload (essentially, while HW_OCOTP_CTRL[RELOAD_SHADOWS] is
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* set. In addition, the contents of the shadow register shall
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* not be updated.
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* - A write is performed to a shadow register which has been
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* locked.
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* - A read is performed to from a shadow register which has
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* been read locked.
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* - A program is performed to a fuse word which has been locked
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* - A read is performed to from a fuse word which has been read
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* locked.
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*/
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2020-01-09 18:40:16 +08:00
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if (c & bm_ctrl_error)
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2017-03-31 20:44:55 +08:00
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return -EPERM;
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return -ETIMEDOUT;
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}
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return 0;
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}
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2020-01-09 18:40:16 +08:00
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static void imx_ocotp_clr_err_if_set(struct ocotp_priv *priv)
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2017-03-31 20:44:54 +08:00
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{
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2020-01-09 18:40:16 +08:00
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u32 c, bm_ctrl_error;
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void __iomem *base = priv->base;
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bm_ctrl_error = priv->params->ctrl.bm_error;
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2017-03-31 20:44:54 +08:00
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c = readl(base + IMX_OCOTP_ADDR_CTRL);
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2020-01-09 18:40:16 +08:00
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if (!(c & bm_ctrl_error))
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2017-03-31 20:44:54 +08:00
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return;
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2020-01-09 18:40:16 +08:00
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writel(bm_ctrl_error, base + IMX_OCOTP_ADDR_CTRL_CLR);
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2017-03-31 20:44:54 +08:00
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}
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2016-04-25 03:28:13 +08:00
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static int imx_ocotp_read(void *context, unsigned int offset,
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void *val, size_t bytes)
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2015-09-30 20:55:47 +08:00
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{
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struct ocotp_priv *priv = context;
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unsigned int count;
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2020-11-27 18:28:37 +08:00
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u8 *buf, *p;
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2016-06-02 19:05:11 +08:00
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int i, ret;
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2020-11-27 18:28:37 +08:00
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u32 index, num_bytes;
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2015-09-30 20:55:47 +08:00
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index = offset >> 2;
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2020-11-27 18:28:37 +08:00
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num_bytes = round_up((offset % 4) + bytes, 4);
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count = num_bytes >> 2;
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2015-09-30 20:55:47 +08:00
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2017-10-24 17:54:28 +08:00
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if (count > (priv->params->nregs - index))
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count = priv->params->nregs - index;
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2015-09-30 20:55:47 +08:00
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2020-11-27 18:28:37 +08:00
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p = kzalloc(num_bytes, GFP_KERNEL);
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if (!p)
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return -ENOMEM;
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2017-03-31 20:44:55 +08:00
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mutex_lock(&ocotp_mutex);
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2020-11-27 18:28:37 +08:00
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buf = p;
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2016-06-02 19:05:11 +08:00
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ret = clk_prepare_enable(priv->clk);
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if (ret < 0) {
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2017-03-31 20:44:55 +08:00
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mutex_unlock(&ocotp_mutex);
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2016-06-02 19:05:11 +08:00
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dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
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2020-11-27 18:28:37 +08:00
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kfree(p);
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2016-06-02 19:05:11 +08:00
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return ret;
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}
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2015-09-30 20:55:47 +08:00
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2020-01-09 18:40:16 +08:00
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ret = imx_ocotp_wait_for_busy(priv, 0);
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2017-03-31 20:44:55 +08:00
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if (ret < 0) {
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dev_err(priv->dev, "timeout during read setup\n");
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goto read_end;
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}
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2017-03-31 20:44:54 +08:00
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for (i = index; i < (index + count); i++) {
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2020-11-27 18:28:37 +08:00
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*(u32 *)buf = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 +
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2017-03-31 20:44:54 +08:00
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i * IMX_OCOTP_OFFSET_PER_WORD);
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2016-06-02 19:05:11 +08:00
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2017-03-31 20:44:54 +08:00
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/* 47.3.1.2
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* For "read locked" registers 0xBADABADA will be returned and
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* HW_OCOTP_CTRL[ERROR] will be set. It must be cleared by
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* software before any new write, read or reload access can be
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* issued
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*/
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2020-11-27 18:28:37 +08:00
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if (*((u32 *)buf) == IMX_OCOTP_READ_LOCKED_VAL)
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2020-01-09 18:40:16 +08:00
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imx_ocotp_clr_err_if_set(priv);
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2020-11-27 18:28:37 +08:00
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buf += 4;
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2017-03-31 20:44:54 +08:00
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}
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2020-11-27 18:28:37 +08:00
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index = offset % 4;
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memcpy(val, &p[index], bytes);
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2017-03-31 20:44:55 +08:00
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read_end:
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2017-03-31 20:44:54 +08:00
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clk_disable_unprepare(priv->clk);
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2017-03-31 20:44:55 +08:00
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mutex_unlock(&ocotp_mutex);
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2020-11-27 18:28:37 +08:00
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kfree(p);
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2017-03-31 20:44:55 +08:00
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return ret;
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}
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2023-02-06 21:43:46 +08:00
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static int imx_ocotp_cell_pp(void *context, const char *id, int index,
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unsigned int offset, void *data, size_t bytes)
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2021-10-13 21:19:57 +08:00
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{
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2023-04-05 01:21:26 +08:00
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u8 *buf = data;
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int i;
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2021-10-13 21:19:57 +08:00
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/* Deal with some post processing of nvmem cell data */
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2023-04-05 01:21:26 +08:00
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if (id && !strcmp(id, "mac-address"))
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for (i = 0; i < bytes / 2; i++)
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swap(buf[i], buf[bytes - i - 1]);
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2021-10-13 21:19:57 +08:00
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return 0;
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}
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2017-10-24 17:54:30 +08:00
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static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv)
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{
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2020-03-10 21:22:53 +08:00
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unsigned long clk_rate;
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2017-10-24 17:54:30 +08:00
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unsigned long strobe_read, relax, strobe_prog;
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2020-03-10 21:22:53 +08:00
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u32 timing;
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2017-10-24 17:54:30 +08:00
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/* 47.3.1.3.1
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* Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX]
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* fields with timing values to match the current frequency of the
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* ipg_clk. OTP writes will work at maximum bus frequencies as long
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* as the HW_OCOTP_TIMING parameters are set correctly.
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2019-06-26 18:27:30 +08:00
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*
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* Note: there are minimum timings required to ensure an OTP fuse burns
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* correctly that are independent of the ipg_clk. Those values are not
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* formally documented anywhere however, working from the minimum
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* timings given in u-boot we can say:
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*
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* - Minimum STROBE_PROG time is 10 microseconds. Intuitively 10
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* microseconds feels about right as representative of a minimum time
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* to physically burn out a fuse.
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*
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* - Minimum STROBE_READ i.e. the time to wait post OTP fuse burn before
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* performing another read is 37 nanoseconds
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*
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* - Minimum RELAX timing is 17 nanoseconds. This final RELAX minimum
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* timing is not entirely clear the documentation says "This
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* count value specifies the time to add to all default timing
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* parameters other than the Tpgm and Trd. It is given in number
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* of ipg_clk periods." where Tpgm and Trd refer to STROBE_PROG
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* and STROBE_READ respectively. What the other timing parameters
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* are though, is not specified. Experience shows a zero RELAX
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* value will mess up a re-load of the shadow registers post OTP
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* burn.
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2017-10-24 17:54:30 +08:00
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*/
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clk_rate = clk_get_rate(priv->clk);
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2019-06-26 18:27:30 +08:00
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relax = DIV_ROUND_UP(clk_rate * TIMING_RELAX_NS, 1000000000) - 1;
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strobe_read = DIV_ROUND_UP(clk_rate * TIMING_STROBE_READ_NS,
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1000000000);
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strobe_read += 2 * (relax + 1) - 1;
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strobe_prog = DIV_ROUND_CLOSEST(clk_rate * TIMING_STROBE_PROG_US,
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1000000);
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strobe_prog += 2 * (relax + 1) - 1;
|
2017-10-24 17:54:30 +08:00
|
|
|
|
2019-06-26 18:27:29 +08:00
|
|
|
timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000;
|
|
|
|
timing |= strobe_prog & 0x00000FFF;
|
2017-10-24 17:54:30 +08:00
|
|
|
timing |= (relax << 12) & 0x0000F000;
|
|
|
|
timing |= (strobe_read << 16) & 0x003F0000;
|
|
|
|
|
|
|
|
writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
|
|
|
|
}
|
|
|
|
|
2017-10-24 17:54:31 +08:00
|
|
|
static void imx_ocotp_set_imx7_timing(struct ocotp_priv *priv)
|
|
|
|
{
|
2020-03-10 21:22:53 +08:00
|
|
|
unsigned long clk_rate;
|
2017-10-24 17:54:31 +08:00
|
|
|
u64 fsource, strobe_prog;
|
2020-03-10 21:22:53 +08:00
|
|
|
u32 timing;
|
2017-10-24 17:54:31 +08:00
|
|
|
|
|
|
|
/* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1
|
|
|
|
* 6.4.3.3
|
|
|
|
*/
|
|
|
|
clk_rate = clk_get_rate(priv->clk);
|
|
|
|
fsource = DIV_ROUND_UP_ULL((u64)clk_rate * DEF_FSOURCE,
|
|
|
|
NSEC_PER_SEC) + 1;
|
|
|
|
strobe_prog = DIV_ROUND_CLOSEST_ULL((u64)clk_rate * DEF_STROBE_PROG,
|
|
|
|
NSEC_PER_SEC) + 1;
|
|
|
|
|
|
|
|
timing = strobe_prog & 0x00000FFF;
|
|
|
|
timing |= (fsource << 12) & 0x000FF000;
|
|
|
|
|
|
|
|
writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
|
|
|
|
}
|
|
|
|
|
2017-03-31 20:44:55 +08:00
|
|
|
static int imx_ocotp_write(void *context, unsigned int offset, void *val,
|
|
|
|
size_t bytes)
|
|
|
|
{
|
|
|
|
struct ocotp_priv *priv = context;
|
|
|
|
u32 *buf = val;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
u32 ctrl;
|
|
|
|
u8 waddr;
|
2017-10-24 17:54:29 +08:00
|
|
|
u8 word = 0;
|
2017-03-31 20:44:55 +08:00
|
|
|
|
|
|
|
/* allow only writing one complete OTP word at a time */
|
|
|
|
if ((bytes != priv->config->word_size) ||
|
|
|
|
(offset % priv->config->word_size))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
mutex_lock(&ocotp_mutex);
|
|
|
|
|
|
|
|
ret = clk_prepare_enable(priv->clk);
|
|
|
|
if (ret < 0) {
|
|
|
|
mutex_unlock(&ocotp_mutex);
|
|
|
|
dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-10-24 17:54:30 +08:00
|
|
|
/* Setup the write timing values */
|
2017-10-24 17:54:31 +08:00
|
|
|
priv->params->set_timing(priv);
|
2017-03-31 20:44:55 +08:00
|
|
|
|
|
|
|
/* 47.3.1.3.2
|
|
|
|
* Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear.
|
|
|
|
* Overlapped accesses are not supported by the controller. Any pending
|
|
|
|
* write or reload must be completed before a write access can be
|
|
|
|
* requested.
|
|
|
|
*/
|
2020-01-09 18:40:16 +08:00
|
|
|
ret = imx_ocotp_wait_for_busy(priv, 0);
|
2017-03-31 20:44:55 +08:00
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(priv->dev, "timeout during timing setup\n");
|
|
|
|
goto write_end;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* 47.3.1.3.3
|
|
|
|
* Write the requested address to HW_OCOTP_CTRL[ADDR] and program the
|
|
|
|
* unlock code into HW_OCOTP_CTRL[WR_UNLOCK]. This must be programmed
|
|
|
|
* for each write access. The lock code is documented in the register
|
|
|
|
* description. Both the unlock code and address can be written in the
|
|
|
|
* same operation.
|
|
|
|
*/
|
2017-10-24 17:54:29 +08:00
|
|
|
if (priv->params->bank_address_words != 0) {
|
|
|
|
/*
|
|
|
|
* In banked/i.MX7 mode the OTP register bank goes into waddr
|
|
|
|
* see i.MX 7Solo Applications Processor Reference Manual, Rev.
|
|
|
|
* 0.1 section 6.4.3.1
|
|
|
|
*/
|
|
|
|
offset = offset / priv->config->word_size;
|
|
|
|
waddr = offset / priv->params->bank_address_words;
|
|
|
|
word = offset & (priv->params->bank_address_words - 1);
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* Non-banked i.MX6 mode.
|
|
|
|
* OTP write/read address specifies one of 128 word address
|
|
|
|
* locations
|
|
|
|
*/
|
|
|
|
waddr = offset / 4;
|
|
|
|
}
|
2017-03-31 20:44:55 +08:00
|
|
|
|
|
|
|
ctrl = readl(priv->base + IMX_OCOTP_ADDR_CTRL);
|
2020-01-09 18:40:16 +08:00
|
|
|
ctrl &= ~priv->params->ctrl.bm_addr;
|
|
|
|
ctrl |= waddr & priv->params->ctrl.bm_addr;
|
2017-03-31 20:44:55 +08:00
|
|
|
ctrl |= IMX_OCOTP_WR_UNLOCK;
|
|
|
|
|
|
|
|
writel(ctrl, priv->base + IMX_OCOTP_ADDR_CTRL);
|
|
|
|
|
|
|
|
/* 47.3.1.3.4
|
|
|
|
* Write the data to the HW_OCOTP_DATA register. This will automatically
|
|
|
|
* set HW_OCOTP_CTRL[BUSY] and clear HW_OCOTP_CTRL[WR_UNLOCK]. To
|
|
|
|
* protect programming same OTP bit twice, before program OCOTP will
|
|
|
|
* automatically read fuse value in OTP and use read value to mask
|
|
|
|
* program data. The controller will use masked program data to program
|
|
|
|
* a 32-bit word in the OTP per the address in HW_OCOTP_CTRL[ADDR]. Bit
|
|
|
|
* fields with 1's will result in that OTP bit being programmed. Bit
|
|
|
|
* fields with 0's will be ignored. At the same time that the write is
|
|
|
|
* accepted, the controller makes an internal copy of
|
|
|
|
* HW_OCOTP_CTRL[ADDR] which cannot be updated until the next write
|
|
|
|
* sequence is initiated. This copy guarantees that erroneous writes to
|
|
|
|
* HW_OCOTP_CTRL[ADDR] will not affect an active write operation. It
|
|
|
|
* should also be noted that during the programming HW_OCOTP_DATA will
|
|
|
|
* shift right (with zero fill). This shifting is required to program
|
|
|
|
* the OTP serially. During the write operation, HW_OCOTP_DATA cannot be
|
|
|
|
* modified.
|
2017-10-24 17:54:29 +08:00
|
|
|
* Note: on i.MX7 there are four data fields to write for banked write
|
|
|
|
* with the fuse blowing operation only taking place after data0
|
|
|
|
* has been written. This is why data0 must always be the last
|
|
|
|
* register written.
|
2017-03-31 20:44:55 +08:00
|
|
|
*/
|
2017-10-24 17:54:29 +08:00
|
|
|
if (priv->params->bank_address_words != 0) {
|
|
|
|
/* Banked/i.MX7 mode */
|
|
|
|
switch (word) {
|
|
|
|
case 0:
|
|
|
|
writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
|
|
|
|
writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
|
|
|
|
writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
|
|
|
|
writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA1);
|
|
|
|
writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
|
|
|
|
writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
|
|
|
|
writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
|
|
|
|
writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA2);
|
|
|
|
writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
|
|
|
|
writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
|
|
|
|
break;
|
|
|
|
case 3:
|
|
|
|
writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
|
|
|
|
writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
|
|
|
|
writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA3);
|
|
|
|
writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* Non-banked i.MX6 mode */
|
|
|
|
writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
|
|
|
|
}
|
2017-03-31 20:44:55 +08:00
|
|
|
|
|
|
|
/* 47.4.1.4.5
|
|
|
|
* Once complete, the controller will clear BUSY. A write request to a
|
|
|
|
* protected or locked region will result in no OTP access and no
|
|
|
|
* setting of HW_OCOTP_CTRL[BUSY]. In addition HW_OCOTP_CTRL[ERROR] will
|
|
|
|
* be set. It must be cleared by software before any new write access
|
|
|
|
* can be issued.
|
|
|
|
*/
|
2020-01-09 18:40:16 +08:00
|
|
|
ret = imx_ocotp_wait_for_busy(priv, 0);
|
2017-03-31 20:44:55 +08:00
|
|
|
if (ret < 0) {
|
|
|
|
if (ret == -EPERM) {
|
|
|
|
dev_err(priv->dev, "failed write to locked region");
|
2020-01-09 18:40:16 +08:00
|
|
|
imx_ocotp_clr_err_if_set(priv);
|
2017-03-31 20:44:55 +08:00
|
|
|
} else {
|
|
|
|
dev_err(priv->dev, "timeout during data write\n");
|
|
|
|
}
|
|
|
|
goto write_end;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* 47.3.1.4
|
|
|
|
* Write Postamble: Due to internal electrical characteristics of the
|
|
|
|
* OTP during writes, all OTP operations following a write must be
|
|
|
|
* separated by 2 us after the clearing of HW_OCOTP_CTRL_BUSY following
|
|
|
|
* the write.
|
|
|
|
*/
|
|
|
|
udelay(2);
|
|
|
|
|
|
|
|
/* reload all shadow registers */
|
2020-01-09 18:40:16 +08:00
|
|
|
writel(priv->params->ctrl.bm_rel_shadows,
|
2017-03-31 20:44:55 +08:00
|
|
|
priv->base + IMX_OCOTP_ADDR_CTRL_SET);
|
2020-01-09 18:40:16 +08:00
|
|
|
ret = imx_ocotp_wait_for_busy(priv,
|
|
|
|
priv->params->ctrl.bm_rel_shadows);
|
2020-05-11 22:50:40 +08:00
|
|
|
if (ret < 0)
|
2017-03-31 20:44:55 +08:00
|
|
|
dev_err(priv->dev, "timeout during shadow register reload\n");
|
|
|
|
|
|
|
|
write_end:
|
|
|
|
clk_disable_unprepare(priv->clk);
|
|
|
|
mutex_unlock(&ocotp_mutex);
|
2020-05-11 22:50:40 +08:00
|
|
|
return ret < 0 ? ret : bytes;
|
2015-09-30 20:55:47 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static struct nvmem_config imx_ocotp_nvmem_config = {
|
|
|
|
.name = "imx-ocotp",
|
2017-03-31 20:44:55 +08:00
|
|
|
.read_only = false,
|
2016-04-25 03:28:13 +08:00
|
|
|
.word_size = 4,
|
2020-11-27 18:28:37 +08:00
|
|
|
.stride = 1,
|
2016-04-25 03:28:13 +08:00
|
|
|
.reg_read = imx_ocotp_read,
|
2017-03-31 20:44:55 +08:00
|
|
|
.reg_write = imx_ocotp_write,
|
2015-09-30 20:55:47 +08:00
|
|
|
};
|
|
|
|
|
2017-10-24 17:54:28 +08:00
|
|
|
static const struct ocotp_params imx6q_params = {
|
|
|
|
.nregs = 128,
|
2017-10-24 17:54:29 +08:00
|
|
|
.bank_address_words = 0,
|
2017-10-24 17:54:31 +08:00
|
|
|
.set_timing = imx_ocotp_set_imx6_timing,
|
2020-01-09 18:40:16 +08:00
|
|
|
.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
|
2017-10-24 17:54:28 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct ocotp_params imx6sl_params = {
|
|
|
|
.nregs = 64,
|
2017-10-24 17:54:29 +08:00
|
|
|
.bank_address_words = 0,
|
2017-10-24 17:54:31 +08:00
|
|
|
.set_timing = imx_ocotp_set_imx6_timing,
|
2020-01-09 18:40:16 +08:00
|
|
|
.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
|
2017-10-24 17:54:28 +08:00
|
|
|
};
|
|
|
|
|
2018-07-11 18:20:43 +08:00
|
|
|
static const struct ocotp_params imx6sll_params = {
|
2023-10-13 20:49:02 +08:00
|
|
|
.nregs = 80,
|
2018-07-11 18:20:43 +08:00
|
|
|
.bank_address_words = 0,
|
|
|
|
.set_timing = imx_ocotp_set_imx6_timing,
|
2020-01-09 18:40:16 +08:00
|
|
|
.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
|
2018-07-11 18:20:43 +08:00
|
|
|
};
|
|
|
|
|
2017-10-24 17:54:28 +08:00
|
|
|
static const struct ocotp_params imx6sx_params = {
|
|
|
|
.nregs = 128,
|
2017-10-24 17:54:29 +08:00
|
|
|
.bank_address_words = 0,
|
2017-10-24 17:54:31 +08:00
|
|
|
.set_timing = imx_ocotp_set_imx6_timing,
|
2020-01-09 18:40:16 +08:00
|
|
|
.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
|
2017-10-24 17:54:28 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct ocotp_params imx6ul_params = {
|
2023-10-13 20:49:03 +08:00
|
|
|
.nregs = 144,
|
2017-10-24 17:54:29 +08:00
|
|
|
.bank_address_words = 0,
|
2017-10-24 17:54:31 +08:00
|
|
|
.set_timing = imx_ocotp_set_imx6_timing,
|
2020-01-09 18:40:16 +08:00
|
|
|
.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
|
2017-10-24 17:54:28 +08:00
|
|
|
};
|
|
|
|
|
2019-01-28 23:54:59 +08:00
|
|
|
static const struct ocotp_params imx6ull_params = {
|
2023-10-13 20:49:04 +08:00
|
|
|
.nregs = 80,
|
2019-01-28 23:54:59 +08:00
|
|
|
.bank_address_words = 0,
|
|
|
|
.set_timing = imx_ocotp_set_imx6_timing,
|
2020-01-09 18:40:16 +08:00
|
|
|
.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
|
2019-01-28 23:54:59 +08:00
|
|
|
};
|
|
|
|
|
2017-10-24 17:54:28 +08:00
|
|
|
static const struct ocotp_params imx7d_params = {
|
|
|
|
.nregs = 64,
|
2017-10-24 17:54:29 +08:00
|
|
|
.bank_address_words = 4,
|
2017-10-24 17:54:31 +08:00
|
|
|
.set_timing = imx_ocotp_set_imx7_timing,
|
2020-01-09 18:40:16 +08:00
|
|
|
.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
|
2017-10-24 17:54:28 +08:00
|
|
|
};
|
|
|
|
|
2019-01-28 23:54:57 +08:00
|
|
|
static const struct ocotp_params imx7ulp_params = {
|
|
|
|
.nregs = 256,
|
|
|
|
.bank_address_words = 0,
|
2020-01-09 18:40:16 +08:00
|
|
|
.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
|
2019-01-28 23:54:57 +08:00
|
|
|
};
|
|
|
|
|
2019-04-13 18:32:47 +08:00
|
|
|
static const struct ocotp_params imx8mq_params = {
|
|
|
|
.nregs = 256,
|
2019-06-26 18:27:33 +08:00
|
|
|
.bank_address_words = 0,
|
|
|
|
.set_timing = imx_ocotp_set_imx6_timing,
|
2020-01-09 18:40:16 +08:00
|
|
|
.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
|
2019-04-13 18:32:47 +08:00
|
|
|
};
|
|
|
|
|
2019-06-26 18:27:31 +08:00
|
|
|
static const struct ocotp_params imx8mm_params = {
|
|
|
|
.nregs = 256,
|
|
|
|
.bank_address_words = 0,
|
|
|
|
.set_timing = imx_ocotp_set_imx6_timing,
|
2020-01-09 18:40:16 +08:00
|
|
|
.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
|
2019-06-26 18:27:31 +08:00
|
|
|
};
|
|
|
|
|
2019-08-18 17:33:40 +08:00
|
|
|
static const struct ocotp_params imx8mn_params = {
|
|
|
|
.nregs = 256,
|
|
|
|
.bank_address_words = 0,
|
|
|
|
.set_timing = imx_ocotp_set_imx6_timing,
|
2020-01-09 18:40:16 +08:00
|
|
|
.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
|
2019-08-18 17:33:40 +08:00
|
|
|
};
|
|
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2020-03-10 21:22:44 +08:00
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|
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static const struct ocotp_params imx8mp_params = {
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|
|
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.nregs = 384,
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|
|
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.bank_address_words = 0,
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.set_timing = imx_ocotp_set_imx6_timing,
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|
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.ctrl = IMX_OCOTP_BM_CTRL_8MP,
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};
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2015-09-30 20:55:47 +08:00
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static const struct of_device_id imx_ocotp_dt_ids[] = {
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2017-10-24 17:54:28 +08:00
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{ .compatible = "fsl,imx6q-ocotp", .data = &imx6q_params },
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|
|
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{ .compatible = "fsl,imx6sl-ocotp", .data = &imx6sl_params },
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|
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{ .compatible = "fsl,imx6sx-ocotp", .data = &imx6sx_params },
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|
|
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{ .compatible = "fsl,imx6ul-ocotp", .data = &imx6ul_params },
|
2019-01-28 23:54:59 +08:00
|
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|
{ .compatible = "fsl,imx6ull-ocotp", .data = &imx6ull_params },
|
2017-10-24 17:54:28 +08:00
|
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|
{ .compatible = "fsl,imx7d-ocotp", .data = &imx7d_params },
|
2018-07-11 18:20:43 +08:00
|
|
|
{ .compatible = "fsl,imx6sll-ocotp", .data = &imx6sll_params },
|
2019-01-28 23:54:57 +08:00
|
|
|
{ .compatible = "fsl,imx7ulp-ocotp", .data = &imx7ulp_params },
|
2019-04-13 18:32:47 +08:00
|
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|
{ .compatible = "fsl,imx8mq-ocotp", .data = &imx8mq_params },
|
2019-06-26 18:27:31 +08:00
|
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|
{ .compatible = "fsl,imx8mm-ocotp", .data = &imx8mm_params },
|
2019-08-18 17:33:40 +08:00
|
|
|
{ .compatible = "fsl,imx8mn-ocotp", .data = &imx8mn_params },
|
2020-03-10 21:22:44 +08:00
|
|
|
{ .compatible = "fsl,imx8mp-ocotp", .data = &imx8mp_params },
|
2015-09-30 20:55:47 +08:00
|
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|
{ },
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|
|
|
};
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|
MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids);
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|
|
|
2023-04-05 01:21:26 +08:00
|
|
|
static void imx_ocotp_fixup_cell_info(struct nvmem_device *nvmem,
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|
|
|
struct nvmem_layout *layout,
|
|
|
|
struct nvmem_cell_info *cell)
|
|
|
|
{
|
|
|
|
cell->read_post_process = imx_ocotp_cell_pp;
|
|
|
|
}
|
|
|
|
|
2023-06-11 22:03:05 +08:00
|
|
|
static struct nvmem_layout imx_ocotp_layout = {
|
2023-04-05 01:21:26 +08:00
|
|
|
.fixup_cell_info = imx_ocotp_fixup_cell_info,
|
|
|
|
};
|
|
|
|
|
2015-09-30 20:55:47 +08:00
|
|
|
static int imx_ocotp_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
struct ocotp_priv *priv;
|
|
|
|
struct nvmem_device *nvmem;
|
|
|
|
|
|
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
|
|
|
if (!priv)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2017-03-31 20:44:49 +08:00
|
|
|
priv->dev = dev;
|
|
|
|
|
2019-04-13 18:32:59 +08:00
|
|
|
priv->base = devm_platform_ioremap_resource(pdev, 0);
|
2015-09-30 20:55:47 +08:00
|
|
|
if (IS_ERR(priv->base))
|
|
|
|
return PTR_ERR(priv->base);
|
|
|
|
|
2017-03-31 20:44:49 +08:00
|
|
|
priv->clk = devm_clk_get(dev, NULL);
|
2016-06-02 19:05:11 +08:00
|
|
|
if (IS_ERR(priv->clk))
|
|
|
|
return PTR_ERR(priv->clk);
|
|
|
|
|
2017-10-24 17:54:28 +08:00
|
|
|
priv->params = of_device_get_match_data(&pdev->dev);
|
|
|
|
imx_ocotp_nvmem_config.size = 4 * priv->params->nregs;
|
2015-09-30 20:55:47 +08:00
|
|
|
imx_ocotp_nvmem_config.dev = dev;
|
2016-04-25 03:28:13 +08:00
|
|
|
imx_ocotp_nvmem_config.priv = priv;
|
2023-06-11 22:03:06 +08:00
|
|
|
imx_ocotp_nvmem_config.layout = &imx_ocotp_layout;
|
2023-04-05 01:21:26 +08:00
|
|
|
|
2017-03-31 20:44:55 +08:00
|
|
|
priv->config = &imx_ocotp_nvmem_config;
|
|
|
|
|
2020-01-09 18:40:16 +08:00
|
|
|
clk_prepare_enable(priv->clk);
|
|
|
|
imx_ocotp_clr_err_if_set(priv);
|
|
|
|
clk_disable_unprepare(priv->clk);
|
|
|
|
|
|
|
|
nvmem = devm_nvmem_register(dev, &imx_ocotp_nvmem_config);
|
2015-09-30 20:55:47 +08:00
|
|
|
|
2018-03-09 22:46:59 +08:00
|
|
|
return PTR_ERR_OR_ZERO(nvmem);
|
2015-09-30 20:55:47 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver imx_ocotp_driver = {
|
|
|
|
.probe = imx_ocotp_probe,
|
|
|
|
.driver = {
|
|
|
|
.name = "imx_ocotp",
|
|
|
|
.of_match_table = imx_ocotp_dt_ids,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
module_platform_driver(imx_ocotp_driver);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
|
2017-10-24 17:54:33 +08:00
|
|
|
MODULE_DESCRIPTION("i.MX6/i.MX7 OCOTP fuse box driver");
|
2015-09-30 20:55:47 +08:00
|
|
|
MODULE_LICENSE("GPL v2");
|