2019-06-01 16:09:00 +08:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2015-01-18 02:15:14 +08:00
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/*
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* Pin controller and GPIO driver for Amlogic Meson SoCs
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*
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* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
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*/
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2018-09-13 19:58:21 +08:00
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#include <linux/gpio/driver.h>
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2015-01-18 02:15:14 +08:00
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#include <linux/pinctrl/pinctrl.h>
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2017-10-12 20:40:25 +08:00
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#include <linux/platform_device.h>
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2015-01-18 02:15:14 +08:00
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#include <linux/regmap.h>
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#include <linux/types.h>
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pinctrl: meson: add a new callback for SoCs fixup
In meson_pinctrl_parse_dt, it contains two parts: reg parsing and
SoC relative fixup for AO. Several fixups in the same code make it hard
to maintain, so move all fixups to each SoC's callback and make
meson_pinctrl_parse_dt just do the reg parsing, separate these two
parts.Overview of all current Meson SoCs fixup is as below:
+------+--------------------------------------+--------------------------+
| | | |
| SoC | EE domain | AO domain |
+------+--------------------------------------+--------------------------+
|m8 | parse regs: | parse regs: |
|m8b | gpio,mux,pull,pull-enable(skip ds) | gpio,mux,pull(skip ds)|
|gxl | fixup: | fixup: |
|gxbb | no | pull-enable = pull; |
|axg | | |
+------+--------------------------------------+--------------------------+
|g12a | parse regs: | parse regs: |
|sm1 | gpio,mux,pull,pull-enable,ds | gpio,mux,ds |
| | fixup: | fixup: |
| | no | pull = gpio; |
| | | pull-enable = gpio; |
+------+--------------------------------------+--------------------------+
|a1 or | parse regs: |
|later | gpio/mux (without ao domain) |
|SoCs | fixup: |
| | pull = gpio; pull-enable = gpio; ds = gpio; |
+------+-----------------------------------------------------------------+
Since m8-axg share the same ao fixup, make a common function
meson8_aobus_parse_dt_extra to do the job.
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
Link: https://lore.kernel.org/r/1573819429-6937-2-git-send-email-qianggui.song@amlogic.com
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-15 20:03:47 +08:00
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struct meson_pinctrl;
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2015-01-18 02:15:14 +08:00
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/**
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* struct meson_pmx_group - a pinmux group
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*
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* @name: group name
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* @pins: pins in the group
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* @num_pins: number of pins in the group
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* @is_gpio: whether the group is a single GPIO group
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* @reg: register offset for the group in the domain mux registers
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* @bit bit index enabling the group
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* @domain: index of the domain this group belongs to
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*/
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struct meson_pmx_group {
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const char *name;
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const unsigned int *pins;
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unsigned int num_pins;
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2017-10-12 20:40:26 +08:00
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const void *data;
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2015-01-18 02:15:14 +08:00
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};
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/**
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* struct meson_pmx_func - a pinmux function
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*
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* @name: function name
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* @groups: groups in the function
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* @num_groups: number of groups in the function
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*/
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struct meson_pmx_func {
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const char *name;
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const char * const *groups;
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unsigned int num_groups;
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};
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/**
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* struct meson_reg_desc - a register descriptor
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*
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* @reg: register offset in the regmap
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* @bit: bit index in register
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*
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* The structure describes the information needed to control pull,
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* pull-enable, direction, etc. for a single pin
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*/
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struct meson_reg_desc {
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unsigned int reg;
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unsigned int bit;
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};
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/**
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* enum meson_reg_type - type of registers encoded in @meson_reg_desc
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*/
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enum meson_reg_type {
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REG_PULLEN,
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REG_PULL,
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REG_DIR,
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REG_OUT,
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REG_IN,
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2019-05-14 16:26:51 +08:00
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REG_DS,
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2015-01-18 02:15:14 +08:00
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NUM_REG,
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};
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2019-05-14 16:26:51 +08:00
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/**
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* enum meson_pinconf_drv - value of drive-strength supported
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*/
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enum meson_pinconf_drv {
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MESON_PINCONF_DRV_500UA,
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MESON_PINCONF_DRV_2500UA,
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MESON_PINCONF_DRV_3000UA,
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MESON_PINCONF_DRV_4000UA,
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};
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2015-01-18 02:15:14 +08:00
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/**
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* struct meson bank
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*
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* @name: bank name
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* @first: first pin of the bank
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* @last: last pin of the bank
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* @irq: hwirq base number of the bank
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2015-01-18 02:15:14 +08:00
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* @regs: array of register descriptors
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*
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* A bank represents a set of pins controlled by a contiguous set of
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* bits in the domain registers. The structure specifies which bits in
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* the regmap control the different functionalities. Each member of
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* the @regs array refers to the first pin of the bank.
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*/
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struct meson_bank {
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const char *name;
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unsigned int first;
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unsigned int last;
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2017-06-09 03:37:50 +08:00
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int irq_first;
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int irq_last;
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struct meson_reg_desc regs[NUM_REG];
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};
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struct meson_pinctrl_data {
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2016-08-14 01:41:18 +08:00
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const char *name;
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2015-01-18 02:15:14 +08:00
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const struct pinctrl_pin_desc *pins;
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struct meson_pmx_group *groups;
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struct meson_pmx_func *funcs;
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unsigned int num_pins;
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unsigned int num_groups;
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unsigned int num_funcs;
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2016-08-14 01:41:18 +08:00
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struct meson_bank *banks;
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unsigned int num_banks;
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2017-10-12 20:40:26 +08:00
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const struct pinmux_ops *pmx_ops;
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2017-11-20 18:08:24 +08:00
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void *pmx_data;
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pinctrl: meson: add a new callback for SoCs fixup
In meson_pinctrl_parse_dt, it contains two parts: reg parsing and
SoC relative fixup for AO. Several fixups in the same code make it hard
to maintain, so move all fixups to each SoC's callback and make
meson_pinctrl_parse_dt just do the reg parsing, separate these two
parts.Overview of all current Meson SoCs fixup is as below:
+------+--------------------------------------+--------------------------+
| | | |
| SoC | EE domain | AO domain |
+------+--------------------------------------+--------------------------+
|m8 | parse regs: | parse regs: |
|m8b | gpio,mux,pull,pull-enable(skip ds) | gpio,mux,pull(skip ds)|
|gxl | fixup: | fixup: |
|gxbb | no | pull-enable = pull; |
|axg | | |
+------+--------------------------------------+--------------------------+
|g12a | parse regs: | parse regs: |
|sm1 | gpio,mux,pull,pull-enable,ds | gpio,mux,ds |
| | fixup: | fixup: |
| | no | pull = gpio; |
| | | pull-enable = gpio; |
+------+--------------------------------------+--------------------------+
|a1 or | parse regs: |
|later | gpio/mux (without ao domain) |
|SoCs | fixup: |
| | pull = gpio; pull-enable = gpio; ds = gpio; |
+------+-----------------------------------------------------------------+
Since m8-axg share the same ao fixup, make a common function
meson8_aobus_parse_dt_extra to do the job.
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
Link: https://lore.kernel.org/r/1573819429-6937-2-git-send-email-qianggui.song@amlogic.com
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-15 20:03:47 +08:00
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int (*parse_dt)(struct meson_pinctrl *pc);
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2015-01-18 02:15:14 +08:00
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};
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struct meson_pinctrl {
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struct device *dev;
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struct pinctrl_dev *pcdev;
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struct pinctrl_desc desc;
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struct meson_pinctrl_data *data;
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2016-08-14 01:41:18 +08:00
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struct regmap *reg_mux;
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struct regmap *reg_pullen;
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struct regmap *reg_pull;
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struct regmap *reg_gpio;
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2019-01-17 18:23:15 +08:00
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struct regmap *reg_ds;
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2016-08-14 01:41:18 +08:00
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struct gpio_chip chip;
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struct device_node *of_node;
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2015-01-18 02:15:14 +08:00
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};
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#define FUNCTION(fn) \
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{ \
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.name = #fn, \
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.groups = fn ## _groups, \
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.num_groups = ARRAY_SIZE(fn ## _groups), \
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}
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2019-05-14 16:26:51 +08:00
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#define BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib, \
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dsr, dsb) \
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{ \
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2017-06-09 03:37:50 +08:00
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.name = n, \
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.first = f, \
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.last = l, \
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.irq_first = fi, \
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.irq_last = li, \
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.regs = { \
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[REG_PULLEN] = { per, peb }, \
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[REG_PULL] = { pr, pb }, \
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[REG_DIR] = { dr, db }, \
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[REG_OUT] = { or, ob }, \
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[REG_IN] = { ir, ib }, \
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2019-05-14 16:26:51 +08:00
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[REG_DS] = { dsr, dsb }, \
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2015-01-18 02:15:14 +08:00
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}, \
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}
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2019-05-14 16:26:51 +08:00
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#define BANK(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
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BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib, 0, 0)
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2017-09-20 21:39:20 +08:00
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#define MESON_PIN(x) PINCTRL_PIN(x, #x)
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2015-01-18 02:15:14 +08:00
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2017-10-12 20:40:26 +08:00
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/* Common pmx functions */
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int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev);
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const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev,
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unsigned selector);
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int meson_pmx_get_groups(struct pinctrl_dev *pcdev,
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unsigned selector,
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const char * const **groups,
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unsigned * const num_groups);
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2017-10-12 20:40:25 +08:00
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/* Common probe function */
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int meson_pinctrl_probe(struct platform_device *pdev);
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pinctrl: meson: add a new callback for SoCs fixup
In meson_pinctrl_parse_dt, it contains two parts: reg parsing and
SoC relative fixup for AO. Several fixups in the same code make it hard
to maintain, so move all fixups to each SoC's callback and make
meson_pinctrl_parse_dt just do the reg parsing, separate these two
parts.Overview of all current Meson SoCs fixup is as below:
+------+--------------------------------------+--------------------------+
| | | |
| SoC | EE domain | AO domain |
+------+--------------------------------------+--------------------------+
|m8 | parse regs: | parse regs: |
|m8b | gpio,mux,pull,pull-enable(skip ds) | gpio,mux,pull(skip ds)|
|gxl | fixup: | fixup: |
|gxbb | no | pull-enable = pull; |
|axg | | |
+------+--------------------------------------+--------------------------+
|g12a | parse regs: | parse regs: |
|sm1 | gpio,mux,pull,pull-enable,ds | gpio,mux,ds |
| | fixup: | fixup: |
| | no | pull = gpio; |
| | | pull-enable = gpio; |
+------+--------------------------------------+--------------------------+
|a1 or | parse regs: |
|later | gpio/mux (without ao domain) |
|SoCs | fixup: |
| | pull = gpio; pull-enable = gpio; ds = gpio; |
+------+-----------------------------------------------------------------+
Since m8-axg share the same ao fixup, make a common function
meson8_aobus_parse_dt_extra to do the job.
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
Link: https://lore.kernel.org/r/1573819429-6937-2-git-send-email-qianggui.song@amlogic.com
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-11-15 20:03:47 +08:00
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/* Common ao groups extra dt parse function for SoCs before g12a */
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int meson8_aobus_parse_dt_extra(struct meson_pinctrl *pc);
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