OpenCloudOS-Kernel/arch/arm/mach-s3c/regs-gpio-s3c64xx.h

/* SPDX-License-Identifier: GPL-2.0 */
/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h
 *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *      http://armlinux.simtec.co.uk/
 *
 * S3C64XX - GPIO register definitions
 */

#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H
#define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__

/* Base addresses for each of the banks */

#define S3C64XX_GPIOREG(reg)	(S3C64XX_VA_GPIO + (reg))

#define S3C64XX_GPA_BASE	S3C64XX_GPIOREG(0x0000)
#define S3C64XX_GPB_BASE	S3C64XX_GPIOREG(0x0020)
#define S3C64XX_GPC_BASE	S3C64XX_GPIOREG(0x0040)
#define S3C64XX_GPD_BASE	S3C64XX_GPIOREG(0x0060)
#define S3C64XX_GPE_BASE	S3C64XX_GPIOREG(0x0080)
#define S3C64XX_GPF_BASE	S3C64XX_GPIOREG(0x00A0)
#define S3C64XX_GPG_BASE	S3C64XX_GPIOREG(0x00C0)
#define S3C64XX_GPH_BASE	S3C64XX_GPIOREG(0x00E0)
#define S3C64XX_GPI_BASE	S3C64XX_GPIOREG(0x0100)
#define S3C64XX_GPJ_BASE	S3C64XX_GPIOREG(0x0120)
#define S3C64XX_GPK_BASE	S3C64XX_GPIOREG(0x0800)
#define S3C64XX_GPL_BASE	S3C64XX_GPIOREG(0x0810)
#define S3C64XX_GPM_BASE	S3C64XX_GPIOREG(0x0820)
#define S3C64XX_GPN_BASE	S3C64XX_GPIOREG(0x0830)
#define S3C64XX_GPO_BASE	S3C64XX_GPIOREG(0x0140)
#define S3C64XX_GPP_BASE	S3C64XX_GPIOREG(0x0160)
#define S3C64XX_GPQ_BASE	S3C64XX_GPIOREG(0x0180)

/* SPCON */

#define S3C64XX_SPCON		S3C64XX_GPIOREG(0x1A0)

#define S3C64XX_SPCON_DRVCON_CAM_MASK		(0x3 << 30)
#define S3C64XX_SPCON_DRVCON_CAM_SHIFT		(30)
#define S3C64XX_SPCON_DRVCON_CAM_2mA		(0x0 << 30)
#define S3C64XX_SPCON_DRVCON_CAM_4mA		(0x1 << 30)
#define S3C64XX_SPCON_DRVCON_CAM_7mA		(0x2 << 30)
#define S3C64XX_SPCON_DRVCON_CAM_9mA		(0x3 << 30)

#define S3C64XX_SPCON_DRVCON_HSSPI_MASK		(0x3 << 28)
#define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT	(28)
#define S3C64XX_SPCON_DRVCON_HSSPI_2mA		(0x0 << 28)
#define S3C64XX_SPCON_DRVCON_HSSPI_4mA		(0x1 << 28)
#define S3C64XX_SPCON_DRVCON_HSSPI_7mA		(0x2 << 28)
#define S3C64XX_SPCON_DRVCON_HSSPI_9mA		(0x3 << 28)

#define S3C64XX_SPCON_DRVCON_HSMMC_MASK		(0x3 << 26)
#define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT	(26)
#define S3C64XX_SPCON_DRVCON_HSMMC_2mA		(0x0 << 26)
#define S3C64XX_SPCON_DRVCON_HSMMC_4mA		(0x1 << 26)
#define S3C64XX_SPCON_DRVCON_HSMMC_7mA		(0x2 << 26)
#define S3C64XX_SPCON_DRVCON_HSMMC_9mA		(0x3 << 26)

#define S3C64XX_SPCON_DRVCON_LCD_MASK		(0x3 << 24)
#define S3C64XX_SPCON_DRVCON_LCD_SHIFT		(24)
#define S3C64XX_SPCON_DRVCON_LCD_2mA		(0x0 << 24)
#define S3C64XX_SPCON_DRVCON_LCD_4mA		(0x1 << 24)
#define S3C64XX_SPCON_DRVCON_LCD_7mA		(0x2 << 24)
#define S3C64XX_SPCON_DRVCON_LCD_9mA		(0x3 << 24)

#define S3C64XX_SPCON_DRVCON_MODEM_MASK		(0x3 << 22)
#define S3C64XX_SPCON_DRVCON_MODEM_SHIFT	(22)
#define S3C64XX_SPCON_DRVCON_MODEM_2mA		(0x0 << 22)
#define S3C64XX_SPCON_DRVCON_MODEM_4mA		(0x1 << 22)
#define S3C64XX_SPCON_DRVCON_MODEM_7mA		(0x2 << 22)
#define S3C64XX_SPCON_DRVCON_MODEM_9mA		(0x3 << 22)

#define S3C64XX_SPCON_nRSTOUT_OEN		(1 << 21)

#define S3C64XX_SPCON_DRVCON_SPICLK1_MASK	(0x3 << 18)
#define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT	(18)
#define S3C64XX_SPCON_DRVCON_SPICLK1_2mA	(0x0 << 18)
#define S3C64XX_SPCON_DRVCON_SPICLK1_4mA	(0x1 << 18)
#define S3C64XX_SPCON_DRVCON_SPICLK1_7mA	(0x2 << 18)
#define S3C64XX_SPCON_DRVCON_SPICLK1_9mA	(0x3 << 18)

#define S3C64XX_SPCON_MEM1_DQS_PUD_MASK		(0x3 << 16)
#define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT	(16)
#define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED	(0x0 << 16)
#define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN		(0x1 << 16)
#define S3C64XX_SPCON_MEM1_DQS_PUD_UP		(0x2 << 16)

#define S3C64XX_SPCON_MEM1_D_PUD1_MASK		(0x3 << 14)
#define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT		(14)
#define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED	(0x0 << 14)
#define S3C64XX_SPCON_MEM1_D_PUD1_DOWN		(0x1 << 14)
#define S3C64XX_SPCON_MEM1_D_PUD1_UP		(0x2 << 14)

#define S3C64XX_SPCON_MEM1_D_PUD0_MASK		(0x3 << 12)
#define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT		(12)
#define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED	(0x0 << 12)
#define S3C64XX_SPCON_MEM1_D_PUD0_DOWN		(0x1 << 12)
#define S3C64XX_SPCON_MEM1_D_PUD0_UP		(0x2 << 12)

#define S3C64XX_SPCON_MEM0_D_PUD_MASK		(0x3 << 8)
#define S3C64XX_SPCON_MEM0_D_PUD_SHIFT		(8)
#define S3C64XX_SPCON_MEM0_D_PUD_DISABLED	(0x0 << 8)
#define S3C64XX_SPCON_MEM0_D_PUD_DOWN		(0x1 << 8)
#define S3C64XX_SPCON_MEM0_D_PUD_UP		(0x2 << 8)

#define S3C64XX_SPCON_USBH_DMPD			(1 << 7)
#define S3C64XX_SPCON_USBH_DPPD			(1 << 6)
#define S3C64XX_SPCON_USBH_PUSW2		(1 << 5)
#define S3C64XX_SPCON_USBH_PUSW1		(1 << 4)
#define S3C64XX_SPCON_USBH_SUSPND		(1 << 3)

#define S3C64XX_SPCON_LCD_SEL_MASK		(0x3 << 0)
#define S3C64XX_SPCON_LCD_SEL_SHIFT		(0)
#define S3C64XX_SPCON_LCD_SEL_HOST		(0x0 << 0)
#define S3C64XX_SPCON_LCD_SEL_RGB		(0x1 << 0)
#define S3C64XX_SPCON_LCD_SEL_606_656		(0x2 << 0)


/* External interrupt registers */

#define S3C64XX_EINT12CON	S3C64XX_GPIOREG(0x200)
#define S3C64XX_EINT34CON	S3C64XX_GPIOREG(0x204)
#define S3C64XX_EINT56CON	S3C64XX_GPIOREG(0x208)
#define S3C64XX_EINT78CON	S3C64XX_GPIOREG(0x20C)
#define S3C64XX_EINT9CON	S3C64XX_GPIOREG(0x210)

#define S3C64XX_EINT12FLTCON	S3C64XX_GPIOREG(0x220)
#define S3C64XX_EINT34FLTCON	S3C64XX_GPIOREG(0x224)
#define S3C64XX_EINT56FLTCON	S3C64XX_GPIOREG(0x228)
#define S3C64XX_EINT78FLTCON	S3C64XX_GPIOREG(0x22C)
#define S3C64XX_EINT9FLTCON	S3C64XX_GPIOREG(0x230)

#define S3C64XX_EINT12MASK	S3C64XX_GPIOREG(0x240)
#define S3C64XX_EINT34MASK	S3C64XX_GPIOREG(0x244)
#define S3C64XX_EINT56MASK	S3C64XX_GPIOREG(0x248)
#define S3C64XX_EINT78MASK	S3C64XX_GPIOREG(0x24C)
#define S3C64XX_EINT9MASK	S3C64XX_GPIOREG(0x250)

#define S3C64XX_EINT12PEND	S3C64XX_GPIOREG(0x260)
#define S3C64XX_EINT34PEND	S3C64XX_GPIOREG(0x264)
#define S3C64XX_EINT56PEND	S3C64XX_GPIOREG(0x268)
#define S3C64XX_EINT78PEND	S3C64XX_GPIOREG(0x26C)
#define S3C64XX_EINT9PEND	S3C64XX_GPIOREG(0x270)

#define S3C64XX_PRIORITY	S3C64XX_GPIOREG(0x280)
#define S3C64XX_PRIORITY_ARB(x)	(1 << (x))

#define S3C64XX_SERVICE		S3C64XX_GPIOREG(0x284)
#define S3C64XX_SERVICEPEND	S3C64XX_GPIOREG(0x288)

#define S3C64XX_EINT0CON0	S3C64XX_GPIOREG(0x900)
#define S3C64XX_EINT0CON1	S3C64XX_GPIOREG(0x904)
#define S3C64XX_EINT0FLTCON0	S3C64XX_GPIOREG(0x910)
#define S3C64XX_EINT0FLTCON1	S3C64XX_GPIOREG(0x914)
#define S3C64XX_EINT0FLTCON2	S3C64XX_GPIOREG(0x918)
#define S3C64XX_EINT0FLTCON3	S3C64XX_GPIOREG(0x91C)

#define S3C64XX_EINT0MASK	S3C64XX_GPIOREG(0x920)
#define S3C64XX_EINT0PEND	S3C64XX_GPIOREG(0x924)

/* GPIO sleep configuration */

#define S3C64XX_SPCONSLP	S3C64XX_GPIOREG(0x880)

#define S3C64XX_SPCONSLP_TDO_PULLDOWN	(1 << 14)
#define S3C64XX_SPCONSLP_CKE1INIT	(1 << 5)

#define S3C64XX_SPCONSLP_RSTOUT_MASK	(0x3 << 12)
#define S3C64XX_SPCONSLP_RSTOUT_OUT0	(0x0 << 12)
#define S3C64XX_SPCONSLP_RSTOUT_OUT1	(0x1 << 12)
#define S3C64XX_SPCONSLP_RSTOUT_HIZ	(0x2 << 12)

#define S3C64XX_SPCONSLP_KPCOL_MASK	(0x3 << 0)
#define S3C64XX_SPCONSLP_KPCOL_OUT0	(0x0 << 0)
#define S3C64XX_SPCONSLP_KPCOL_OUT1	(0x1 << 0)
#define S3C64XX_SPCONSLP_KPCOL_INP	(0x2 << 0)


#define S3C64XX_SLPEN		S3C64XX_GPIOREG(0x930)

#define S3C64XX_SLPEN_USE_xSLP		(1 << 0)
#define S3C64XX_SLPEN_CFG_BYSLPEN	(1 << 1)

#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */
License cleanup: add SPDX GPL-2.0 license identifier to files with no license Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a /uapi/ one with no licensing information in it, - file was a /uapi/ one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non /uapi/ files that summary was: SPDX license identifier # files ---------------------------------------------------\|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a /uapi/ path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------\|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the /uapi/ ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------\|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2017-11-01 22:07:57 +08:00			`/* SPDX-License-Identifier: GPL-2.0 */`
[ARM] S3C64XX: GPIO library support Add gpiolib registration for the GPIOs available on the S3C64XX platform Signed-off-by: Ben Dooks <ben-linux@fluff.org> 2008-11-01 00:14:33 +08:00			`/* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h`
			`*`
			`* Copyright 2008 Openmoko, Inc.`
			`* Copyright 2008 Simtec Electronics`
			`* Ben Dooks <ben@simtec.co.uk>`
			`* http://armlinux.simtec.co.uk/`
			`*`
			`* S3C64XX - GPIO register definitions`
			`*/`

			`#ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H`
			`#define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__`

			`/* Base addresses for each of the banks */`

[ARM] S3C64XX: Add EINT group regs and move IRQ_EINT to regs-gpio.h Add definitions for the EINT group registers and move the EINT IRQ register definitions out of arch/arm/plat-s3c64xx/irq-eint.c so that they are available for re-use with PM and the other code. Signed-off-by: Ben Dooks <ben-linux@fluff.org> 2008-12-12 08:24:15 +08:00			`#define S3C64XX_GPIOREG(reg) (S3C64XX_VA_GPIO + (reg))`

			`#define S3C64XX_GPA_BASE S3C64XX_GPIOREG(0x0000)`
			`#define S3C64XX_GPB_BASE S3C64XX_GPIOREG(0x0020)`
			`#define S3C64XX_GPC_BASE S3C64XX_GPIOREG(0x0040)`
			`#define S3C64XX_GPD_BASE S3C64XX_GPIOREG(0x0060)`
			`#define S3C64XX_GPE_BASE S3C64XX_GPIOREG(0x0080)`
			`#define S3C64XX_GPF_BASE S3C64XX_GPIOREG(0x00A0)`
			`#define S3C64XX_GPG_BASE S3C64XX_GPIOREG(0x00C0)`
			`#define S3C64XX_GPH_BASE S3C64XX_GPIOREG(0x00E0)`
			`#define S3C64XX_GPI_BASE S3C64XX_GPIOREG(0x0100)`
			`#define S3C64XX_GPJ_BASE S3C64XX_GPIOREG(0x0120)`
			`#define S3C64XX_GPK_BASE S3C64XX_GPIOREG(0x0800)`
			`#define S3C64XX_GPL_BASE S3C64XX_GPIOREG(0x0810)`
			`#define S3C64XX_GPM_BASE S3C64XX_GPIOREG(0x0820)`
			`#define S3C64XX_GPN_BASE S3C64XX_GPIOREG(0x0830)`
			`#define S3C64XX_GPO_BASE S3C64XX_GPIOREG(0x0140)`
			`#define S3C64XX_GPP_BASE S3C64XX_GPIOREG(0x0160)`
			`#define S3C64XX_GPQ_BASE S3C64XX_GPIOREG(0x0180)`

[ARM] S3C64XX: Add GPIO SPCONSLP and SLPEN register definitions Add GPIO register definitions for SPCONSLP and SLPEN for controlling the state of the pins over sleep. Signed-off-by: Ben Dooks <ben-linux@fluff.org> 2008-12-12 08:24:17 +08:00			`/* SPCON */`

			`#define S3C64XX_SPCON S3C64XX_GPIOREG(0x1A0)`

[ARM] S3C64XX: Add S3C64XX_SPCON register bit definitions Add the definitions for the SPCON register in the GPIO block. Signed-off-by: Ben Dooks <ben-linux@fluff.org> 2008-12-12 08:24:39 +08:00			`#define S3C64XX_SPCON_DRVCON_CAM_MASK (0x3 << 30)`
			`#define S3C64XX_SPCON_DRVCON_CAM_SHIFT (30)`
			`#define S3C64XX_SPCON_DRVCON_CAM_2mA (0x0 << 30)`
			`#define S3C64XX_SPCON_DRVCON_CAM_4mA (0x1 << 30)`
			`#define S3C64XX_SPCON_DRVCON_CAM_7mA (0x2 << 30)`
			`#define S3C64XX_SPCON_DRVCON_CAM_9mA (0x3 << 30)`

			`#define S3C64XX_SPCON_DRVCON_HSSPI_MASK (0x3 << 28)`
			`#define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT (28)`
			`#define S3C64XX_SPCON_DRVCON_HSSPI_2mA (0x0 << 28)`
			`#define S3C64XX_SPCON_DRVCON_HSSPI_4mA (0x1 << 28)`
			`#define S3C64XX_SPCON_DRVCON_HSSPI_7mA (0x2 << 28)`
			`#define S3C64XX_SPCON_DRVCON_HSSPI_9mA (0x3 << 28)`

			`#define S3C64XX_SPCON_DRVCON_HSMMC_MASK (0x3 << 26)`
			`#define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT (26)`
			`#define S3C64XX_SPCON_DRVCON_HSMMC_2mA (0x0 << 26)`
			`#define S3C64XX_SPCON_DRVCON_HSMMC_4mA (0x1 << 26)`
			`#define S3C64XX_SPCON_DRVCON_HSMMC_7mA (0x2 << 26)`
			`#define S3C64XX_SPCON_DRVCON_HSMMC_9mA (0x3 << 26)`

			`#define S3C64XX_SPCON_DRVCON_LCD_MASK (0x3 << 24)`
			`#define S3C64XX_SPCON_DRVCON_LCD_SHIFT (24)`
			`#define S3C64XX_SPCON_DRVCON_LCD_2mA (0x0 << 24)`
			`#define S3C64XX_SPCON_DRVCON_LCD_4mA (0x1 << 24)`
			`#define S3C64XX_SPCON_DRVCON_LCD_7mA (0x2 << 24)`
			`#define S3C64XX_SPCON_DRVCON_LCD_9mA (0x3 << 24)`

			`#define S3C64XX_SPCON_DRVCON_MODEM_MASK (0x3 << 22)`
			`#define S3C64XX_SPCON_DRVCON_MODEM_SHIFT (22)`
			`#define S3C64XX_SPCON_DRVCON_MODEM_2mA (0x0 << 22)`
			`#define S3C64XX_SPCON_DRVCON_MODEM_4mA (0x1 << 22)`
			`#define S3C64XX_SPCON_DRVCON_MODEM_7mA (0x2 << 22)`
			`#define S3C64XX_SPCON_DRVCON_MODEM_9mA (0x3 << 22)`

			`#define S3C64XX_SPCON_nRSTOUT_OEN (1 << 21)`

			`#define S3C64XX_SPCON_DRVCON_SPICLK1_MASK (0x3 << 18)`
			`#define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT (18)`
			`#define S3C64XX_SPCON_DRVCON_SPICLK1_2mA (0x0 << 18)`
			`#define S3C64XX_SPCON_DRVCON_SPICLK1_4mA (0x1 << 18)`
			`#define S3C64XX_SPCON_DRVCON_SPICLK1_7mA (0x2 << 18)`
			`#define S3C64XX_SPCON_DRVCON_SPICLK1_9mA (0x3 << 18)`

			`#define S3C64XX_SPCON_MEM1_DQS_PUD_MASK (0x3 << 16)`
			`#define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT (16)`
			`#define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED (0x0 << 16)`
			`#define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN (0x1 << 16)`
			`#define S3C64XX_SPCON_MEM1_DQS_PUD_UP (0x2 << 16)`

			`#define S3C64XX_SPCON_MEM1_D_PUD1_MASK (0x3 << 14)`
			`#define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT (14)`
			`#define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED (0x0 << 14)`
			`#define S3C64XX_SPCON_MEM1_D_PUD1_DOWN (0x1 << 14)`
			`#define S3C64XX_SPCON_MEM1_D_PUD1_UP (0x2 << 14)`

			`#define S3C64XX_SPCON_MEM1_D_PUD0_MASK (0x3 << 12)`
			`#define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT (12)`
			`#define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED (0x0 << 12)`
			`#define S3C64XX_SPCON_MEM1_D_PUD0_DOWN (0x1 << 12)`
			`#define S3C64XX_SPCON_MEM1_D_PUD0_UP (0x2 << 12)`

			`#define S3C64XX_SPCON_MEM0_D_PUD_MASK (0x3 << 8)`
			`#define S3C64XX_SPCON_MEM0_D_PUD_SHIFT (8)`
			`#define S3C64XX_SPCON_MEM0_D_PUD_DISABLED (0x0 << 8)`
			`#define S3C64XX_SPCON_MEM0_D_PUD_DOWN (0x1 << 8)`
			`#define S3C64XX_SPCON_MEM0_D_PUD_UP (0x2 << 8)`

			`#define S3C64XX_SPCON_USBH_DMPD (1 << 7)`
			`#define S3C64XX_SPCON_USBH_DPPD (1 << 6)`
			`#define S3C64XX_SPCON_USBH_PUSW2 (1 << 5)`
			`#define S3C64XX_SPCON_USBH_PUSW1 (1 << 4)`
			`#define S3C64XX_SPCON_USBH_SUSPND (1 << 3)`

			`#define S3C64XX_SPCON_LCD_SEL_MASK (0x3 << 0)`
			`#define S3C64XX_SPCON_LCD_SEL_SHIFT (0)`
			`#define S3C64XX_SPCON_LCD_SEL_HOST (0x0 << 0)`
			`#define S3C64XX_SPCON_LCD_SEL_RGB (0x1 << 0)`
			`#define S3C64XX_SPCON_LCD_SEL_606_656 (0x2 << 0)`


[ARM] S3C64XX: Add EINT group regs and move IRQ_EINT to regs-gpio.h Add definitions for the EINT group registers and move the EINT IRQ register definitions out of arch/arm/plat-s3c64xx/irq-eint.c so that they are available for re-use with PM and the other code. Signed-off-by: Ben Dooks <ben-linux@fluff.org> 2008-12-12 08:24:15 +08:00			`/* External interrupt registers */`

			`#define S3C64XX_EINT12CON S3C64XX_GPIOREG(0x200)`
			`#define S3C64XX_EINT34CON S3C64XX_GPIOREG(0x204)`
			`#define S3C64XX_EINT56CON S3C64XX_GPIOREG(0x208)`
			`#define S3C64XX_EINT78CON S3C64XX_GPIOREG(0x20C)`
			`#define S3C64XX_EINT9CON S3C64XX_GPIOREG(0x210)`

			`#define S3C64XX_EINT12FLTCON S3C64XX_GPIOREG(0x220)`
			`#define S3C64XX_EINT34FLTCON S3C64XX_GPIOREG(0x224)`
			`#define S3C64XX_EINT56FLTCON S3C64XX_GPIOREG(0x228)`
			`#define S3C64XX_EINT78FLTCON S3C64XX_GPIOREG(0x22C)`
			`#define S3C64XX_EINT9FLTCON S3C64XX_GPIOREG(0x230)`

			`#define S3C64XX_EINT12MASK S3C64XX_GPIOREG(0x240)`
			`#define S3C64XX_EINT34MASK S3C64XX_GPIOREG(0x244)`
			`#define S3C64XX_EINT56MASK S3C64XX_GPIOREG(0x248)`
			`#define S3C64XX_EINT78MASK S3C64XX_GPIOREG(0x24C)`
			`#define S3C64XX_EINT9MASK S3C64XX_GPIOREG(0x250)`

			`#define S3C64XX_EINT12PEND S3C64XX_GPIOREG(0x260)`
			`#define S3C64XX_EINT34PEND S3C64XX_GPIOREG(0x264)`
			`#define S3C64XX_EINT56PEND S3C64XX_GPIOREG(0x268)`
			`#define S3C64XX_EINT78PEND S3C64XX_GPIOREG(0x26C)`
			`#define S3C64XX_EINT9PEND S3C64XX_GPIOREG(0x270)`

			`#define S3C64XX_PRIORITY S3C64XX_GPIOREG(0x280)`
			`#define S3C64XX_PRIORITY_ARB(x) (1 << (x))`

			`#define S3C64XX_SERVICE S3C64XX_GPIOREG(0x284)`
			`#define S3C64XX_SERVICEPEND S3C64XX_GPIOREG(0x288)`

			`#define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900)`
			`#define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904)`
			`#define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910)`
			`#define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914)`
			`#define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918)`
			`#define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C)`

			`#define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920)`
			`#define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924)`
[ARM] S3C64XX: GPIO library support Add gpiolib registration for the GPIOs available on the S3C64XX platform Signed-off-by: Ben Dooks <ben-linux@fluff.org> 2008-11-01 00:14:33 +08:00
[ARM] S3C64XX: Add GPIO SPCONSLP and SLPEN register definitions Add GPIO register definitions for SPCONSLP and SLPEN for controlling the state of the pins over sleep. Signed-off-by: Ben Dooks <ben-linux@fluff.org> 2008-12-12 08:24:17 +08:00			`/* GPIO sleep configuration */`

			`#define S3C64XX_SPCONSLP S3C64XX_GPIOREG(0x880)`

			`#define S3C64XX_SPCONSLP_TDO_PULLDOWN (1 << 14)`
			`#define S3C64XX_SPCONSLP_CKE1INIT (1 << 5)`

			`#define S3C64XX_SPCONSLP_RSTOUT_MASK (0x3 << 12)`
			`#define S3C64XX_SPCONSLP_RSTOUT_OUT0 (0x0 << 12)`
			`#define S3C64XX_SPCONSLP_RSTOUT_OUT1 (0x1 << 12)`
			`#define S3C64XX_SPCONSLP_RSTOUT_HIZ (0x2 << 12)`

			`#define S3C64XX_SPCONSLP_KPCOL_MASK (0x3 << 0)`
			`#define S3C64XX_SPCONSLP_KPCOL_OUT0 (0x0 << 0)`
			`#define S3C64XX_SPCONSLP_KPCOL_OUT1 (0x1 << 0)`
			`#define S3C64XX_SPCONSLP_KPCOL_INP (0x2 << 0)`


			`#define S3C64XX_SLPEN S3C64XX_GPIOREG(0x930)`

			`#define S3C64XX_SLPEN_USE_xSLP (1 << 0)`
			`#define S3C64XX_SLPEN_CFG_BYSLPEN (1 << 1)`

[ARM] S3C64XX: GPIO library support Add gpiolib registration for the GPIOs available on the S3C64XX platform Signed-off-by: Ben Dooks <ben-linux@fluff.org> 2008-11-01 00:14:33 +08:00			`#endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */`