2013-03-09 16:02:52 +08:00
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* Samsung Exynos4 Clock Controller
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The Exynos4 clock controller generates and supplies clock to various controllers
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within the Exynos4 SoC. The clock binding described here is applicable to all
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SoC's in the Exynos4 family.
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Required Properties:
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- comptible: should be one of the following.
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- "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
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- "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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The following is the list of clocks generated by the controller. Each clock is
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assigned an identifier and client nodes use this identifier to specify the
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clock which they consume. Some of the clocks are available only on a particular
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Exynos4 SoC and this is specified where applicable.
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[Core Clocks]
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Clock ID SoC (if specific)
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-----------------------------------------------
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xxti 1
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xusbxti 2
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fin_pll 3
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fout_apll 4
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fout_mpll 5
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fout_epll 6
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fout_vpll 7
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sclk_apll 8
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sclk_mpll 9
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sclk_epll 10
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sclk_vpll 11
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arm_clk 12
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aclk200 13
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aclk100 14
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aclk160 15
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aclk133 16
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2013-04-04 12:32:37 +08:00
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mout_mpll_user_t 17 Exynos4x12
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mout_mpll_user_c 18 Exynos4x12
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2013-04-04 12:32:59 +08:00
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mout_core 19
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mout_apll 20
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2013-03-09 16:02:52 +08:00
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[Clock Gate for Special Clocks]
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Clock ID SoC (if specific)
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-----------------------------------------------
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sclk_fimc0 128
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sclk_fimc1 129
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sclk_fimc2 130
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sclk_fimc3 131
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sclk_cam0 132
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sclk_cam1 133
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sclk_csis0 134
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sclk_csis1 135
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sclk_hdmi 136
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sclk_mixer 137
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sclk_dac 138
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sclk_pixel 139
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sclk_fimd0 140
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sclk_mdnie0 141 Exynos4412
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sclk_mdnie_pwm0 12 142 Exynos4412
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sclk_mipi0 143
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sclk_audio0 144
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sclk_mmc0 145
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sclk_mmc1 146
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sclk_mmc2 147
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sclk_mmc3 148
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sclk_mmc4 149
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sclk_sata 150 Exynos4210
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sclk_uart0 151
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sclk_uart1 152
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sclk_uart2 153
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sclk_uart3 154
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sclk_uart4 155
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sclk_audio1 156
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sclk_audio2 157
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sclk_spdif 158
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sclk_spi0 159
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sclk_spi1 160
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sclk_spi2 161
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sclk_slimbus 162
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sclk_fimd1 163 Exynos4210
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sclk_mipi1 164 Exynos4210
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sclk_pcm1 165
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sclk_pcm2 166
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sclk_i2s1 167
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sclk_i2s2 168
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sclk_mipihsi 169 Exynos4412
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2013-04-04 12:32:33 +08:00
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sclk_mfc 170
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2013-04-04 12:32:51 +08:00
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sclk_pcm0 171
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2013-03-09 16:02:52 +08:00
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[Peripheral Clock Gates]
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Clock ID SoC (if specific)
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-----------------------------------------------
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fimc0 256
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fimc1 257
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fimc2 258
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fimc3 259
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csis0 260
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csis1 261
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jpeg 262
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smmu_fimc0 263
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smmu_fimc1 264
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smmu_fimc2 265
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smmu_fimc3 266
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smmu_jpeg 267
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vp 268
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mixer 269
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tvenc 270 Exynos4210
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hdmi 271
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smmu_tv 272
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mfc 273
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smmu_mfcl 274
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smmu_mfcr 275
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g3d 276
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g2d 277 Exynos4210
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rotator 278 Exynos4210
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mdma 279 Exynos4210
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smmu_g2d 280 Exynos4210
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smmu_rotator 281 Exynos4210
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smmu_mdma 282 Exynos4210
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fimd0 283
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mie0 284
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mdnie0 285 Exynos4412
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dsim0 286
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smmu_fimd0 287
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fimd1 288 Exynos4210
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mie1 289 Exynos4210
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dsim1 290 Exynos4210
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smmu_fimd1 291 Exynos4210
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pdma0 292
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pdma1 293
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pcie_phy 294
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sata_phy 295 Exynos4210
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tsi 296
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sdmmc0 297
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sdmmc1 298
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sdmmc2 299
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sdmmc3 300
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sdmmc4 301
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sata 302 Exynos4210
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sromc 303
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usb_host 304
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usb_device 305
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pcie 306
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onenand 307
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nfcon 308
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smmu_pcie 309
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gps 310
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smmu_gps 311
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uart0 312
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uart1 313
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uart2 314
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uart3 315
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uart4 316
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i2c0 317
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i2c1 318
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i2c2 319
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i2c3 320
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i2c4 321
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i2c5 322
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i2c6 323
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i2c7 324
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i2c_hdmi 325
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tsadc 326
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spi0 327
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spi1 328
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spi2 329
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i2s1 330
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i2s2 331
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pcm0 332
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i2s0 333
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pcm1 334
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pcm2 335
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pwm 336
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slimbus 337
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spdif 338
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ac97 339
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modemif 340
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chipid 341
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sysreg 342
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hdmi_cec 343
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mct 344
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wdt 345
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rtc 346
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keyif 347
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audss 348
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mipi_hsi 349 Exynos4210
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mdma2 350 Exynos4210
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Example 1: An example of a clock controller node is listed below.
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clock: clock-controller@0x10030000 {
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compatible = "samsung,exynos4210-clock";
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reg = <0x10030000 0x20000>;
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#clock-cells = <1>;
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};
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Example 2: UART controller node that consumes the clock generated by the clock
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controller. Refer to the standard clock bindings for information
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about 'clocks' and 'clock-names' property.
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serial@13820000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x13820000 0x100>;
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interrupts = <0 54 0>;
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clocks = <&clock 314>, <&clock 153>;
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clock-names = "uart", "clk_uart_baud0";
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};
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