2006-06-26 15:25:03 +08:00
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/*
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2008-04-16 19:24:42 +08:00
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* omap-rng.c - RNG driver for TI OMAP CPU family
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2006-06-26 15:25:03 +08:00
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*
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* Author: Deepak Saxena <dsaxena@plexity.net>
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*
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* Copyright 2005 (c) MontaVista Software, Inc.
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*
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* Mostly based on original driver:
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*
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* Copyright (C) 2005 Nokia Corporation
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2007-10-20 05:21:04 +08:00
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* Author: Juha Yrjölä <juha.yrjola@nokia.com>
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2006-06-26 15:25:03 +08:00
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/random.h>
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#include <linux/err.h>
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2006-08-06 03:14:04 +08:00
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#include <linux/platform_device.h>
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2006-06-26 15:25:03 +08:00
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#include <linux/hw_random.h>
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2007-11-21 12:24:45 +08:00
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#include <linux/delay.h>
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2020-06-29 16:03:55 +08:00
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#include <linux/kernel.h>
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2012-09-24 07:28:26 +08:00
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#include <linux/slab.h>
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2012-09-24 07:28:26 +08:00
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#include <linux/pm_runtime.h>
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2013-08-05 22:47:21 +08:00
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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2013-08-05 22:47:23 +08:00
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#include <linux/interrupt.h>
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2016-09-16 18:08:55 +08:00
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#include <linux/clk.h>
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2021-02-19 19:19:18 +08:00
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#include <linux/io.h>
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2006-06-26 15:25:03 +08:00
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2013-08-05 22:47:23 +08:00
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#define RNG_REG_STATUS_RDY (1 << 0)
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#define RNG_REG_INTACK_RDY_MASK (1 << 0)
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#define RNG_REG_INTACK_SHUTDOWN_OFLO_MASK (1 << 1)
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#define RNG_SHUTDOWN_OFLO_MASK (1 << 1)
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#define RNG_CONTROL_STARTUP_CYCLES_SHIFT 16
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#define RNG_CONTROL_STARTUP_CYCLES_MASK (0xffff << 16)
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#define RNG_CONTROL_ENABLE_TRNG_SHIFT 10
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#define RNG_CONTROL_ENABLE_TRNG_MASK (1 << 10)
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#define RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT 16
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#define RNG_CONFIG_MAX_REFIL_CYCLES_MASK (0xffff << 16)
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#define RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT 0
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#define RNG_CONFIG_MIN_REFIL_CYCLES_MASK (0xff << 0)
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#define RNG_CONTROL_STARTUP_CYCLES 0xff
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#define RNG_CONFIG_MIN_REFIL_CYCLES 0x21
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#define RNG_CONFIG_MAX_REFIL_CYCLES 0x22
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#define RNG_ALARMCNT_ALARM_TH_SHIFT 0x0
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#define RNG_ALARMCNT_ALARM_TH_MASK (0xff << 0)
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#define RNG_ALARMCNT_SHUTDOWN_TH_SHIFT 16
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#define RNG_ALARMCNT_SHUTDOWN_TH_MASK (0x1f << 16)
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#define RNG_ALARM_THRESHOLD 0xff
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#define RNG_SHUTDOWN_THRESHOLD 0x4
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#define RNG_REG_FROENABLE_MASK 0xffffff
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#define RNG_REG_FRODETUNE_MASK 0xffffff
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#define OMAP2_RNG_OUTPUT_SIZE 0x4
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#define OMAP4_RNG_OUTPUT_SIZE 0x8
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2016-09-16 18:08:55 +08:00
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#define EIP76_RNG_OUTPUT_SIZE 0x10
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2013-08-05 22:47:23 +08:00
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2019-10-14 20:02:45 +08:00
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/*
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* EIP76 RNG takes approx. 700us to produce 16 bytes of output data
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* as per testing results. And to account for the lack of udelay()'s
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* reliability, we keep the timeout as 1000us.
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*/
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#define RNG_DATA_FILL_TIMEOUT 100
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2013-08-05 22:47:23 +08:00
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enum {
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2016-09-16 18:08:53 +08:00
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RNG_OUTPUT_0_REG = 0,
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RNG_OUTPUT_1_REG,
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RNG_OUTPUT_2_REG,
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RNG_OUTPUT_3_REG,
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2013-08-05 22:47:23 +08:00
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RNG_STATUS_REG,
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RNG_INTMASK_REG,
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RNG_INTACK_REG,
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RNG_CONTROL_REG,
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RNG_CONFIG_REG,
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RNG_ALARMCNT_REG,
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RNG_FROENABLE_REG,
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RNG_FRODETUNE_REG,
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RNG_ALARMMASK_REG,
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RNG_ALARMSTOP_REG,
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RNG_REV_REG,
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RNG_SYSCONFIG_REG,
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};
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static const u16 reg_map_omap2[] = {
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2016-09-16 18:08:53 +08:00
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[RNG_OUTPUT_0_REG] = 0x0,
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2013-08-05 22:47:23 +08:00
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[RNG_STATUS_REG] = 0x4,
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[RNG_CONFIG_REG] = 0x28,
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[RNG_REV_REG] = 0x3c,
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[RNG_SYSCONFIG_REG] = 0x40,
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};
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static const u16 reg_map_omap4[] = {
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2016-09-16 18:08:53 +08:00
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[RNG_OUTPUT_0_REG] = 0x0,
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[RNG_OUTPUT_1_REG] = 0x4,
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2013-08-05 22:47:23 +08:00
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[RNG_STATUS_REG] = 0x8,
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[RNG_INTMASK_REG] = 0xc,
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[RNG_INTACK_REG] = 0x10,
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[RNG_CONTROL_REG] = 0x14,
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[RNG_CONFIG_REG] = 0x18,
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[RNG_ALARMCNT_REG] = 0x1c,
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[RNG_FROENABLE_REG] = 0x20,
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[RNG_FRODETUNE_REG] = 0x24,
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[RNG_ALARMMASK_REG] = 0x28,
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[RNG_ALARMSTOP_REG] = 0x2c,
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[RNG_REV_REG] = 0x1FE0,
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[RNG_SYSCONFIG_REG] = 0x1FE4,
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};
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2006-06-26 15:25:03 +08:00
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2016-09-16 18:08:55 +08:00
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static const u16 reg_map_eip76[] = {
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[RNG_OUTPUT_0_REG] = 0x0,
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[RNG_OUTPUT_1_REG] = 0x4,
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[RNG_OUTPUT_2_REG] = 0x8,
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[RNG_OUTPUT_3_REG] = 0xc,
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[RNG_STATUS_REG] = 0x10,
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[RNG_INTACK_REG] = 0x10,
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[RNG_CONTROL_REG] = 0x14,
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[RNG_CONFIG_REG] = 0x18,
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[RNG_ALARMCNT_REG] = 0x1c,
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[RNG_FROENABLE_REG] = 0x20,
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[RNG_FRODETUNE_REG] = 0x24,
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[RNG_ALARMMASK_REG] = 0x28,
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[RNG_ALARMSTOP_REG] = 0x2c,
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[RNG_REV_REG] = 0x7c,
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};
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2013-08-05 22:47:23 +08:00
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struct omap_rng_dev;
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2012-09-24 07:28:26 +08:00
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/**
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2013-08-05 22:47:23 +08:00
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* struct omap_rng_pdata - RNG IP block-specific data
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* @regs: Pointer to the register offsets structure.
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* @data_size: No. of bytes in RNG output.
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* @data_present: Callback to determine if data is available.
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* @init: Callback for IP specific initialization sequence.
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* @cleanup: Callback for IP specific cleanup sequence.
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2012-09-24 07:28:26 +08:00
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*/
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2013-08-05 22:47:23 +08:00
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struct omap_rng_pdata {
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u16 *regs;
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u32 data_size;
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u32 (*data_present)(struct omap_rng_dev *priv);
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int (*init)(struct omap_rng_dev *priv);
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void (*cleanup)(struct omap_rng_dev *priv);
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2012-09-24 07:28:26 +08:00
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};
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2006-06-26 15:25:03 +08:00
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2013-08-05 22:47:23 +08:00
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struct omap_rng_dev {
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void __iomem *base;
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struct device *dev;
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const struct omap_rng_pdata *pdata;
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2016-09-16 18:08:52 +08:00
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struct hwrng rng;
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2016-09-16 18:08:55 +08:00
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struct clk *clk;
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2018-02-28 22:27:23 +08:00
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struct clk *clk_reg;
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2013-08-05 22:47:23 +08:00
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};
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static inline u32 omap_rng_read(struct omap_rng_dev *priv, u16 reg)
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{
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return __raw_readl(priv->base + priv->pdata->regs[reg]);
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}
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static inline void omap_rng_write(struct omap_rng_dev *priv, u16 reg,
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u32 val)
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2006-06-26 15:25:03 +08:00
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{
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2013-08-05 22:47:23 +08:00
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__raw_writel(val, priv->base + priv->pdata->regs[reg]);
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2006-06-26 15:25:03 +08:00
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}
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2016-09-16 18:08:51 +08:00
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static int omap_rng_do_read(struct hwrng *rng, void *data, size_t max,
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bool wait)
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2006-06-26 15:25:03 +08:00
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{
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2013-08-05 22:47:23 +08:00
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struct omap_rng_dev *priv;
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2016-09-16 18:08:51 +08:00
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int i, present;
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2007-11-21 12:24:45 +08:00
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2013-08-05 22:47:23 +08:00
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priv = (struct omap_rng_dev *)rng->priv;
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2012-09-24 07:28:26 +08:00
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2016-09-16 18:08:51 +08:00
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if (max < priv->pdata->data_size)
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return 0;
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2019-10-14 20:02:45 +08:00
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for (i = 0; i < RNG_DATA_FILL_TIMEOUT; i++) {
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2016-09-16 18:08:51 +08:00
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present = priv->pdata->data_present(priv);
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if (present || !wait)
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2007-11-21 12:24:45 +08:00
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break;
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2016-09-16 18:08:51 +08:00
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2007-11-21 12:24:45 +08:00
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udelay(10);
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}
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2016-09-16 18:08:51 +08:00
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if (!present)
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return 0;
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2013-08-05 22:47:23 +08:00
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2016-09-16 18:08:53 +08:00
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memcpy_fromio(data, priv->base + priv->pdata->regs[RNG_OUTPUT_0_REG],
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2016-09-16 18:08:51 +08:00
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priv->pdata->data_size);
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2013-08-05 22:47:23 +08:00
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if (priv->pdata->regs[RNG_INTACK_REG])
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omap_rng_write(priv, RNG_INTACK_REG, RNG_REG_INTACK_RDY_MASK);
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2016-09-16 18:08:51 +08:00
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return priv->pdata->data_size;
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2013-08-05 22:47:23 +08:00
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}
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2013-08-21 02:07:53 +08:00
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static int omap_rng_init(struct hwrng *rng)
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{
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struct omap_rng_dev *priv;
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priv = (struct omap_rng_dev *)rng->priv;
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return priv->pdata->init(priv);
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}
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static void omap_rng_cleanup(struct hwrng *rng)
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{
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struct omap_rng_dev *priv;
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priv = (struct omap_rng_dev *)rng->priv;
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priv->pdata->cleanup(priv);
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}
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static inline u32 omap2_rng_data_present(struct omap_rng_dev *priv)
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{
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return omap_rng_read(priv, RNG_STATUS_REG) ? 0 : 1;
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}
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static int omap2_rng_init(struct omap_rng_dev *priv)
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{
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omap_rng_write(priv, RNG_SYSCONFIG_REG, 0x1);
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return 0;
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}
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static void omap2_rng_cleanup(struct omap_rng_dev *priv)
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{
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omap_rng_write(priv, RNG_SYSCONFIG_REG, 0x0);
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}
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static struct omap_rng_pdata omap2_rng_pdata = {
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.regs = (u16 *)reg_map_omap2,
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.data_size = OMAP2_RNG_OUTPUT_SIZE,
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.data_present = omap2_rng_data_present,
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.init = omap2_rng_init,
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.cleanup = omap2_rng_cleanup,
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};
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static inline u32 omap4_rng_data_present(struct omap_rng_dev *priv)
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{
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return omap_rng_read(priv, RNG_STATUS_REG) & RNG_REG_STATUS_RDY;
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}
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2016-09-16 18:08:55 +08:00
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static int eip76_rng_init(struct omap_rng_dev *priv)
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{
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u32 val;
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/* Return if RNG is already running. */
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if (omap_rng_read(priv, RNG_CONTROL_REG) & RNG_CONTROL_ENABLE_TRNG_MASK)
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return 0;
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/* Number of 512 bit blocks of raw Noise Source output data that must
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* be processed by either the Conditioning Function or the
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* SP 800-90 DRBG ‘BC_DF’ functionality to yield a ‘full entropy’
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* output value.
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*/
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val = 0x5 << RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT;
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/* Number of FRO samples that are XOR-ed together into one bit to be
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* shifted into the main shift register
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*/
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|
|
val |= RNG_CONFIG_MAX_REFIL_CYCLES << RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT;
|
|
|
|
|
omap_rng_write(priv, RNG_CONFIG_REG, val);
|
|
|
|
|
|
|
|
|
|
/* Enable all available FROs */
|
|
|
|
|
omap_rng_write(priv, RNG_FRODETUNE_REG, 0x0);
|
|
|
|
|
omap_rng_write(priv, RNG_FROENABLE_REG, RNG_REG_FROENABLE_MASK);
|
|
|
|
|
|
|
|
|
|
/* Enable TRNG */
|
|
|
|
|
val = RNG_CONTROL_ENABLE_TRNG_MASK;
|
|
|
|
|
omap_rng_write(priv, RNG_CONTROL_REG, val);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-05 22:47:23 +08:00
|
|
|
|
static int omap4_rng_init(struct omap_rng_dev *priv)
|
|
|
|
|
{
|
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
|
|
/* Return if RNG is already running. */
|
2015-03-16 09:54:50 +08:00
|
|
|
|
if (omap_rng_read(priv, RNG_CONTROL_REG) & RNG_CONTROL_ENABLE_TRNG_MASK)
|
2013-08-05 22:47:23 +08:00
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
val = RNG_CONFIG_MIN_REFIL_CYCLES << RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT;
|
|
|
|
|
val |= RNG_CONFIG_MAX_REFIL_CYCLES << RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT;
|
|
|
|
|
omap_rng_write(priv, RNG_CONFIG_REG, val);
|
|
|
|
|
|
|
|
|
|
omap_rng_write(priv, RNG_FRODETUNE_REG, 0x0);
|
|
|
|
|
omap_rng_write(priv, RNG_FROENABLE_REG, RNG_REG_FROENABLE_MASK);
|
|
|
|
|
val = RNG_ALARM_THRESHOLD << RNG_ALARMCNT_ALARM_TH_SHIFT;
|
|
|
|
|
val |= RNG_SHUTDOWN_THRESHOLD << RNG_ALARMCNT_SHUTDOWN_TH_SHIFT;
|
|
|
|
|
omap_rng_write(priv, RNG_ALARMCNT_REG, val);
|
|
|
|
|
|
|
|
|
|
val = RNG_CONTROL_STARTUP_CYCLES << RNG_CONTROL_STARTUP_CYCLES_SHIFT;
|
|
|
|
|
val |= RNG_CONTROL_ENABLE_TRNG_MASK;
|
|
|
|
|
omap_rng_write(priv, RNG_CONTROL_REG, val);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void omap4_rng_cleanup(struct omap_rng_dev *priv)
|
|
|
|
|
{
|
|
|
|
|
int val;
|
|
|
|
|
|
|
|
|
|
val = omap_rng_read(priv, RNG_CONTROL_REG);
|
|
|
|
|
val &= ~RNG_CONTROL_ENABLE_TRNG_MASK;
|
2015-03-16 07:19:11 +08:00
|
|
|
|
omap_rng_write(priv, RNG_CONTROL_REG, val);
|
2013-08-05 22:47:23 +08:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static irqreturn_t omap4_rng_irq(int irq, void *dev_id)
|
|
|
|
|
{
|
|
|
|
|
struct omap_rng_dev *priv = dev_id;
|
|
|
|
|
u32 fro_detune, fro_enable;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Interrupt raised by a fro shutdown threshold, do the following:
|
|
|
|
|
* 1. Clear the alarm events.
|
|
|
|
|
* 2. De tune the FROs which are shutdown.
|
|
|
|
|
* 3. Re enable the shutdown FROs.
|
|
|
|
|
*/
|
|
|
|
|
omap_rng_write(priv, RNG_ALARMMASK_REG, 0x0);
|
|
|
|
|
omap_rng_write(priv, RNG_ALARMSTOP_REG, 0x0);
|
|
|
|
|
|
|
|
|
|
fro_enable = omap_rng_read(priv, RNG_FROENABLE_REG);
|
|
|
|
|
fro_detune = ~fro_enable & RNG_REG_FRODETUNE_MASK;
|
|
|
|
|
fro_detune = fro_detune | omap_rng_read(priv, RNG_FRODETUNE_REG);
|
|
|
|
|
fro_enable = RNG_REG_FROENABLE_MASK;
|
2012-09-24 07:28:26 +08:00
|
|
|
|
|
2013-08-05 22:47:23 +08:00
|
|
|
|
omap_rng_write(priv, RNG_FRODETUNE_REG, fro_detune);
|
|
|
|
|
omap_rng_write(priv, RNG_FROENABLE_REG, fro_enable);
|
2012-09-24 07:28:26 +08:00
|
|
|
|
|
2013-08-05 22:47:23 +08:00
|
|
|
|
omap_rng_write(priv, RNG_INTACK_REG, RNG_REG_INTACK_SHUTDOWN_OFLO_MASK);
|
2006-06-26 15:25:03 +08:00
|
|
|
|
|
2013-08-05 22:47:23 +08:00
|
|
|
|
return IRQ_HANDLED;
|
2006-06-26 15:25:03 +08:00
|
|
|
|
}
|
|
|
|
|
|
2013-08-05 22:47:23 +08:00
|
|
|
|
static struct omap_rng_pdata omap4_rng_pdata = {
|
|
|
|
|
.regs = (u16 *)reg_map_omap4,
|
|
|
|
|
.data_size = OMAP4_RNG_OUTPUT_SIZE,
|
|
|
|
|
.data_present = omap4_rng_data_present,
|
|
|
|
|
.init = omap4_rng_init,
|
|
|
|
|
.cleanup = omap4_rng_cleanup,
|
|
|
|
|
};
|
|
|
|
|
|
2016-09-16 18:08:55 +08:00
|
|
|
|
static struct omap_rng_pdata eip76_rng_pdata = {
|
|
|
|
|
.regs = (u16 *)reg_map_eip76,
|
|
|
|
|
.data_size = EIP76_RNG_OUTPUT_SIZE,
|
|
|
|
|
.data_present = omap4_rng_data_present,
|
|
|
|
|
.init = eip76_rng_init,
|
|
|
|
|
.cleanup = omap4_rng_cleanup,
|
|
|
|
|
};
|
|
|
|
|
|
2020-06-29 16:03:55 +08:00
|
|
|
|
static const struct of_device_id omap_rng_of_match[] __maybe_unused = {
|
2013-08-05 22:47:23 +08:00
|
|
|
|
{
|
|
|
|
|
.compatible = "ti,omap2-rng",
|
|
|
|
|
.data = &omap2_rng_pdata,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.compatible = "ti,omap4-rng",
|
|
|
|
|
.data = &omap4_rng_pdata,
|
|
|
|
|
},
|
2016-09-16 18:08:55 +08:00
|
|
|
|
{
|
|
|
|
|
.compatible = "inside-secure,safexcel-eip76",
|
|
|
|
|
.data = &eip76_rng_pdata,
|
|
|
|
|
},
|
2013-08-05 22:47:21 +08:00
|
|
|
|
{},
|
|
|
|
|
};
|
|
|
|
|
MODULE_DEVICE_TABLE(of, omap_rng_of_match);
|
2013-08-05 22:47:23 +08:00
|
|
|
|
|
|
|
|
|
static int of_get_omap_rng_device_details(struct omap_rng_dev *priv,
|
|
|
|
|
struct platform_device *pdev)
|
|
|
|
|
{
|
|
|
|
|
struct device *dev = &pdev->dev;
|
|
|
|
|
int irq, err;
|
|
|
|
|
|
2021-03-22 14:51:51 +08:00
|
|
|
|
priv->pdata = of_device_get_match_data(dev);
|
|
|
|
|
if (!priv->pdata)
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
2013-08-05 22:47:23 +08:00
|
|
|
|
|
2016-09-16 18:08:55 +08:00
|
|
|
|
if (of_device_is_compatible(dev->of_node, "ti,omap4-rng") ||
|
|
|
|
|
of_device_is_compatible(dev->of_node, "inside-secure,safexcel-eip76")) {
|
2013-08-05 22:47:23 +08:00
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
2020-04-04 22:45:57 +08:00
|
|
|
|
if (irq < 0)
|
2013-08-05 22:47:23 +08:00
|
|
|
|
return irq;
|
|
|
|
|
|
|
|
|
|
err = devm_request_irq(dev, irq, omap4_rng_irq,
|
|
|
|
|
IRQF_TRIGGER_NONE, dev_name(dev), priv);
|
|
|
|
|
if (err) {
|
|
|
|
|
dev_err(dev, "unable to request irq %d, err = %d\n",
|
|
|
|
|
irq, err);
|
|
|
|
|
return err;
|
|
|
|
|
}
|
2016-09-16 18:08:55 +08:00
|
|
|
|
|
2017-03-07 22:14:48 +08:00
|
|
|
|
/*
|
|
|
|
|
* On OMAP4, enabling the shutdown_oflo interrupt is
|
|
|
|
|
* done in the interrupt mask register. There is no
|
|
|
|
|
* such register on EIP76, and it's enabled by the
|
|
|
|
|
* same bit in the control register
|
|
|
|
|
*/
|
|
|
|
|
if (priv->pdata->regs[RNG_INTMASK_REG])
|
|
|
|
|
omap_rng_write(priv, RNG_INTMASK_REG,
|
|
|
|
|
RNG_SHUTDOWN_OFLO_MASK);
|
|
|
|
|
else
|
|
|
|
|
omap_rng_write(priv, RNG_CONTROL_REG,
|
|
|
|
|
RNG_SHUTDOWN_OFLO_MASK);
|
2013-08-05 22:47:23 +08:00
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
2013-08-05 22:47:21 +08:00
|
|
|
|
|
2013-08-05 22:47:23 +08:00
|
|
|
|
static int get_omap_rng_device_details(struct omap_rng_dev *omap_rng)
|
|
|
|
|
{
|
|
|
|
|
/* Only OMAP2/3 can be non-DT */
|
|
|
|
|
omap_rng->pdata = &omap2_rng_pdata;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2012-12-22 07:12:08 +08:00
|
|
|
|
static int omap_rng_probe(struct platform_device *pdev)
|
2006-06-26 15:25:03 +08:00
|
|
|
|
{
|
2013-08-05 22:47:23 +08:00
|
|
|
|
struct omap_rng_dev *priv;
|
|
|
|
|
struct device *dev = &pdev->dev;
|
2006-06-26 15:25:03 +08:00
|
|
|
|
int ret;
|
|
|
|
|
|
2013-08-05 22:47:23 +08:00
|
|
|
|
priv = devm_kzalloc(dev, sizeof(struct omap_rng_dev), GFP_KERNEL);
|
2014-04-29 16:15:36 +08:00
|
|
|
|
if (!priv)
|
2012-09-24 07:28:26 +08:00
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
2016-09-16 18:08:52 +08:00
|
|
|
|
priv->rng.read = omap_rng_do_read;
|
|
|
|
|
priv->rng.init = omap_rng_init;
|
|
|
|
|
priv->rng.cleanup = omap_rng_cleanup;
|
2019-03-11 18:58:57 +08:00
|
|
|
|
priv->rng.quality = 900;
|
2016-09-16 18:08:52 +08:00
|
|
|
|
|
|
|
|
|
priv->rng.priv = (unsigned long)priv;
|
2013-05-29 08:47:29 +08:00
|
|
|
|
platform_set_drvdata(pdev, priv);
|
2013-08-05 22:47:23 +08:00
|
|
|
|
priv->dev = dev;
|
2006-06-26 15:25:03 +08:00
|
|
|
|
|
2019-10-16 18:46:16 +08:00
|
|
|
|
priv->base = devm_platform_ioremap_resource(pdev, 0);
|
2013-01-21 18:08:59 +08:00
|
|
|
|
if (IS_ERR(priv->base)) {
|
|
|
|
|
ret = PTR_ERR(priv->base);
|
2008-09-04 21:07:22 +08:00
|
|
|
|
goto err_ioremap;
|
|
|
|
|
}
|
2006-06-26 15:25:03 +08:00
|
|
|
|
|
2016-09-16 18:08:52 +08:00
|
|
|
|
priv->rng.name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
|
|
|
|
|
if (!priv->rng.name) {
|
|
|
|
|
ret = -ENOMEM;
|
|
|
|
|
goto err_ioremap;
|
|
|
|
|
}
|
|
|
|
|
|
2012-09-24 07:28:26 +08:00
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
2016-06-25 00:50:39 +08:00
|
|
|
|
ret = pm_runtime_get_sync(&pdev->dev);
|
2016-09-20 23:25:40 +08:00
|
|
|
|
if (ret < 0) {
|
2016-06-25 00:50:39 +08:00
|
|
|
|
dev_err(&pdev->dev, "Failed to runtime_get device: %d\n", ret);
|
|
|
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
|
|
|
goto err_ioremap;
|
|
|
|
|
}
|
2012-09-24 07:28:26 +08:00
|
|
|
|
|
2017-03-07 22:14:49 +08:00
|
|
|
|
priv->clk = devm_clk_get(&pdev->dev, NULL);
|
2020-02-04 09:37:45 +08:00
|
|
|
|
if (PTR_ERR(priv->clk) == -EPROBE_DEFER)
|
2017-03-07 22:14:49 +08:00
|
|
|
|
return -EPROBE_DEFER;
|
|
|
|
|
if (!IS_ERR(priv->clk)) {
|
|
|
|
|
ret = clk_prepare_enable(priv->clk);
|
|
|
|
|
if (ret) {
|
|
|
|
|
dev_err(&pdev->dev,
|
|
|
|
|
"Unable to enable the clk: %d\n", ret);
|
|
|
|
|
goto err_register;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2018-02-28 22:27:23 +08:00
|
|
|
|
priv->clk_reg = devm_clk_get(&pdev->dev, "reg");
|
2020-02-04 09:37:45 +08:00
|
|
|
|
if (PTR_ERR(priv->clk_reg) == -EPROBE_DEFER)
|
2018-02-28 22:27:23 +08:00
|
|
|
|
return -EPROBE_DEFER;
|
|
|
|
|
if (!IS_ERR(priv->clk_reg)) {
|
|
|
|
|
ret = clk_prepare_enable(priv->clk_reg);
|
|
|
|
|
if (ret) {
|
|
|
|
|
dev_err(&pdev->dev,
|
|
|
|
|
"Unable to enable the register clk: %d\n",
|
|
|
|
|
ret);
|
|
|
|
|
goto err_register;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-05 22:47:23 +08:00
|
|
|
|
ret = (dev->of_node) ? of_get_omap_rng_device_details(priv, pdev) :
|
|
|
|
|
get_omap_rng_device_details(priv);
|
|
|
|
|
if (ret)
|
2016-09-16 18:08:55 +08:00
|
|
|
|
goto err_register;
|
2013-08-05 22:47:23 +08:00
|
|
|
|
|
2019-07-25 16:01:55 +08:00
|
|
|
|
ret = devm_hwrng_register(&pdev->dev, &priv->rng);
|
2008-09-04 21:07:22 +08:00
|
|
|
|
if (ret)
|
|
|
|
|
goto err_register;
|
2006-06-26 15:25:03 +08:00
|
|
|
|
|
2016-09-16 18:08:54 +08:00
|
|
|
|
dev_info(&pdev->dev, "Random Number Generator ver. %02x\n",
|
2013-08-05 22:47:23 +08:00
|
|
|
|
omap_rng_read(priv, RNG_REV_REG));
|
2006-06-26 15:25:03 +08:00
|
|
|
|
|
|
|
|
|
return 0;
|
2008-09-04 21:07:22 +08:00
|
|
|
|
|
|
|
|
|
err_register:
|
2012-09-24 07:28:26 +08:00
|
|
|
|
priv->base = NULL;
|
2016-09-16 18:08:55 +08:00
|
|
|
|
pm_runtime_put_sync(&pdev->dev);
|
2012-09-24 07:28:26 +08:00
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
2016-09-16 18:08:55 +08:00
|
|
|
|
|
2018-02-28 22:27:23 +08:00
|
|
|
|
clk_disable_unprepare(priv->clk_reg);
|
2018-02-28 22:27:22 +08:00
|
|
|
|
clk_disable_unprepare(priv->clk);
|
2008-09-04 21:07:22 +08:00
|
|
|
|
err_ioremap:
|
2013-08-05 22:47:23 +08:00
|
|
|
|
dev_err(dev, "initialization failed.\n");
|
2008-09-04 21:07:22 +08:00
|
|
|
|
return ret;
|
2006-06-26 15:25:03 +08:00
|
|
|
|
}
|
|
|
|
|
|
2015-03-10 01:36:35 +08:00
|
|
|
|
static int omap_rng_remove(struct platform_device *pdev)
|
2006-06-26 15:25:03 +08:00
|
|
|
|
{
|
2013-08-05 22:47:23 +08:00
|
|
|
|
struct omap_rng_dev *priv = platform_get_drvdata(pdev);
|
2012-09-24 07:28:26 +08:00
|
|
|
|
|
2006-06-26 15:25:03 +08:00
|
|
|
|
|
2013-08-05 22:47:23 +08:00
|
|
|
|
priv->pdata->cleanup(priv);
|
2012-09-24 07:28:26 +08:00
|
|
|
|
|
2012-09-24 07:28:26 +08:00
|
|
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
2006-06-26 15:25:03 +08:00
|
|
|
|
|
2018-02-28 22:27:22 +08:00
|
|
|
|
clk_disable_unprepare(priv->clk);
|
2018-02-28 22:27:23 +08:00
|
|
|
|
clk_disable_unprepare(priv->clk_reg);
|
2016-09-16 18:08:55 +08:00
|
|
|
|
|
2006-06-26 15:25:03 +08:00
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2015-03-12 05:08:36 +08:00
|
|
|
|
static int __maybe_unused omap_rng_suspend(struct device *dev)
|
2006-06-26 15:25:03 +08:00
|
|
|
|
{
|
2013-08-05 22:47:23 +08:00
|
|
|
|
struct omap_rng_dev *priv = dev_get_drvdata(dev);
|
2012-09-24 07:28:26 +08:00
|
|
|
|
|
2013-08-05 22:47:23 +08:00
|
|
|
|
priv->pdata->cleanup(priv);
|
2012-09-24 07:28:26 +08:00
|
|
|
|
pm_runtime_put_sync(dev);
|
2012-09-24 07:28:26 +08:00
|
|
|
|
|
2006-06-26 15:25:03 +08:00
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2015-03-12 05:08:36 +08:00
|
|
|
|
static int __maybe_unused omap_rng_resume(struct device *dev)
|
2006-06-26 15:25:03 +08:00
|
|
|
|
{
|
2013-08-05 22:47:23 +08:00
|
|
|
|
struct omap_rng_dev *priv = dev_get_drvdata(dev);
|
2016-06-25 00:50:39 +08:00
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
ret = pm_runtime_get_sync(dev);
|
2016-09-20 23:25:40 +08:00
|
|
|
|
if (ret < 0) {
|
2016-06-25 00:50:39 +08:00
|
|
|
|
dev_err(dev, "Failed to runtime_get device: %d\n", ret);
|
|
|
|
|
pm_runtime_put_noidle(dev);
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
2012-09-24 07:28:26 +08:00
|
|
|
|
|
2013-08-05 22:47:23 +08:00
|
|
|
|
priv->pdata->init(priv);
|
2012-09-24 07:28:26 +08:00
|
|
|
|
|
2006-08-06 03:14:04 +08:00
|
|
|
|
return 0;
|
2006-06-26 15:25:03 +08:00
|
|
|
|
}
|
|
|
|
|
|
2012-07-07 01:08:53 +08:00
|
|
|
|
static SIMPLE_DEV_PM_OPS(omap_rng_pm, omap_rng_suspend, omap_rng_resume);
|
2006-06-26 15:25:03 +08:00
|
|
|
|
|
2006-08-06 03:14:04 +08:00
|
|
|
|
static struct platform_driver omap_rng_driver = {
|
|
|
|
|
.driver = {
|
|
|
|
|
.name = "omap_rng",
|
2015-03-12 05:08:36 +08:00
|
|
|
|
.pm = &omap_rng_pm,
|
2013-08-05 22:47:21 +08:00
|
|
|
|
.of_match_table = of_match_ptr(omap_rng_of_match),
|
2006-08-06 03:14:04 +08:00
|
|
|
|
},
|
2006-06-26 15:25:03 +08:00
|
|
|
|
.probe = omap_rng_probe,
|
2015-03-10 01:36:35 +08:00
|
|
|
|
.remove = omap_rng_remove,
|
2006-06-26 15:25:03 +08:00
|
|
|
|
};
|
|
|
|
|
|
2013-08-05 22:47:18 +08:00
|
|
|
|
module_platform_driver(omap_rng_driver);
|
|
|
|
|
MODULE_ALIAS("platform:omap_rng");
|
2006-06-26 15:25:03 +08:00
|
|
|
|
MODULE_AUTHOR("Deepak Saxena (and others)");
|
|
|
|
|
MODULE_LICENSE("GPL");
|