2011-06-21 01:47:27 +08:00
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/*
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* This file contains driver for the Xilinx PS Timer Counter IP.
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*
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* Copyright (C) 2011 Xilinx
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*
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* based on arch/mips/kernel/time.c timer driver
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/interrupt.h>
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#include <linux/clockchips.h>
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2012-11-01 03:56:14 +08:00
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/slab.h>
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#include <linux/clk-provider.h>
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2011-06-21 01:47:27 +08:00
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#include "common.h"
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/*
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* Timer Register Offset Definitions of Timer 1, Increment base address by 4
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* and use same offsets for Timer 2
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*/
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2012-12-20 02:18:39 +08:00
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#define XTTCPS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
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#define XTTCPS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
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#define XTTCPS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
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2012-12-20 02:18:36 +08:00
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#define XTTCPS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
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#define XTTCPS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
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#define XTTCPS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
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#define XTTCPS_CNT_CNTRL_DISABLE_MASK 0x1
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2011-06-21 01:47:27 +08:00
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2012-12-20 02:18:41 +08:00
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/*
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* Setup the timers to use pre-scaling, using a fixed value for now that will
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2012-11-01 03:56:14 +08:00
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* work across most input frequency, but it may need to be more dynamic
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*/
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#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
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#define PRESCALE 2048 /* The exponent must match this */
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#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
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#define CLK_CNTRL_PRESCALE_EN 1
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#define CNT_CNTRL_RESET (1<<4)
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2011-06-21 01:47:27 +08:00
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/**
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2012-12-20 02:18:36 +08:00
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* struct xttcps_timer - This definition defines local timer structure
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2011-06-21 01:47:27 +08:00
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*
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* @base_addr: Base address of timer
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**/
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2012-12-20 02:18:36 +08:00
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struct xttcps_timer {
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2012-11-01 03:56:14 +08:00
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void __iomem *base_addr;
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};
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2012-12-20 02:18:36 +08:00
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struct xttcps_timer_clocksource {
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struct xttcps_timer xttc;
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2012-11-01 03:56:14 +08:00
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struct clocksource cs;
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2011-06-21 01:47:27 +08:00
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};
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2012-12-20 02:18:36 +08:00
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#define to_xttcps_timer_clksrc(x) \
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container_of(x, struct xttcps_timer_clocksource, cs)
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2012-11-01 03:56:14 +08:00
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2012-12-20 02:18:36 +08:00
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struct xttcps_timer_clockevent {
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struct xttcps_timer xttc;
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2012-11-01 03:56:14 +08:00
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struct clock_event_device ce;
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struct clk *clk;
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};
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2012-12-20 02:18:36 +08:00
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#define to_xttcps_timer_clkevent(x) \
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container_of(x, struct xttcps_timer_clockevent, ce)
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2011-06-21 01:47:27 +08:00
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/**
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2012-12-20 02:18:36 +08:00
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* xttcps_set_interval - Set the timer interval value
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2011-06-21 01:47:27 +08:00
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*
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* @timer: Pointer to the timer instance
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* @cycles: Timer interval ticks
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**/
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2012-12-20 02:18:36 +08:00
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static void xttcps_set_interval(struct xttcps_timer *timer,
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2011-06-21 01:47:27 +08:00
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unsigned long cycles)
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{
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u32 ctrl_reg;
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/* Disable the counter, set the counter value and re-enable counter */
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2012-12-20 02:18:36 +08:00
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ctrl_reg = __raw_readl(timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
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ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
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__raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
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2011-06-21 01:47:27 +08:00
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2012-12-20 02:18:36 +08:00
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__raw_writel(cycles, timer->base_addr + XTTCPS_INTR_VAL_OFFSET);
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2011-06-21 01:47:27 +08:00
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2012-12-20 02:18:41 +08:00
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/*
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* Reset the counter (0x10) so that it starts from 0, one-shot
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* mode makes this needed for timing to be right.
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*/
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2012-11-01 03:56:14 +08:00
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ctrl_reg |= CNT_CNTRL_RESET;
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2012-12-20 02:18:36 +08:00
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ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
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__raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
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2011-06-21 01:47:27 +08:00
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}
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/**
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2012-12-20 02:18:36 +08:00
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* xttcps_clock_event_interrupt - Clock event timer interrupt handler
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2011-06-21 01:47:27 +08:00
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*
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* @irq: IRQ number of the Timer
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2012-12-20 02:18:36 +08:00
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* @dev_id: void pointer to the xttcps_timer instance
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2011-06-21 01:47:27 +08:00
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*
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* returns: Always IRQ_HANDLED - success
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**/
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2012-12-20 02:18:36 +08:00
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static irqreturn_t xttcps_clock_event_interrupt(int irq, void *dev_id)
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2011-06-21 01:47:27 +08:00
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{
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2012-12-20 02:18:36 +08:00
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struct xttcps_timer_clockevent *xttce = dev_id;
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struct xttcps_timer *timer = &xttce->xttc;
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2011-06-21 01:47:27 +08:00
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/* Acknowledge the interrupt and call event handler */
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2012-12-20 02:18:37 +08:00
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__raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET);
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2011-06-21 01:47:27 +08:00
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2012-11-01 03:56:14 +08:00
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xttce->ce.event_handler(&xttce->ce);
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2011-06-21 01:47:27 +08:00
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return IRQ_HANDLED;
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}
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/**
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2012-11-01 03:56:14 +08:00
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* __xttc_clocksource_read - Reads the timer counter register
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2011-06-21 01:47:27 +08:00
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*
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* returns: Current timer counter register value
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**/
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2012-11-01 03:56:14 +08:00
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static cycle_t __xttc_clocksource_read(struct clocksource *cs)
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2011-06-21 01:47:27 +08:00
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{
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2012-12-20 02:18:36 +08:00
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struct xttcps_timer *timer = &to_xttcps_timer_clksrc(cs)->xttc;
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2011-06-21 01:47:27 +08:00
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return (cycle_t)__raw_readl(timer->base_addr +
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2012-12-20 02:18:36 +08:00
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XTTCPS_COUNT_VAL_OFFSET);
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2011-06-21 01:47:27 +08:00
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}
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/**
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2012-12-20 02:18:36 +08:00
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* xttcps_set_next_event - Sets the time interval for next event
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2011-06-21 01:47:27 +08:00
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*
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* @cycles: Timer interval ticks
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* @evt: Address of clock event instance
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*
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* returns: Always 0 - success
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**/
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2012-12-20 02:18:36 +08:00
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static int xttcps_set_next_event(unsigned long cycles,
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2011-06-21 01:47:27 +08:00
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struct clock_event_device *evt)
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{
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2012-12-20 02:18:36 +08:00
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struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
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struct xttcps_timer *timer = &xttce->xttc;
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2011-06-21 01:47:27 +08:00
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2012-12-20 02:18:36 +08:00
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xttcps_set_interval(timer, cycles);
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2011-06-21 01:47:27 +08:00
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return 0;
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}
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/**
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2012-12-20 02:18:36 +08:00
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* xttcps_set_mode - Sets the mode of timer
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2011-06-21 01:47:27 +08:00
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*
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* @mode: Mode to be set
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* @evt: Address of clock event instance
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**/
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2012-12-20 02:18:36 +08:00
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static void xttcps_set_mode(enum clock_event_mode mode,
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2011-06-21 01:47:27 +08:00
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struct clock_event_device *evt)
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{
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2012-12-20 02:18:36 +08:00
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struct xttcps_timer_clockevent *xttce = to_xttcps_timer_clkevent(evt);
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struct xttcps_timer *timer = &xttce->xttc;
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2011-06-21 01:47:27 +08:00
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u32 ctrl_reg;
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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2012-12-20 02:18:36 +08:00
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xttcps_set_interval(timer,
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2012-11-01 03:56:14 +08:00
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DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk),
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PRESCALE * HZ));
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2011-06-21 01:47:27 +08:00
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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ctrl_reg = __raw_readl(timer->base_addr +
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2012-12-20 02:18:36 +08:00
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XTTCPS_CNT_CNTRL_OFFSET);
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ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
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2011-06-21 01:47:27 +08:00
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__raw_writel(ctrl_reg,
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2012-12-20 02:18:36 +08:00
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timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
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2011-06-21 01:47:27 +08:00
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break;
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case CLOCK_EVT_MODE_RESUME:
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ctrl_reg = __raw_readl(timer->base_addr +
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2012-12-20 02:18:36 +08:00
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XTTCPS_CNT_CNTRL_OFFSET);
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ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
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2011-06-21 01:47:27 +08:00
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__raw_writel(ctrl_reg,
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2012-12-20 02:18:36 +08:00
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timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
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2011-06-21 01:47:27 +08:00
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break;
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}
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}
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2012-11-01 03:56:14 +08:00
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static void __init zynq_ttc_setup_clocksource(struct device_node *np,
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void __iomem *base)
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{
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2012-12-20 02:18:36 +08:00
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struct xttcps_timer_clocksource *ttccs;
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2012-11-01 03:56:14 +08:00
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struct clk *clk;
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int err;
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u32 reg;
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ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
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if (WARN_ON(!ttccs))
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return;
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err = of_property_read_u32(np, "reg", ®);
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if (WARN_ON(err))
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return;
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clk = of_clk_get_by_name(np, "cpu_1x");
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if (WARN_ON(IS_ERR(clk)))
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return;
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err = clk_prepare_enable(clk);
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if (WARN_ON(err))
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return;
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ttccs->xttc.base_addr = base + reg * 4;
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ttccs->cs.name = np->name;
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ttccs->cs.rating = 200;
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ttccs->cs.read = __xttc_clocksource_read;
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ttccs->cs.mask = CLOCKSOURCE_MASK(16);
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ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
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2012-12-20 02:18:36 +08:00
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__raw_writel(0x0, ttccs->xttc.base_addr + XTTCPS_IER_OFFSET);
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2012-11-01 03:56:14 +08:00
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__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
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2012-12-20 02:18:36 +08:00
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ttccs->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
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2012-11-01 03:56:14 +08:00
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__raw_writel(CNT_CNTRL_RESET,
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2012-12-20 02:18:36 +08:00
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ttccs->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
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2012-11-01 03:56:14 +08:00
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err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE);
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if (WARN_ON(err))
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return;
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}
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static void __init zynq_ttc_setup_clockevent(struct device_node *np,
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void __iomem *base)
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{
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2012-12-20 02:18:36 +08:00
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struct xttcps_timer_clockevent *ttcce;
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2012-11-01 03:56:14 +08:00
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int err, irq;
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u32 reg;
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ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
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if (WARN_ON(!ttcce))
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return;
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err = of_property_read_u32(np, "reg", ®);
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if (WARN_ON(err))
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return;
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ttcce->xttc.base_addr = base + reg * 4;
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ttcce->clk = of_clk_get_by_name(np, "cpu_1x");
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if (WARN_ON(IS_ERR(ttcce->clk)))
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return;
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err = clk_prepare_enable(ttcce->clk);
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if (WARN_ON(err))
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return;
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irq = irq_of_parse_and_map(np, 0);
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if (WARN_ON(!irq))
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return;
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ttcce->ce.name = np->name;
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ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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2012-12-20 02:18:36 +08:00
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ttcce->ce.set_next_event = xttcps_set_next_event;
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ttcce->ce.set_mode = xttcps_set_mode;
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2012-11-01 03:56:14 +08:00
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ttcce->ce.rating = 200;
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ttcce->ce.irq = irq;
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2012-12-20 02:18:42 +08:00
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ttcce->ce.cpumask = cpu_possible_mask;
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2012-11-01 03:56:14 +08:00
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2012-12-20 02:18:36 +08:00
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__raw_writel(0x23, ttcce->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
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2012-11-01 03:56:14 +08:00
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__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
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2012-12-20 02:18:36 +08:00
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ttcce->xttc.base_addr + XTTCPS_CLK_CNTRL_OFFSET);
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__raw_writel(0x1, ttcce->xttc.base_addr + XTTCPS_IER_OFFSET);
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2012-11-01 03:56:14 +08:00
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2012-12-20 02:18:36 +08:00
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err = request_irq(irq, xttcps_clock_event_interrupt, IRQF_TIMER,
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2012-11-01 03:56:14 +08:00
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np->name, ttcce);
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if (WARN_ON(err))
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return;
|
|
|
|
|
|
|
|
clockevents_config_and_register(&ttcce->ce,
|
|
|
|
clk_get_rate(ttcce->clk) / PRESCALE,
|
|
|
|
1, 0xfffe);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const __initconst struct of_device_id zynq_ttc_match[] = {
|
|
|
|
{ .compatible = "xlnx,ttc-counter-clocksource",
|
|
|
|
.data = zynq_ttc_setup_clocksource, },
|
|
|
|
{ .compatible = "xlnx,ttc-counter-clockevent",
|
|
|
|
.data = zynq_ttc_setup_clockevent, },
|
|
|
|
{}
|
2011-06-21 01:47:27 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
2012-12-20 02:18:36 +08:00
|
|
|
* xttcps_timer_init - Initialize the timer
|
2011-06-21 01:47:27 +08:00
|
|
|
*
|
|
|
|
* Initializes the timer hardware and register the clock source and clock event
|
|
|
|
* timers with Linux kernal timer framework
|
|
|
|
**/
|
2012-12-20 02:18:36 +08:00
|
|
|
void __init xttcps_timer_init(void)
|
2011-06-21 01:47:27 +08:00
|
|
|
{
|
2012-11-01 03:56:14 +08:00
|
|
|
struct device_node *np;
|
|
|
|
|
|
|
|
for_each_compatible_node(np, NULL, "xlnx,ttc") {
|
|
|
|
struct device_node *np_chld;
|
|
|
|
void __iomem *base;
|
|
|
|
|
|
|
|
base = of_iomap(np, 0);
|
|
|
|
if (WARN_ON(!base))
|
|
|
|
return;
|
|
|
|
|
|
|
|
for_each_available_child_of_node(np, np_chld) {
|
|
|
|
int (*cb)(struct device_node *np, void __iomem *base);
|
|
|
|
const struct of_device_id *match;
|
|
|
|
|
|
|
|
match = of_match_node(zynq_ttc_match, np_chld);
|
|
|
|
if (match) {
|
|
|
|
cb = match->data;
|
|
|
|
cb(np_chld, base);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2011-06-21 01:47:27 +08:00
|
|
|
}
|