2009-04-23 17:22:13 +08:00
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/*
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*
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* arch/arm/mach-u300/core.c
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*
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*
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2012-08-13 16:11:15 +08:00
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* Copyright (C) 2007-2012 ST-Ericsson SA
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2009-04-23 17:22:13 +08:00
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* License terms: GNU General Public License (GPL) version 2
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* Core platform support, IRQ handling and device definitions.
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* Author: Linus Walleij <linus.walleij@stericsson.com>
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*/
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#include <linux/kernel.h>
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2011-05-03 02:54:38 +08:00
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#include <linux/pinctrl/machine.h>
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2012-01-21 00:53:15 +08:00
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#include <linux/pinctrl/pinconf-generic.h>
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2012-06-20 05:44:25 +08:00
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#include <linux/platform_data/clk-u300.h>
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2013-04-08 17:38:50 +08:00
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#include <linux/irqchip.h>
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2013-05-22 22:15:13 +08:00
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#include <linux/of_address.h>
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2013-04-08 17:38:50 +08:00
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#include <linux/of_platform.h>
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#include <linux/clocksource.h>
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2013-04-22 17:29:30 +08:00
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#include <linux/clk.h>
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2009-04-23 17:22:13 +08:00
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#include <asm/mach/map.h>
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2012-08-13 17:35:55 +08:00
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#include <asm/mach/arch.h>
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2009-04-23 17:22:13 +08:00
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2013-05-22 22:20:27 +08:00
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/*
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* These are the large blocks of memory allocated for I/O.
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* the defines are used for setting up the I/O memory mapping.
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*/
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/* NAND Flash CS0 */
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#define U300_NAND_CS0_PHYS_BASE 0x80000000
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/* NFIF */
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#define U300_NAND_IF_PHYS_BASE 0x9f800000
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/* ALE, CLE offset for FSMC NAND */
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#define PLAT_NAND_CLE (1 << 16)
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#define PLAT_NAND_ALE (1 << 17)
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/* AHB Peripherals */
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#define U300_AHB_PER_PHYS_BASE 0xa0000000
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#define U300_AHB_PER_VIRT_BASE 0xff010000
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/* FAST Peripherals */
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#define U300_FAST_PER_PHYS_BASE 0xc0000000
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#define U300_FAST_PER_VIRT_BASE 0xff020000
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/* SLOW Peripherals */
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#define U300_SLOW_PER_PHYS_BASE 0xc0010000
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#define U300_SLOW_PER_VIRT_BASE 0xff000000
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/* Boot ROM */
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#define U300_BOOTROM_PHYS_BASE 0xffff0000
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#define U300_BOOTROM_VIRT_BASE 0xffff0000
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/* SEMI config base */
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#define U300_SEMI_CONFIG_BASE 0x2FFE0000
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/*
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* AHB peripherals
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*/
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/* AHB Peripherals Bridge Controller */
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#define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000)
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/* Vectored Interrupt Controller 0, servicing 32 interrupts */
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#define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000)
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#define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
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/* Vectored Interrupt Controller 1, servicing 32 interrupts */
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#define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000)
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#define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
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/* Memory Stick Pro (MSPRO) controller */
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#define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000)
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/* EMIF Configuration Area */
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#define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000)
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/*
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* FAST peripherals
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*/
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/* FAST bridge control */
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#define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000)
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/* MMC/SD controller */
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#define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000)
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/* PCM I2S0 controller */
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#define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000)
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/* PCM I2S1 controller */
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#define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000)
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/* I2C0 controller */
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#define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000)
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/* I2C1 controller */
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#define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000)
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/* SPI controller */
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#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000)
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/* Fast UART1 on U335 only */
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#define U300_UART1_BASE (U300_FAST_PER_PHYS_BASE+0x7000)
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/*
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* SLOW peripherals
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*/
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/* SLOW bridge control */
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#define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE)
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/* SYSCON */
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#define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000)
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#define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
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/* Watchdog */
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#define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000)
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/* UART0 */
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#define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000)
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/* APP side special timer */
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#define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000)
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#define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
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/* Keypad */
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#define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000)
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/* GPIO */
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#define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000)
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/* RTC */
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#define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
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/* Bus tracer */
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#define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000)
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/* Event handler (hardware queue) */
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#define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000)
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/* Genric Timer */
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#define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000)
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/* PPM */
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#define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000)
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/*
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* REST peripherals
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*/
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/* ISP (image signal processor) */
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#define U300_ISP_BASE (0xA0008000)
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/* DMA Controller base */
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#define U300_DMAC_BASE (0xC0020000)
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/* MSL Base */
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#define U300_MSL_BASE (0xc0022000)
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/* APEX Base */
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#define U300_APEX_BASE (0xc0030000)
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/* Video Encoder Base */
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#define U300_VIDEOENC_BASE (0xc0080000)
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/* XGAM Base */
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#define U300_XGAM_BASE (0xd0000000)
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2013-05-02 22:56:15 +08:00
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/*
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* SYSCON addresses applicable to the core machine.
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*/
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/* Chip ID register 16bit (R/-) */
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#define U300_SYSCON_CIDR (0x400)
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/* SMCR */
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#define U300_SYSCON_SMCR (0x4d0)
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#define U300_SYSCON_SMCR_FIELD_MASK (0x000e)
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#define U300_SYSCON_SMCR_SEMI_SREFACK_IND (0x0008)
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#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE (0x0004)
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#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE (0x0002)
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/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
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#define U300_SYSCON_CSDR (0x4f0)
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#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE (0x0001)
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/* PRINT_CONTROL Print Control 16bit (R/-) */
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#define U300_SYSCON_PCR (0x4f8)
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#define U300_SYSCON_PCR_SERV_IND (0x0001)
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/* BOOT_CONTROL 16bit (R/-) */
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#define U300_SYSCON_BCR (0x4fc)
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#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND (0x0400)
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#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND (0x0200)
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#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC)
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#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003)
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2009-04-23 17:22:13 +08:00
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2013-05-22 22:15:13 +08:00
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static void __iomem *syscon_base;
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2009-04-23 17:22:13 +08:00
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/*
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* Static I/O mappings that are needed for booting the U300 platforms. The
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* only things we need are the areas where we find the timer, syscon and
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* intcon, since the remaining device drivers will map their own memory
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* physical to virtual as the need arise.
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*/
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static struct map_desc u300_io_desc[] __initdata = {
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{
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.virtual = U300_SLOW_PER_VIRT_BASE,
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.pfn = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
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.length = SZ_64K,
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.type = MT_DEVICE,
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},
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{
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.virtual = U300_AHB_PER_VIRT_BASE,
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.pfn = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
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.length = SZ_32K,
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.type = MT_DEVICE,
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},
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{
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.virtual = U300_FAST_PER_VIRT_BASE,
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.pfn = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
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.length = SZ_32K,
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.type = MT_DEVICE,
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},
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};
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2012-08-13 17:35:55 +08:00
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static void __init u300_map_io(void)
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2009-04-23 17:22:13 +08:00
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{
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iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
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}
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2012-01-21 00:53:15 +08:00
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static unsigned long pin_pullup_conf[] = {
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PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
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};
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static unsigned long pin_highz_conf[] = {
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PIN_CONF_PACKED(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0),
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};
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/* Pin control settings */
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2012-02-09 14:23:28 +08:00
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static struct pinctrl_map __initdata u300_pinmux_map[] = {
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2011-05-03 02:54:38 +08:00
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/* anonymous maps for chip power and EMIFs */
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2012-03-03 04:05:48 +08:00
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PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "power"),
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PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif0"),
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PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-u300", NULL, "emif1"),
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2011-05-03 02:54:38 +08:00
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/* per-device maps for MMC/SD, SPI and UART */
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2012-03-03 04:05:48 +08:00
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PIN_MAP_MUX_GROUP_DEFAULT("mmci", "pinctrl-u300", NULL, "mmc0"),
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PIN_MAP_MUX_GROUP_DEFAULT("pl022", "pinctrl-u300", NULL, "spi0"),
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PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-u300", NULL, "uart0"),
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2012-01-21 00:53:15 +08:00
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/* This pin is used for clock return rather than GPIO */
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PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO APP GPIO 11",
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pin_pullup_conf),
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/* This pin is used for card detect */
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PIN_MAP_CONFIGS_PIN_DEFAULT("mmci", "pinctrl-u300", "PIO MS INS",
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pin_highz_conf),
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2011-05-03 02:54:38 +08:00
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};
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2009-04-23 17:22:13 +08:00
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struct db_chip {
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u16 chipid;
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const char *name;
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};
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/*
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* This is a list of the Digital Baseband chips used in the U300 platform.
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*/
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static struct db_chip db_chips[] __initdata = {
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{
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.chipid = 0xb800,
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.name = "DB3000",
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},
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{
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.chipid = 0xc000,
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.name = "DB3100",
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},
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{
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.chipid = 0xc800,
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.name = "DB3150",
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},
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{
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.chipid = 0xd800,
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.name = "DB3200",
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},
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{
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.chipid = 0xe000,
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.name = "DB3250",
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},
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{
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.chipid = 0xe800,
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.name = "DB3210",
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},
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{
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.chipid = 0xf000,
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.name = "DB3350 P1x",
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},
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{
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.chipid = 0xf100,
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.name = "DB3350 P2x",
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},
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{
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.chipid = 0x0000, /* List terminator */
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.name = NULL,
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}
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};
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2009-08-14 04:57:22 +08:00
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static void __init u300_init_check_chip(void)
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2009-04-23 17:22:13 +08:00
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{
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u16 val;
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struct db_chip *chip;
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const char *chipname;
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const char unknown[] = "UNKNOWN";
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/* Read out and print chip ID */
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2013-05-22 22:15:13 +08:00
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val = readw(syscon_base + U300_SYSCON_CIDR);
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2009-04-23 17:22:13 +08:00
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/* This is in funky bigendian order... */
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val = (val & 0xFFU) << 8 | (val >> 8);
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chip = db_chips;
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chipname = unknown;
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for ( ; chip->chipid; chip++) {
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if (chip->chipid == (val & 0xFF00U)) {
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chipname = chip->name;
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break;
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}
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}
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printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
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"(chip ID 0x%04x)\n", chipname, val);
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if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
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2010-08-13 17:31:59 +08:00
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printk(KERN_ERR "Platform configured for BS335 " \
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2009-04-23 17:22:13 +08:00
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" with DB3350 but %s detected, expect problems!",
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chipname);
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}
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}
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2011-11-05 23:51:25 +08:00
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/* Forward declare this function from the watchdog */
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void coh901327_watchdog_reset(void);
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2013-07-09 07:01:40 +08:00
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static void u300_restart(enum reboot_mode mode, const char *cmd)
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2011-11-05 23:51:25 +08:00
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{
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switch (mode) {
|
2013-07-09 07:01:40 +08:00
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case REBOOT_SOFT:
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case REBOOT_HARD:
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2011-11-05 23:51:25 +08:00
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#ifdef CONFIG_COH901327_WATCHDOG
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coh901327_watchdog_reset();
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#endif
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break;
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default:
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|
|
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/* Do nothing */
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break;
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}
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/* Wait for system do die/reset. */
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while (1);
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}
|
2012-08-13 17:35:55 +08:00
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2013-04-08 17:38:50 +08:00
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/* These are mostly to get the right device names for the clock lookups */
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static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
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OF_DEV_AUXDATA("stericsson,pinctrl-u300", U300_SYSCON_BASE,
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"pinctrl-u300", NULL),
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OF_DEV_AUXDATA("stericsson,gpio-coh901", U300_GPIO_BASE,
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2013-05-24 02:09:43 +08:00
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|
"u300-gpio", NULL),
|
2013-04-19 18:59:59 +08:00
|
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|
OF_DEV_AUXDATA("stericsson,coh901327", U300_WDOG_BASE,
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|
"coh901327_wdog", NULL),
|
2013-04-19 19:22:57 +08:00
|
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|
OF_DEV_AUXDATA("stericsson,coh901331", U300_RTC_BASE,
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|
|
|
"rtc-coh901331", NULL),
|
2013-04-19 19:44:25 +08:00
|
|
|
OF_DEV_AUXDATA("stericsson,coh901318", U300_DMAC_BASE,
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|
|
|
"coh901318", NULL),
|
2013-04-22 17:00:02 +08:00
|
|
|
OF_DEV_AUXDATA("stericsson,fsmc-nand", U300_NAND_IF_PHYS_BASE,
|
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|
|
"fsmc-nand", NULL),
|
2013-04-08 17:38:50 +08:00
|
|
|
OF_DEV_AUXDATA("arm,primecell", U300_UART0_BASE,
|
2013-04-22 17:29:30 +08:00
|
|
|
"uart0", NULL),
|
2013-04-08 17:38:50 +08:00
|
|
|
OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE,
|
2013-04-22 17:29:30 +08:00
|
|
|
"uart1", NULL),
|
2013-04-19 20:56:46 +08:00
|
|
|
OF_DEV_AUXDATA("arm,primecell", U300_SPI_BASE,
|
2013-04-22 17:29:30 +08:00
|
|
|
"pl022", NULL),
|
2013-04-11 21:13:39 +08:00
|
|
|
OF_DEV_AUXDATA("st,ddci2c", U300_I2C0_BASE,
|
|
|
|
"stu300.0", NULL),
|
|
|
|
OF_DEV_AUXDATA("st,ddci2c", U300_I2C1_BASE,
|
|
|
|
"stu300.1", NULL),
|
2013-04-08 17:38:50 +08:00
|
|
|
OF_DEV_AUXDATA("arm,primecell", U300_MMCSD_BASE,
|
2013-04-22 17:29:30 +08:00
|
|
|
"mmci", NULL),
|
2013-04-08 17:38:50 +08:00
|
|
|
{ /* sentinel */ },
|
|
|
|
};
|
|
|
|
|
|
|
|
static void __init u300_init_irq_dt(void)
|
|
|
|
{
|
2013-05-22 22:15:13 +08:00
|
|
|
struct device_node *syscon;
|
2013-04-08 17:38:50 +08:00
|
|
|
struct clk *clk;
|
|
|
|
|
2013-05-22 22:15:13 +08:00
|
|
|
syscon = of_find_node_by_path("/syscon@c0011000");
|
|
|
|
if (!syscon) {
|
|
|
|
pr_crit("could not find syscon node\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
syscon_base = of_iomap(syscon, 0);
|
|
|
|
if (!syscon_base) {
|
|
|
|
pr_crit("could not remap syscon\n");
|
|
|
|
return;
|
|
|
|
}
|
2013-04-08 17:38:50 +08:00
|
|
|
/* initialize clocking early, we want to clock the INTCON */
|
2013-05-22 22:15:13 +08:00
|
|
|
u300_clk_init(syscon_base);
|
2013-04-08 17:38:50 +08:00
|
|
|
|
|
|
|
/* Bootstrap EMIF and SEMI clocks */
|
|
|
|
clk = clk_get_sys("pl172", NULL);
|
|
|
|
BUG_ON(IS_ERR(clk));
|
|
|
|
clk_prepare_enable(clk);
|
|
|
|
clk = clk_get_sys("semi", NULL);
|
|
|
|
BUG_ON(IS_ERR(clk));
|
|
|
|
clk_prepare_enable(clk);
|
|
|
|
|
|
|
|
/* Clock the interrupt controller */
|
|
|
|
clk = clk_get_sys("intcon", NULL);
|
|
|
|
BUG_ON(IS_ERR(clk));
|
|
|
|
clk_prepare_enable(clk);
|
|
|
|
|
|
|
|
irqchip_init();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __init u300_init_machine_dt(void)
|
|
|
|
{
|
|
|
|
u16 val;
|
|
|
|
|
|
|
|
/* Check what platform we run and print some status information */
|
|
|
|
u300_init_check_chip();
|
|
|
|
|
|
|
|
/* Initialize pinmuxing */
|
|
|
|
pinctrl_register_mappings(u300_pinmux_map,
|
|
|
|
ARRAY_SIZE(u300_pinmux_map));
|
|
|
|
|
|
|
|
of_platform_populate(NULL, of_default_bus_match_table,
|
|
|
|
u300_auxdata_lookup, NULL);
|
|
|
|
|
|
|
|
/* Enable SEMI self refresh */
|
2013-05-22 22:15:13 +08:00
|
|
|
val = readw(syscon_base + U300_SYSCON_SMCR) |
|
2013-04-08 17:38:50 +08:00
|
|
|
U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
|
2013-05-22 22:15:13 +08:00
|
|
|
writew(val, syscon_base + U300_SYSCON_SMCR);
|
2013-04-08 17:38:50 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static const char * u300_board_compat[] = {
|
|
|
|
"stericsson,u300",
|
|
|
|
NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
DT_MACHINE_START(U300_DT, "U300 S335/B335 (Device Tree)")
|
|
|
|
.map_io = u300_map_io,
|
|
|
|
.init_irq = u300_init_irq_dt,
|
2015-09-28 22:49:18 +08:00
|
|
|
.init_time = clocksource_probe,
|
2013-04-08 17:38:50 +08:00
|
|
|
.init_machine = u300_init_machine_dt,
|
|
|
|
.restart = u300_restart,
|
|
|
|
.dt_compat = u300_board_compat,
|
|
|
|
MACHINE_END
|