2019-03-04 14:29:55 +08:00
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/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef NVD_H
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#define NVD_H
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/**
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* Navi's PM4 definitions
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*/
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#define PACKET_TYPE0 0
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#define PACKET_TYPE1 1
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#define PACKET_TYPE2 2
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#define PACKET_TYPE3 3
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#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
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#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
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#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)
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#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
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#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
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((reg) & 0xFFFF) | \
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((n) & 0x3FFF) << 16)
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#define CP_PACKET2 0x80000000
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#define PACKET2_PAD_SHIFT 0
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#define PACKET2_PAD_MASK (0x3fffffff << 0)
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#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
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#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
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(((op) & 0xFF) << 8) | \
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((n) & 0x3FFF) << 16)
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#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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/* Packet 3 types */
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#define PACKET3_NOP 0x10
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#define PACKET3_SET_BASE 0x11
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#define PACKET3_BASE_INDEX(x) ((x) << 0)
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#define CE_PARTITION_BASE 3
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#define PACKET3_CLEAR_STATE 0x12
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#define PACKET3_INDEX_BUFFER_SIZE 0x13
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#define PACKET3_DISPATCH_DIRECT 0x15
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#define PACKET3_DISPATCH_INDIRECT 0x16
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#define PACKET3_INDIRECT_BUFFER_END 0x17
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#define PACKET3_INDIRECT_BUFFER_CNST_END 0x19
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#define PACKET3_ATOMIC_GDS 0x1D
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#define PACKET3_ATOMIC_MEM 0x1E
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#define PACKET3_OCCLUSION_QUERY 0x1F
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#define PACKET3_SET_PREDICATION 0x20
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#define PACKET3_REG_RMW 0x21
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#define PACKET3_COND_EXEC 0x22
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#define PACKET3_PRED_EXEC 0x23
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#define PACKET3_DRAW_INDIRECT 0x24
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#define PACKET3_DRAW_INDEX_INDIRECT 0x25
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#define PACKET3_INDEX_BASE 0x26
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#define PACKET3_DRAW_INDEX_2 0x27
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#define PACKET3_CONTEXT_CONTROL 0x28
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#define PACKET3_INDEX_TYPE 0x2A
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#define PACKET3_DRAW_INDIRECT_MULTI 0x2C
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#define PACKET3_DRAW_INDEX_AUTO 0x2D
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#define PACKET3_NUM_INSTANCES 0x2F
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#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
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#define PACKET3_INDIRECT_BUFFER_PRIV 0x32
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#define PACKET3_INDIRECT_BUFFER_CNST 0x33
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#define PACKET3_COND_INDIRECT_BUFFER_CNST 0x33
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#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
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#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
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#define PACKET3_DRAW_PREAMBLE 0x36
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#define PACKET3_WRITE_DATA 0x37
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#define WRITE_DATA_DST_SEL(x) ((x) << 8)
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/* 0 - register
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* 1 - memory (sync - via GRBM)
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* 2 - gl2
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* 3 - gds
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* 4 - reserved
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* 5 - memory (async - direct)
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*/
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#define WR_ONE_ADDR (1 << 16)
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#define WR_CONFIRM (1 << 20)
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#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)
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/* 0 - LRU
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* 1 - Stream
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*/
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#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
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/* 0 - me
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* 1 - pfp
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* 2 - ce
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*/
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#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
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#define PACKET3_MEM_SEMAPHORE 0x39
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# define PACKET3_SEM_USE_MAILBOX (0x1 << 16)
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# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */
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# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
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# define PACKET3_SEM_SEL_WAIT (0x7 << 29)
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#define PACKET3_DRAW_INDEX_MULTI_INST 0x3A
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#define PACKET3_COPY_DW 0x3B
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#define PACKET3_WAIT_REG_MEM 0x3C
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#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
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/* 0 - always
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* 1 - <
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* 2 - <=
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* 3 - ==
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* 4 - !=
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* 5 - >=
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* 6 - >
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*/
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#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
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/* 0 - reg
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* 1 - mem
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*/
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#define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
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/* 0 - wait_reg_mem
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* 1 - wr_wait_wr_reg
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*/
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#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
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/* 0 - me
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* 1 - pfp
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*/
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#define PACKET3_INDIRECT_BUFFER 0x3F
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#define INDIRECT_BUFFER_VALID (1 << 23)
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#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)
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/* 0 - LRU
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* 1 - Stream
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* 2 - Bypass
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*/
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#define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21)
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#define INDIRECT_BUFFER_PRE_RESUME(x) ((x) << 30)
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#define PACKET3_COND_INDIRECT_BUFFER 0x3F
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#define PACKET3_COPY_DATA 0x40
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#define PACKET3_CP_DMA 0x41
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#define PACKET3_PFP_SYNC_ME 0x42
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#define PACKET3_SURFACE_SYNC 0x43
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#define PACKET3_ME_INITIALIZE 0x44
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#define PACKET3_COND_WRITE 0x45
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#define PACKET3_EVENT_WRITE 0x46
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#define EVENT_TYPE(x) ((x) << 0)
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#define EVENT_INDEX(x) ((x) << 8)
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/* 0 - any non-TS event
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* 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
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* 2 - SAMPLE_PIPELINESTAT
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* 3 - SAMPLE_STREAMOUTSTAT*
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* 4 - *S_PARTIAL_FLUSH
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*/
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#define PACKET3_EVENT_WRITE_EOP 0x47
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#define PACKET3_EVENT_WRITE_EOS 0x48
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#define PACKET3_RELEASE_MEM 0x49
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#define PACKET3_RELEASE_MEM_EVENT_TYPE(x) ((x) << 0)
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#define PACKET3_RELEASE_MEM_EVENT_INDEX(x) ((x) << 8)
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#define PACKET3_RELEASE_MEM_GCR_GLM_WB (1 << 12)
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#define PACKET3_RELEASE_MEM_GCR_GLM_INV (1 << 13)
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#define PACKET3_RELEASE_MEM_GCR_GLV_INV (1 << 14)
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#define PACKET3_RELEASE_MEM_GCR_GL1_INV (1 << 15)
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#define PACKET3_RELEASE_MEM_GCR_GL2_US (1 << 16)
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#define PACKET3_RELEASE_MEM_GCR_GL2_RANGE (1 << 17)
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#define PACKET3_RELEASE_MEM_GCR_GL2_DISCARD (1 << 19)
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#define PACKET3_RELEASE_MEM_GCR_GL2_INV (1 << 20)
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#define PACKET3_RELEASE_MEM_GCR_GL2_WB (1 << 21)
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#define PACKET3_RELEASE_MEM_GCR_SEQ (1 << 22)
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#define PACKET3_RELEASE_MEM_CACHE_POLICY(x) ((x) << 25)
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/* 0 - cache_policy__me_release_mem__lru
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* 1 - cache_policy__me_release_mem__stream
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* 2 - cache_policy__me_release_mem__noa
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* 3 - cache_policy__me_release_mem__bypass
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*/
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#define PACKET3_RELEASE_MEM_EXECUTE (1 << 28)
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#define PACKET3_RELEASE_MEM_DATA_SEL(x) ((x) << 29)
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/* 0 - discard
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* 1 - send low 32bit data
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* 2 - send 64bit data
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* 3 - send 64bit GPU counter value
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* 4 - send 64bit sys counter value
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*/
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#define PACKET3_RELEASE_MEM_INT_SEL(x) ((x) << 24)
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/* 0 - none
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* 1 - interrupt only (DATA_SEL = 0)
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* 2 - interrupt when data write is confirmed
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*/
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#define PACKET3_RELEASE_MEM_DST_SEL(x) ((x) << 16)
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/* 0 - MC
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* 1 - TC/L2
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*/
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#define PACKET3_PREAMBLE_CNTL 0x4A
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# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
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# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
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#define PACKET3_DMA_DATA 0x50
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/* 1. header
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* 2. CONTROL
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* 3. SRC_ADDR_LO or DATA [31:0]
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* 4. SRC_ADDR_HI [31:0]
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* 5. DST_ADDR_LO [31:0]
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* 6. DST_ADDR_HI [7:0]
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* 7. COMMAND [31:26] | BYTE_COUNT [25:0]
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*/
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/* CONTROL */
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# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0)
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/* 0 - ME
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* 1 - PFP
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*/
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# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)
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/* 0 - LRU
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* 1 - Stream
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*/
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# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20)
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/* 0 - DST_ADDR using DAS
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* 1 - GDS
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* 3 - DST_ADDR using L2
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*/
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# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)
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/* 0 - LRU
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* 1 - Stream
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*/
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# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29)
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/* 0 - SRC_ADDR using SAS
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* 1 - GDS
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* 2 - DATA
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* 3 - SRC_ADDR using L2
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*/
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# define PACKET3_DMA_DATA_CP_SYNC (1 << 31)
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/* COMMAND */
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# define PACKET3_DMA_DATA_CMD_SAS (1 << 26)
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/* 0 - memory
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* 1 - register
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*/
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# define PACKET3_DMA_DATA_CMD_DAS (1 << 27)
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/* 0 - memory
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* 1 - register
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*/
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# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28)
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# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)
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# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)
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#define PACKET3_CONTEXT_REG_RMW 0x51
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#define PACKET3_GFX_CNTX_UPDATE 0x52
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#define PACKET3_BLK_CNTX_UPDATE 0x53
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#define PACKET3_INCR_UPDT_STATE 0x55
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#define PACKET3_ACQUIRE_MEM 0x58
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2020-03-25 04:39:37 +08:00
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/* 1. HEADER
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* 2. COHER_CNTL [30:0]
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* 2.1 ENGINE_SEL [31:31]
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* 2. COHER_SIZE [31:0]
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* 3. COHER_SIZE_HI [7:0]
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* 4. COHER_BASE_LO [31:0]
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* 5. COHER_BASE_HI [23:0]
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* 7. POLL_INTERVAL [15:0]
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* 8. GCR_CNTL [18:0]
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*/
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#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x) ((x) << 0)
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/*
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* 0:NOP
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* 1:ALL
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* 2:RANGE
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* 3:FIRST_LAST
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*/
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#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x) ((x) << 2)
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/*
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* 0:ALL
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* 1:reserved
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* 2:RANGE
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* 3:FIRST_LAST
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*/
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#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(x) ((x) << 4)
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#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(x) ((x) << 5)
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#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB(x) ((x) << 6)
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#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x) ((x) << 7)
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#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x) ((x) << 8)
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#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(x) ((x) << 9)
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#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x) ((x) << 10)
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#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x) ((x) << 11)
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/*
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* 0:ALL
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* 1:VOL
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* 2:RANGE
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* 3:FIRST_LAST
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*/
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#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x) ((x) << 13)
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#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x) ((x) << 14)
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#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x) ((x) << 15)
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#define PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x) ((x) << 16)
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/*
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* 0: PARALLEL
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* 1: FORWARD
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* 2: REVERSE
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*/
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#define PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA (1 << 18)
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2019-03-04 14:29:55 +08:00
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#define PACKET3_REWIND 0x59
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#define PACKET3_INTERRUPT 0x5A
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#define PACKET3_GEN_PDEPTE 0x5B
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#define PACKET3_INDIRECT_BUFFER_PASID 0x5C
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#define PACKET3_PRIME_UTCL2 0x5D
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#define PACKET3_LOAD_UCONFIG_REG 0x5E
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#define PACKET3_LOAD_SH_REG 0x5F
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#define PACKET3_LOAD_CONFIG_REG 0x60
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#define PACKET3_LOAD_CONTEXT_REG 0x61
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#define PACKET3_LOAD_COMPUTE_STATE 0x62
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#define PACKET3_LOAD_SH_REG_INDEX 0x63
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#define PACKET3_SET_CONFIG_REG 0x68
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#define PACKET3_SET_CONFIG_REG_START 0x00002000
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#define PACKET3_SET_CONFIG_REG_END 0x00002c00
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#define PACKET3_SET_CONTEXT_REG 0x69
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#define PACKET3_SET_CONTEXT_REG_START 0x0000a000
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#define PACKET3_SET_CONTEXT_REG_END 0x0000a400
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#define PACKET3_SET_CONTEXT_REG_INDEX 0x6A
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#define PACKET3_SET_VGPR_REG_DI_MULTI 0x71
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#define PACKET3_SET_SH_REG_DI 0x72
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#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
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#define PACKET3_SET_SH_REG_DI_MULTI 0x74
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#define PACKET3_GFX_PIPE_LOCK 0x75
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#define PACKET3_SET_SH_REG 0x76
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#define PACKET3_SET_SH_REG_START 0x00002c00
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#define PACKET3_SET_SH_REG_END 0x00003000
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#define PACKET3_SET_SH_REG_OFFSET 0x77
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#define PACKET3_SET_QUEUE_REG 0x78
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#define PACKET3_SET_UCONFIG_REG 0x79
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#define PACKET3_SET_UCONFIG_REG_START 0x0000c000
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#define PACKET3_SET_UCONFIG_REG_END 0x0000c400
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#define PACKET3_SET_UCONFIG_REG_INDEX 0x7A
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#define PACKET3_FORWARD_HEADER 0x7C
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#define PACKET3_SCRATCH_RAM_WRITE 0x7D
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#define PACKET3_SCRATCH_RAM_READ 0x7E
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#define PACKET3_LOAD_CONST_RAM 0x80
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#define PACKET3_WRITE_CONST_RAM 0x81
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#define PACKET3_DUMP_CONST_RAM 0x83
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#define PACKET3_INCREMENT_CE_COUNTER 0x84
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#define PACKET3_INCREMENT_DE_COUNTER 0x85
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#define PACKET3_WAIT_ON_CE_COUNTER 0x86
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#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
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#define PACKET3_SWITCH_BUFFER 0x8B
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#define PACKET3_DISPATCH_DRAW_PREAMBLE 0x8C
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#define PACKET3_DISPATCH_DRAW_PREAMBLE_ACE 0x8C
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#define PACKET3_DISPATCH_DRAW 0x8D
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#define PACKET3_DISPATCH_DRAW_ACE 0x8D
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#define PACKET3_GET_LOD_STATS 0x8E
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#define PACKET3_DRAW_MULTI_PREAMBLE 0x8F
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#define PACKET3_FRAME_CONTROL 0x90
|
2019-08-08 17:00:16 +08:00
|
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# define FRAME_TMZ (1 << 0)
|
2019-03-04 14:29:55 +08:00
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# define FRAME_CMD(x) ((x) << 28)
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/*
|
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|
* x=0: tmz_begin
|
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|
* x=1: tmz_end
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*/
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#define PACKET3_INDEX_ATTRIBUTES_INDIRECT 0x91
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#define PACKET3_WAIT_REG_MEM64 0x93
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|
#define PACKET3_COND_PREEMPT 0x94
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|
#define PACKET3_HDP_FLUSH 0x95
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|
#define PACKET3_COPY_DATA_RB 0x96
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#define PACKET3_INVALIDATE_TLBS 0x98
|
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|
# define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0)
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|
|
# define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4)
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|
# define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5)
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|
|
#define PACKET3_AQL_PACKET 0x99
|
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|
|
#define PACKET3_DMA_DATA_FILL_MULTI 0x9A
|
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|
|
#define PACKET3_SET_SH_REG_INDEX 0x9B
|
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|
|
|
#define PACKET3_DRAW_INDIRECT_COUNT_MULTI 0x9C
|
|
|
|
|
#define PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI 0x9D
|
|
|
|
|
#define PACKET3_DUMP_CONST_RAM_OFFSET 0x9E
|
|
|
|
|
#define PACKET3_LOAD_CONTEXT_REG_INDEX 0x9F
|
|
|
|
|
#define PACKET3_SET_RESOURCES 0xA0
|
|
|
|
|
/* 1. header
|
|
|
|
|
* 2. CONTROL
|
|
|
|
|
* 3. QUEUE_MASK_LO [31:0]
|
|
|
|
|
* 4. QUEUE_MASK_HI [31:0]
|
|
|
|
|
* 5. GWS_MASK_LO [31:0]
|
|
|
|
|
* 6. GWS_MASK_HI [31:0]
|
|
|
|
|
* 7. OAC_MASK [15:0]
|
|
|
|
|
* 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0]
|
|
|
|
|
*/
|
|
|
|
|
# define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0)
|
|
|
|
|
# define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16)
|
|
|
|
|
# define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29)
|
|
|
|
|
#define PACKET3_MAP_PROCESS 0xA1
|
|
|
|
|
#define PACKET3_MAP_QUEUES 0xA2
|
|
|
|
|
/* 1. header
|
|
|
|
|
* 2. CONTROL
|
|
|
|
|
* 3. CONTROL2
|
|
|
|
|
* 4. MQD_ADDR_LO [31:0]
|
|
|
|
|
* 5. MQD_ADDR_HI [31:0]
|
|
|
|
|
* 6. WPTR_ADDR_LO [31:0]
|
|
|
|
|
* 7. WPTR_ADDR_HI [31:0]
|
|
|
|
|
*/
|
|
|
|
|
/* CONTROL */
|
|
|
|
|
# define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4)
|
|
|
|
|
# define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8)
|
|
|
|
|
# define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13)
|
|
|
|
|
# define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16)
|
|
|
|
|
# define PACKET3_MAP_QUEUES_ME(x) ((x) << 18)
|
|
|
|
|
# define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21)
|
|
|
|
|
# define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24)
|
|
|
|
|
# define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26)
|
|
|
|
|
# define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29)
|
|
|
|
|
/* CONTROL2 */
|
|
|
|
|
# define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1)
|
|
|
|
|
# define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2)
|
|
|
|
|
#define PACKET3_UNMAP_QUEUES 0xA3
|
|
|
|
|
/* 1. header
|
|
|
|
|
* 2. CONTROL
|
|
|
|
|
* 3. CONTROL2
|
|
|
|
|
* 4. CONTROL3
|
|
|
|
|
* 5. CONTROL4
|
|
|
|
|
* 6. CONTROL5
|
|
|
|
|
*/
|
|
|
|
|
/* CONTROL */
|
|
|
|
|
# define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0)
|
|
|
|
|
/* 0 - PREEMPT_QUEUES
|
|
|
|
|
* 1 - RESET_QUEUES
|
|
|
|
|
* 2 - DISABLE_PROCESS_QUEUES
|
|
|
|
|
* 3 - PREEMPT_QUEUES_NO_UNMAP
|
|
|
|
|
*/
|
|
|
|
|
# define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4)
|
|
|
|
|
# define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26)
|
|
|
|
|
# define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29)
|
|
|
|
|
/* CONTROL2a */
|
|
|
|
|
# define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0)
|
|
|
|
|
/* CONTROL2b */
|
|
|
|
|
# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2)
|
|
|
|
|
/* CONTROL3a */
|
|
|
|
|
# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2)
|
|
|
|
|
/* CONTROL3b */
|
|
|
|
|
# define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0)
|
|
|
|
|
/* CONTROL4 */
|
|
|
|
|
# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2)
|
|
|
|
|
/* CONTROL5 */
|
|
|
|
|
# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2)
|
|
|
|
|
#define PACKET3_QUERY_STATUS 0xA4
|
|
|
|
|
/* 1. header
|
|
|
|
|
* 2. CONTROL
|
|
|
|
|
* 3. CONTROL2
|
|
|
|
|
* 4. ADDR_LO [31:0]
|
|
|
|
|
* 5. ADDR_HI [31:0]
|
|
|
|
|
* 6. DATA_LO [31:0]
|
|
|
|
|
* 7. DATA_HI [31:0]
|
|
|
|
|
*/
|
|
|
|
|
/* CONTROL */
|
|
|
|
|
# define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0)
|
|
|
|
|
# define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28)
|
|
|
|
|
# define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30)
|
|
|
|
|
/* CONTROL2a */
|
|
|
|
|
# define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0)
|
|
|
|
|
/* CONTROL2b */
|
|
|
|
|
# define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2)
|
|
|
|
|
# define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25)
|
|
|
|
|
#define PACKET3_RUN_LIST 0xA5
|
|
|
|
|
#define PACKET3_MAP_PROCESS_VM 0xA6
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#endif
|
