2016-04-26 06:28:56 +08:00
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/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Ke Yu
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* Zhiyuan Lv <zhiyuan.lv@intel.com>
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*
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* Contributors:
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* Terrence Xu <terrence.xu@intel.com>
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* Changbin Du <changbin.du@intel.com>
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* Bing Niu <bing.niu@intel.com>
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* Zhi Wang <zhi.a.wang@intel.com>
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*
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*/
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#ifndef _GVT_DISPLAY_H_
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#define _GVT_DISPLAY_H_
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2019-11-08 17:41:42 +08:00
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#include <linux/types.h>
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drm/i915/gvt: Refactor GVT vblank emulator for vGPU virtual display
Current vblank emulator uses single hrtimer at 16ms period for all vGPUs,
which introduces three major issues:
- 16ms matches the refresh rate at 62.5Hz (instead of 60Hz) which
doesn't follow standard timing. This leads to some frame drop or glitch
issue during video playback. SW expects a vsync interval of 16.667ms or
higher precision for an accurate 60Hz refresh rate. However current
vblank emulator only works at 16ms.
- Doesn't respect the fact that with current virtual EDID timing set,
not all resolutions are running at 60Hz. For example, current virtual
EDID also supports refresh rate at 56Hz, 59.97Hz, 60Hz, 75Hz, etc.
- Current vblank emulator use single hrtimer for all vGPUs. Regardsless
the possibility that different guests could run in different
resolutions, all vsync interrupts are injected at 16ms interval with
same hrtimer.
Based on previous patch which decode guest expected refresh rate from
vreg, the vblank emulator refactor patch makes following changes:
- Change the vblank emulator hrtimer from gvt global to per-vGPU.
By doing this, each vGPU display can operates at different refresh
rates. Currently only one dislay is supported for each vGPU so per-vGPU
hrtimer is enough. If multiple displays are supported per-vGPU in
future, we can expand to per-PIPE further.
- Change the fixed hrtimer period from 16ms to dynamic based on vreg.
GVT is expected to emulate the HW as close as possible. So reflacting
the accurate vsync interrupt interval is more correct than fixed 16ms.
- Change the vblank timer period and start the timer on PIPECONF change.
The initial period is updated to 16666667 based on 60Hz refresh rate.
According to PRM, PIPECONF controls the timing generator of the
connected display on this pipe, so it's safe to stop hrtimer on
PIPECONF disabling, and re-start hrtimer at new period on enabling.
Other changes including:
- Move vblank_timer_fn from irq.c into display.c.
- Clean per-vGPU vblank timer at clean_display instead of clean_irq.
To run quick test, launch a web browser and goto URL: www.displayhz.com
The actual refresh rate from guest can now always match guest settings.
V2:
Rebase to 5.11.
Remove unused intel_gvt_clean_irq().
Simplify enable logic in update_vblank_emulation(). (zhenyu)
Loop all vGPU by idr when check all vblank timer. (zhenyu)
Signed-off-by: Colin Xu <colin.xu@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20210226044630.284269-1-colin.xu@intel.com
Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2021-02-26 12:46:30 +08:00
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#include <linux/hrtimer.h>
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2019-11-08 17:41:42 +08:00
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struct intel_gvt;
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struct intel_vgpu;
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2016-04-26 06:28:56 +08:00
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#define SBI_REG_MAX 20
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#define DPCD_SIZE 0x700
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#define intel_vgpu_port(vgpu, port) \
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(&(vgpu->display.ports[port]))
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#define intel_vgpu_has_monitor_on_port(vgpu, port) \
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(intel_vgpu_port(vgpu, port)->edid && \
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intel_vgpu_port(vgpu, port)->edid->data_valid)
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#define intel_vgpu_port_is_dp(vgpu, port) \
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((intel_vgpu_port(vgpu, port)->type == GVT_DP_A) || \
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(intel_vgpu_port(vgpu, port)->type == GVT_DP_B) || \
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(intel_vgpu_port(vgpu, port)->type == GVT_DP_C) || \
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(intel_vgpu_port(vgpu, port)->type == GVT_DP_D))
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#define INTEL_GVT_MAX_UEVENT_VARS 3
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/* DPCD start */
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#define DPCD_SIZE 0x700
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/* DPCD */
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#define DP_SET_POWER 0x600
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#define DP_SET_POWER_D0 0x1
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#define AUX_NATIVE_WRITE 0x8
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#define AUX_NATIVE_READ 0x9
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#define AUX_NATIVE_REPLY_MASK (0x3 << 4)
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#define AUX_NATIVE_REPLY_ACK (0x0 << 4)
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#define AUX_NATIVE_REPLY_NAK (0x1 << 4)
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#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
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2018-04-11 16:39:22 +08:00
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#define AUX_BURST_SIZE 20
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2016-04-26 06:28:56 +08:00
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/* DPCD addresses */
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#define DPCD_REV 0x000
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#define DPCD_MAX_LINK_RATE 0x001
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#define DPCD_MAX_LANE_COUNT 0x002
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#define DPCD_TRAINING_PATTERN_SET 0x102
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#define DPCD_SINK_COUNT 0x200
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#define DPCD_LANE0_1_STATUS 0x202
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#define DPCD_LANE2_3_STATUS 0x203
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#define DPCD_LANE_ALIGN_STATUS_UPDATED 0x204
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#define DPCD_SINK_STATUS 0x205
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/* link training */
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#define DPCD_TRAINING_PATTERN_SET_MASK 0x03
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#define DPCD_LINK_TRAINING_DISABLED 0x00
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#define DPCD_TRAINING_PATTERN_1 0x01
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#define DPCD_TRAINING_PATTERN_2 0x02
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#define DPCD_CP_READY_MASK (1 << 6)
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/* lane status */
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#define DPCD_LANES_CR_DONE 0x11
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#define DPCD_LANES_EQ_DONE 0x22
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#define DPCD_SYMBOL_LOCKED 0x44
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#define DPCD_INTERLANE_ALIGN_DONE 0x01
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#define DPCD_SINK_IN_SYNC 0x03
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/* DPCD end */
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#define SBI_RESPONSE_MASK 0x3
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#define SBI_RESPONSE_SHIFT 0x1
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#define SBI_STAT_MASK 0x1
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#define SBI_STAT_SHIFT 0x0
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#define SBI_OPCODE_SHIFT 8
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#define SBI_OPCODE_MASK (0xff << SBI_OPCODE_SHIFT)
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#define SBI_CMD_IORD 2
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#define SBI_CMD_IOWR 3
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#define SBI_CMD_CRRD 6
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#define SBI_CMD_CRWR 7
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#define SBI_ADDR_OFFSET_SHIFT 16
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#define SBI_ADDR_OFFSET_MASK (0xffff << SBI_ADDR_OFFSET_SHIFT)
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struct intel_vgpu_sbi_register {
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unsigned int offset;
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u32 value;
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};
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struct intel_vgpu_sbi {
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int number;
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struct intel_vgpu_sbi_register registers[SBI_REG_MAX];
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};
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enum intel_gvt_plane_type {
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PRIMARY_PLANE = 0,
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CURSOR_PLANE,
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SPRITE_PLANE,
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MAX_PLANE
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};
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struct intel_vgpu_dpcd_data {
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bool data_valid;
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u8 data[DPCD_SIZE];
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};
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enum intel_vgpu_port_type {
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GVT_CRT = 0,
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GVT_DP_A,
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GVT_DP_B,
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GVT_DP_C,
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GVT_DP_D,
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GVT_HDMI_B,
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GVT_HDMI_C,
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GVT_HDMI_D,
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GVT_PORT_MAX
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};
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2019-01-30 18:25:52 +08:00
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enum intel_vgpu_edid {
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GVT_EDID_1024_768,
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GVT_EDID_1920_1200,
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GVT_EDID_NUM,
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};
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2021-02-26 12:45:59 +08:00
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#define GVT_DEFAULT_REFRESH_RATE 60
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2016-04-26 06:28:56 +08:00
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struct intel_vgpu_port {
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/* per display EDID information */
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struct intel_vgpu_edid_data *edid;
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/* per display DPCD information */
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struct intel_vgpu_dpcd_data *dpcd;
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int type;
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2019-01-30 18:25:52 +08:00
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enum intel_vgpu_edid id;
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2021-02-26 12:45:59 +08:00
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/* x1000 to get accurate 59.94, 24.976, 29.94, etc. in timing std. */
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u32 vrefresh_k;
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2017-02-24 10:58:20 +08:00
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};
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drm/i915/gvt: Refactor GVT vblank emulator for vGPU virtual display
Current vblank emulator uses single hrtimer at 16ms period for all vGPUs,
which introduces three major issues:
- 16ms matches the refresh rate at 62.5Hz (instead of 60Hz) which
doesn't follow standard timing. This leads to some frame drop or glitch
issue during video playback. SW expects a vsync interval of 16.667ms or
higher precision for an accurate 60Hz refresh rate. However current
vblank emulator only works at 16ms.
- Doesn't respect the fact that with current virtual EDID timing set,
not all resolutions are running at 60Hz. For example, current virtual
EDID also supports refresh rate at 56Hz, 59.97Hz, 60Hz, 75Hz, etc.
- Current vblank emulator use single hrtimer for all vGPUs. Regardsless
the possibility that different guests could run in different
resolutions, all vsync interrupts are injected at 16ms interval with
same hrtimer.
Based on previous patch which decode guest expected refresh rate from
vreg, the vblank emulator refactor patch makes following changes:
- Change the vblank emulator hrtimer from gvt global to per-vGPU.
By doing this, each vGPU display can operates at different refresh
rates. Currently only one dislay is supported for each vGPU so per-vGPU
hrtimer is enough. If multiple displays are supported per-vGPU in
future, we can expand to per-PIPE further.
- Change the fixed hrtimer period from 16ms to dynamic based on vreg.
GVT is expected to emulate the HW as close as possible. So reflacting
the accurate vsync interrupt interval is more correct than fixed 16ms.
- Change the vblank timer period and start the timer on PIPECONF change.
The initial period is updated to 16666667 based on 60Hz refresh rate.
According to PRM, PIPECONF controls the timing generator of the
connected display on this pipe, so it's safe to stop hrtimer on
PIPECONF disabling, and re-start hrtimer at new period on enabling.
Other changes including:
- Move vblank_timer_fn from irq.c into display.c.
- Clean per-vGPU vblank timer at clean_display instead of clean_irq.
To run quick test, launch a web browser and goto URL: www.displayhz.com
The actual refresh rate from guest can now always match guest settings.
V2:
Rebase to 5.11.
Remove unused intel_gvt_clean_irq().
Simplify enable logic in update_vblank_emulation(). (zhenyu)
Loop all vGPU by idr when check all vblank timer. (zhenyu)
Signed-off-by: Colin Xu <colin.xu@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20210226044630.284269-1-colin.xu@intel.com
Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2021-02-26 12:46:30 +08:00
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struct intel_vgpu_vblank_timer {
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struct hrtimer timer;
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u32 vrefresh_k;
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u64 period;
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};
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2017-02-24 10:58:21 +08:00
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static inline char *vgpu_edid_str(enum intel_vgpu_edid id)
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{
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switch (id) {
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case GVT_EDID_1024_768:
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return "1024x768";
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case GVT_EDID_1920_1200:
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return "1920x1200";
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default:
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return "";
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}
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}
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2019-01-30 18:25:52 +08:00
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static inline unsigned int vgpu_edid_xres(enum intel_vgpu_edid id)
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{
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switch (id) {
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case GVT_EDID_1024_768:
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return 1024;
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case GVT_EDID_1920_1200:
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return 1920;
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default:
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return 0;
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}
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}
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static inline unsigned int vgpu_edid_yres(enum intel_vgpu_edid id)
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{
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switch (id) {
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case GVT_EDID_1024_768:
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return 768;
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case GVT_EDID_1920_1200:
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return 1200;
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default:
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return 0;
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}
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}
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drm/i915/gvt: Refactor GVT vblank emulator for vGPU virtual display
Current vblank emulator uses single hrtimer at 16ms period for all vGPUs,
which introduces three major issues:
- 16ms matches the refresh rate at 62.5Hz (instead of 60Hz) which
doesn't follow standard timing. This leads to some frame drop or glitch
issue during video playback. SW expects a vsync interval of 16.667ms or
higher precision for an accurate 60Hz refresh rate. However current
vblank emulator only works at 16ms.
- Doesn't respect the fact that with current virtual EDID timing set,
not all resolutions are running at 60Hz. For example, current virtual
EDID also supports refresh rate at 56Hz, 59.97Hz, 60Hz, 75Hz, etc.
- Current vblank emulator use single hrtimer for all vGPUs. Regardsless
the possibility that different guests could run in different
resolutions, all vsync interrupts are injected at 16ms interval with
same hrtimer.
Based on previous patch which decode guest expected refresh rate from
vreg, the vblank emulator refactor patch makes following changes:
- Change the vblank emulator hrtimer from gvt global to per-vGPU.
By doing this, each vGPU display can operates at different refresh
rates. Currently only one dislay is supported for each vGPU so per-vGPU
hrtimer is enough. If multiple displays are supported per-vGPU in
future, we can expand to per-PIPE further.
- Change the fixed hrtimer period from 16ms to dynamic based on vreg.
GVT is expected to emulate the HW as close as possible. So reflacting
the accurate vsync interrupt interval is more correct than fixed 16ms.
- Change the vblank timer period and start the timer on PIPECONF change.
The initial period is updated to 16666667 based on 60Hz refresh rate.
According to PRM, PIPECONF controls the timing generator of the
connected display on this pipe, so it's safe to stop hrtimer on
PIPECONF disabling, and re-start hrtimer at new period on enabling.
Other changes including:
- Move vblank_timer_fn from irq.c into display.c.
- Clean per-vGPU vblank timer at clean_display instead of clean_irq.
To run quick test, launch a web browser and goto URL: www.displayhz.com
The actual refresh rate from guest can now always match guest settings.
V2:
Rebase to 5.11.
Remove unused intel_gvt_clean_irq().
Simplify enable logic in update_vblank_emulation(). (zhenyu)
Loop all vGPU by idr when check all vblank timer. (zhenyu)
Signed-off-by: Colin Xu <colin.xu@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20210226044630.284269-1-colin.xu@intel.com
Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2021-02-26 12:46:30 +08:00
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void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu);
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void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon);
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2016-04-26 06:28:56 +08:00
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2017-02-24 10:58:21 +08:00
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int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution);
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2017-02-14 14:50:18 +08:00
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void intel_vgpu_reset_display(struct intel_vgpu *vgpu);
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2016-04-26 06:28:56 +08:00
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void intel_vgpu_clean_display(struct intel_vgpu *vgpu);
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2017-11-23 16:26:32 +08:00
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int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe);
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2016-04-26 06:28:56 +08:00
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#endif
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