2009-04-28 10:57:12 +08:00
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/*
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* xHCI host controller driver
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*
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* Copyright (C) 2008 Intel Corp.
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*
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* Author: Sarah Sharp
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* Some code borrowed from the Linux EHCI driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <asm/unaligned.h>
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#include "xhci.h"
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2010-10-14 22:23:03 +08:00
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#define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
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#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
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PORT_RC | PORT_PLC | PORT_PE)
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xhci: Register second xHCI roothub.
This patch changes the xHCI driver to allocate two roothubs. This touches
the driver initialization and shutdown paths, roothub emulation code, and
port status change event handlers. This is a rather large patch, but it
can't be broken up, or it would break git-bisect.
Make the xHCI driver register its own PCI probe function. This will call
the USB core to create the USB 2.0 roothub, and then create the USB 3.0
roothub. This gets the code for registering a shared roothub out of the
USB core, and allows other HCDs later to decide if and how many shared
roothubs they want to allocate.
Make sure the xHCI's reset method marks the xHCI host controller's primary
roothub as the USB 2.0 roothub. This ensures that the high speed bus will
be processed first when the PCI device is resumed, and any USB 3.0 devices
that have migrated over to high speed will migrate back after being reset.
This ensures that USB persist works with these odd devices.
The reset method will also mark the xHCI USB2 roothub as having an
integrated TT. Like EHCI host controllers with a "rate matching hub" the
xHCI USB 2.0 roothub doesn't have an OHCI or UHCI companion controller.
It doesn't really have a TT, but we'll lie and say it has an integrated
TT. We need to do this because the USB core will reject LS/FS devices
under a HS hub without a TT.
Other details:
-------------
The roothub emulation code is changed to return the correct number of
ports for the two roothubs. For the USB 3.0 roothub, it only reports the
USB 3.0 ports. For the USB 2.0 roothub, it reports all the LS/FS/HS
ports. The code to disable a port now checks the speed of the roothub,
and refuses to disable SuperSpeed ports under the USB 3.0 roothub.
The code for initializing a new device context must be changed to set the
proper roothub port number. Since we've split the xHCI host into two
roothubs, we can't just use the port number in the ancestor hub. Instead,
we loop through the array of hardware port status register speeds and find
the Nth port with a similar speed.
The port status change event handler is updated to figure out whether the
port that reported the change is a USB 3.0 port, or a non-SuperSpeed port.
Once it figures out the port speed, it kicks the proper roothub.
The function to find a slot ID based on the port index is updated to take
into account that the two roothubs will have over-lapping port indexes.
It checks that the virtual device with a matching port index is the same
speed as the passed in roothub.
There's also changes to the driver initialization and shutdown paths:
1. Make sure that the xhci_hcd pointer is shared across the two
usb_hcd structures. The xhci_hcd pointer is allocated and the
registers are mapped in when xhci_pci_setup() is called with the
primary HCD. When xhci_pci_setup() is called with the non-primary
HCD, the xhci_hcd pointer is stored.
2. Make sure to set the sg_tablesize for both usb_hcd structures. Set
the PCI DMA mask for the non-primary HCD to allow for 64-bit or 32-bit
DMA. (The PCI DMA mask is set from the primary HCD further down in
the xhci_pci_setup() function.)
3. Ensure that the host controller doesn't start kicking khubd in
response to port status changes before both usb_hcd structures are
registered. xhci_run() only starts the xHC running once it has been
called with the non-primary roothub. Similarly, the xhci_stop()
function only halts the host controller when it is called with the
non-primary HCD. Then on the second call, it resets and cleans up the
MSI-X irqs.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2010-12-17 03:21:10 +08:00
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static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
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2009-04-28 10:57:12 +08:00
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struct usb_hub_descriptor *desc)
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{
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int ports;
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u16 temp;
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xhci: Register second xHCI roothub.
This patch changes the xHCI driver to allocate two roothubs. This touches
the driver initialization and shutdown paths, roothub emulation code, and
port status change event handlers. This is a rather large patch, but it
can't be broken up, or it would break git-bisect.
Make the xHCI driver register its own PCI probe function. This will call
the USB core to create the USB 2.0 roothub, and then create the USB 3.0
roothub. This gets the code for registering a shared roothub out of the
USB core, and allows other HCDs later to decide if and how many shared
roothubs they want to allocate.
Make sure the xHCI's reset method marks the xHCI host controller's primary
roothub as the USB 2.0 roothub. This ensures that the high speed bus will
be processed first when the PCI device is resumed, and any USB 3.0 devices
that have migrated over to high speed will migrate back after being reset.
This ensures that USB persist works with these odd devices.
The reset method will also mark the xHCI USB2 roothub as having an
integrated TT. Like EHCI host controllers with a "rate matching hub" the
xHCI USB 2.0 roothub doesn't have an OHCI or UHCI companion controller.
It doesn't really have a TT, but we'll lie and say it has an integrated
TT. We need to do this because the USB core will reject LS/FS devices
under a HS hub without a TT.
Other details:
-------------
The roothub emulation code is changed to return the correct number of
ports for the two roothubs. For the USB 3.0 roothub, it only reports the
USB 3.0 ports. For the USB 2.0 roothub, it reports all the LS/FS/HS
ports. The code to disable a port now checks the speed of the roothub,
and refuses to disable SuperSpeed ports under the USB 3.0 roothub.
The code for initializing a new device context must be changed to set the
proper roothub port number. Since we've split the xHCI host into two
roothubs, we can't just use the port number in the ancestor hub. Instead,
we loop through the array of hardware port status register speeds and find
the Nth port with a similar speed.
The port status change event handler is updated to figure out whether the
port that reported the change is a USB 3.0 port, or a non-SuperSpeed port.
Once it figures out the port speed, it kicks the proper roothub.
The function to find a slot ID based on the port index is updated to take
into account that the two roothubs will have over-lapping port indexes.
It checks that the virtual device with a matching port index is the same
speed as the passed in roothub.
There's also changes to the driver initialization and shutdown paths:
1. Make sure that the xhci_hcd pointer is shared across the two
usb_hcd structures. The xhci_hcd pointer is allocated and the
registers are mapped in when xhci_pci_setup() is called with the
primary HCD. When xhci_pci_setup() is called with the non-primary
HCD, the xhci_hcd pointer is stored.
2. Make sure to set the sg_tablesize for both usb_hcd structures. Set
the PCI DMA mask for the non-primary HCD to allow for 64-bit or 32-bit
DMA. (The PCI DMA mask is set from the primary HCD further down in
the xhci_pci_setup() function.)
3. Ensure that the host controller doesn't start kicking khubd in
response to port status changes before both usb_hcd structures are
registered. xhci_run() only starts the xHC running once it has been
called with the non-primary roothub. Similarly, the xhci_stop()
function only halts the host controller when it is called with the
non-primary HCD. Then on the second call, it resets and cleans up the
MSI-X irqs.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2010-12-17 03:21:10 +08:00
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if (hcd->speed == HCD_USB3)
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ports = xhci->num_usb3_ports;
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else
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ports = xhci->num_usb2_ports;
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/* FIXME: return a USB 3.0 hub descriptor if this request was for the
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* USB3 roothub.
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*/
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2009-04-28 10:57:12 +08:00
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/* USB 3.0 hubs have a different descriptor, but we fake this for now */
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desc->bDescriptorType = 0x29;
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desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
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desc->bHubContrCurrent = 0;
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desc->bNbrPorts = ports;
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temp = 1 + (ports / 8);
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desc->bDescLength = 7 + 2 * temp;
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2001-09-17 15:00:00 +08:00
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memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
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memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
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2009-04-28 10:57:12 +08:00
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/* Ugh, these should be #defines, FIXME */
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/* Using table 11-13 in USB 2.0 spec. */
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temp = 0;
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/* Bits 1:0 - support port power switching, or power always on */
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if (HCC_PPC(xhci->hcc_params))
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temp |= 0x0001;
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else
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temp |= 0x0002;
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/* Bit 2 - root hubs are not part of a compound device */
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/* Bits 4:3 - individual port over current protection */
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temp |= 0x0008;
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/* Bits 6:5 - no TTs in root ports */
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/* Bit 7 - no port indicators */
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desc->wHubCharacteristics = (__force __u16) cpu_to_le16(temp);
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}
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static unsigned int xhci_port_speed(unsigned int port_status)
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{
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if (DEV_LOWSPEED(port_status))
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2010-03-05 00:32:30 +08:00
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return USB_PORT_STAT_LOW_SPEED;
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2009-04-28 10:57:12 +08:00
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if (DEV_HIGHSPEED(port_status))
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2010-03-05 00:32:30 +08:00
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return USB_PORT_STAT_HIGH_SPEED;
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2009-04-28 10:57:12 +08:00
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if (DEV_SUPERSPEED(port_status))
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2010-03-05 00:32:30 +08:00
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return USB_PORT_STAT_SUPER_SPEED;
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2009-04-28 10:57:12 +08:00
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/*
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* FIXME: Yes, we should check for full speed, but the core uses that as
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* a default in portspeed() in usb/core/hub.c (which is the only place
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2010-03-05 00:32:30 +08:00
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* USB_PORT_STAT_*_SPEED is used).
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2009-04-28 10:57:12 +08:00
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*/
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return 0;
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}
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/*
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* These bits are Read Only (RO) and should be saved and written to the
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* registers: 0, 3, 10:13, 30
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* connect status, over-current status, port speed, and device removable.
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* connect status and port speed are also sticky - meaning they're in
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* the AUX well and they aren't changed by a hot, warm, or cold reset.
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*/
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#define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
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/*
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* These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
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* bits 5:8, 9, 14:15, 25:27
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* link state, port power, port indicator state, "wake on" enable state
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*/
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#define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
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/*
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* These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
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* bit 4 (port reset)
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*/
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#define XHCI_PORT_RW1S ((1<<4))
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/*
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* These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
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* bits 1, 17, 18, 19, 20, 21, 22, 23
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* port enable/disable, and
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* change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
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* over-current, reset, link state, and L1 change
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*/
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#define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
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/*
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* Bit 16 is RW, and writing a '1' to it causes the link state control to be
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* latched in
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*/
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#define XHCI_PORT_RW ((1<<16))
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/*
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* These bits are Reserved Zero (RsvdZ) and zero should be written to them:
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* bits 2, 24, 28:31
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*/
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#define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
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/*
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* Given a port state, this function returns a value that would result in the
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* port being in the same state, if the value was written to the port status
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* control register.
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* Save Read Only (RO) bits and save read/write bits where
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* writing a 0 clears the bit and writing a 1 sets the bit (RWS).
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* For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
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*/
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2010-10-14 22:23:00 +08:00
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u32 xhci_port_state_to_neutral(u32 state)
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2009-04-28 10:57:12 +08:00
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{
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/* Save read-only status and port state */
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return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
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}
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2010-10-14 22:22:57 +08:00
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/*
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* find slot id based on port number.
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xhci: Register second xHCI roothub.
This patch changes the xHCI driver to allocate two roothubs. This touches
the driver initialization and shutdown paths, roothub emulation code, and
port status change event handlers. This is a rather large patch, but it
can't be broken up, or it would break git-bisect.
Make the xHCI driver register its own PCI probe function. This will call
the USB core to create the USB 2.0 roothub, and then create the USB 3.0
roothub. This gets the code for registering a shared roothub out of the
USB core, and allows other HCDs later to decide if and how many shared
roothubs they want to allocate.
Make sure the xHCI's reset method marks the xHCI host controller's primary
roothub as the USB 2.0 roothub. This ensures that the high speed bus will
be processed first when the PCI device is resumed, and any USB 3.0 devices
that have migrated over to high speed will migrate back after being reset.
This ensures that USB persist works with these odd devices.
The reset method will also mark the xHCI USB2 roothub as having an
integrated TT. Like EHCI host controllers with a "rate matching hub" the
xHCI USB 2.0 roothub doesn't have an OHCI or UHCI companion controller.
It doesn't really have a TT, but we'll lie and say it has an integrated
TT. We need to do this because the USB core will reject LS/FS devices
under a HS hub without a TT.
Other details:
-------------
The roothub emulation code is changed to return the correct number of
ports for the two roothubs. For the USB 3.0 roothub, it only reports the
USB 3.0 ports. For the USB 2.0 roothub, it reports all the LS/FS/HS
ports. The code to disable a port now checks the speed of the roothub,
and refuses to disable SuperSpeed ports under the USB 3.0 roothub.
The code for initializing a new device context must be changed to set the
proper roothub port number. Since we've split the xHCI host into two
roothubs, we can't just use the port number in the ancestor hub. Instead,
we loop through the array of hardware port status register speeds and find
the Nth port with a similar speed.
The port status change event handler is updated to figure out whether the
port that reported the change is a USB 3.0 port, or a non-SuperSpeed port.
Once it figures out the port speed, it kicks the proper roothub.
The function to find a slot ID based on the port index is updated to take
into account that the two roothubs will have over-lapping port indexes.
It checks that the virtual device with a matching port index is the same
speed as the passed in roothub.
There's also changes to the driver initialization and shutdown paths:
1. Make sure that the xhci_hcd pointer is shared across the two
usb_hcd structures. The xhci_hcd pointer is allocated and the
registers are mapped in when xhci_pci_setup() is called with the
primary HCD. When xhci_pci_setup() is called with the non-primary
HCD, the xhci_hcd pointer is stored.
2. Make sure to set the sg_tablesize for both usb_hcd structures. Set
the PCI DMA mask for the non-primary HCD to allow for 64-bit or 32-bit
DMA. (The PCI DMA mask is set from the primary HCD further down in
the xhci_pci_setup() function.)
3. Ensure that the host controller doesn't start kicking khubd in
response to port status changes before both usb_hcd structures are
registered. xhci_run() only starts the xHC running once it has been
called with the non-primary roothub. Similarly, the xhci_stop()
function only halts the host controller when it is called with the
non-primary HCD. Then on the second call, it resets and cleans up the
MSI-X irqs.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2010-12-17 03:21:10 +08:00
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* @port: The one-based port number from one of the two split roothubs.
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2010-10-14 22:22:57 +08:00
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*/
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2010-12-17 02:49:09 +08:00
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int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
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u16 port)
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2010-10-14 22:22:57 +08:00
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{
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int slot_id;
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int i;
|
xhci: Register second xHCI roothub.
This patch changes the xHCI driver to allocate two roothubs. This touches
the driver initialization and shutdown paths, roothub emulation code, and
port status change event handlers. This is a rather large patch, but it
can't be broken up, or it would break git-bisect.
Make the xHCI driver register its own PCI probe function. This will call
the USB core to create the USB 2.0 roothub, and then create the USB 3.0
roothub. This gets the code for registering a shared roothub out of the
USB core, and allows other HCDs later to decide if and how many shared
roothubs they want to allocate.
Make sure the xHCI's reset method marks the xHCI host controller's primary
roothub as the USB 2.0 roothub. This ensures that the high speed bus will
be processed first when the PCI device is resumed, and any USB 3.0 devices
that have migrated over to high speed will migrate back after being reset.
This ensures that USB persist works with these odd devices.
The reset method will also mark the xHCI USB2 roothub as having an
integrated TT. Like EHCI host controllers with a "rate matching hub" the
xHCI USB 2.0 roothub doesn't have an OHCI or UHCI companion controller.
It doesn't really have a TT, but we'll lie and say it has an integrated
TT. We need to do this because the USB core will reject LS/FS devices
under a HS hub without a TT.
Other details:
-------------
The roothub emulation code is changed to return the correct number of
ports for the two roothubs. For the USB 3.0 roothub, it only reports the
USB 3.0 ports. For the USB 2.0 roothub, it reports all the LS/FS/HS
ports. The code to disable a port now checks the speed of the roothub,
and refuses to disable SuperSpeed ports under the USB 3.0 roothub.
The code for initializing a new device context must be changed to set the
proper roothub port number. Since we've split the xHCI host into two
roothubs, we can't just use the port number in the ancestor hub. Instead,
we loop through the array of hardware port status register speeds and find
the Nth port with a similar speed.
The port status change event handler is updated to figure out whether the
port that reported the change is a USB 3.0 port, or a non-SuperSpeed port.
Once it figures out the port speed, it kicks the proper roothub.
The function to find a slot ID based on the port index is updated to take
into account that the two roothubs will have over-lapping port indexes.
It checks that the virtual device with a matching port index is the same
speed as the passed in roothub.
There's also changes to the driver initialization and shutdown paths:
1. Make sure that the xhci_hcd pointer is shared across the two
usb_hcd structures. The xhci_hcd pointer is allocated and the
registers are mapped in when xhci_pci_setup() is called with the
primary HCD. When xhci_pci_setup() is called with the non-primary
HCD, the xhci_hcd pointer is stored.
2. Make sure to set the sg_tablesize for both usb_hcd structures. Set
the PCI DMA mask for the non-primary HCD to allow for 64-bit or 32-bit
DMA. (The PCI DMA mask is set from the primary HCD further down in
the xhci_pci_setup() function.)
3. Ensure that the host controller doesn't start kicking khubd in
response to port status changes before both usb_hcd structures are
registered. xhci_run() only starts the xHC running once it has been
called with the non-primary roothub. Similarly, the xhci_stop()
function only halts the host controller when it is called with the
non-primary HCD. Then on the second call, it resets and cleans up the
MSI-X irqs.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2010-12-17 03:21:10 +08:00
|
|
|
|
enum usb_device_speed speed;
|
2010-10-14 22:22:57 +08:00
|
|
|
|
|
|
|
|
|
|
slot_id = 0;
|
|
|
|
|
|
for (i = 0; i < MAX_HC_SLOTS; i++) {
|
|
|
|
|
|
if (!xhci->devs[i])
|
|
|
|
|
|
continue;
|
xhci: Register second xHCI roothub.
This patch changes the xHCI driver to allocate two roothubs. This touches
the driver initialization and shutdown paths, roothub emulation code, and
port status change event handlers. This is a rather large patch, but it
can't be broken up, or it would break git-bisect.
Make the xHCI driver register its own PCI probe function. This will call
the USB core to create the USB 2.0 roothub, and then create the USB 3.0
roothub. This gets the code for registering a shared roothub out of the
USB core, and allows other HCDs later to decide if and how many shared
roothubs they want to allocate.
Make sure the xHCI's reset method marks the xHCI host controller's primary
roothub as the USB 2.0 roothub. This ensures that the high speed bus will
be processed first when the PCI device is resumed, and any USB 3.0 devices
that have migrated over to high speed will migrate back after being reset.
This ensures that USB persist works with these odd devices.
The reset method will also mark the xHCI USB2 roothub as having an
integrated TT. Like EHCI host controllers with a "rate matching hub" the
xHCI USB 2.0 roothub doesn't have an OHCI or UHCI companion controller.
It doesn't really have a TT, but we'll lie and say it has an integrated
TT. We need to do this because the USB core will reject LS/FS devices
under a HS hub without a TT.
Other details:
-------------
The roothub emulation code is changed to return the correct number of
ports for the two roothubs. For the USB 3.0 roothub, it only reports the
USB 3.0 ports. For the USB 2.0 roothub, it reports all the LS/FS/HS
ports. The code to disable a port now checks the speed of the roothub,
and refuses to disable SuperSpeed ports under the USB 3.0 roothub.
The code for initializing a new device context must be changed to set the
proper roothub port number. Since we've split the xHCI host into two
roothubs, we can't just use the port number in the ancestor hub. Instead,
we loop through the array of hardware port status register speeds and find
the Nth port with a similar speed.
The port status change event handler is updated to figure out whether the
port that reported the change is a USB 3.0 port, or a non-SuperSpeed port.
Once it figures out the port speed, it kicks the proper roothub.
The function to find a slot ID based on the port index is updated to take
into account that the two roothubs will have over-lapping port indexes.
It checks that the virtual device with a matching port index is the same
speed as the passed in roothub.
There's also changes to the driver initialization and shutdown paths:
1. Make sure that the xhci_hcd pointer is shared across the two
usb_hcd structures. The xhci_hcd pointer is allocated and the
registers are mapped in when xhci_pci_setup() is called with the
primary HCD. When xhci_pci_setup() is called with the non-primary
HCD, the xhci_hcd pointer is stored.
2. Make sure to set the sg_tablesize for both usb_hcd structures. Set
the PCI DMA mask for the non-primary HCD to allow for 64-bit or 32-bit
DMA. (The PCI DMA mask is set from the primary HCD further down in
the xhci_pci_setup() function.)
3. Ensure that the host controller doesn't start kicking khubd in
response to port status changes before both usb_hcd structures are
registered. xhci_run() only starts the xHC running once it has been
called with the non-primary roothub. Similarly, the xhci_stop()
function only halts the host controller when it is called with the
non-primary HCD. Then on the second call, it resets and cleans up the
MSI-X irqs.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2010-12-17 03:21:10 +08:00
|
|
|
|
speed = xhci->devs[i]->udev->speed;
|
|
|
|
|
|
if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
|
|
|
|
|
|
&& xhci->devs[i]->port == port) {
|
2010-10-14 22:22:57 +08:00
|
|
|
|
slot_id = i;
|
|
|
|
|
|
break;
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
return slot_id;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
|
* Stop device
|
|
|
|
|
|
* It issues stop endpoint command for EP 0 to 30. And wait the last command
|
|
|
|
|
|
* to complete.
|
|
|
|
|
|
* suspend will set to 1, if suspend bit need to set in command.
|
|
|
|
|
|
*/
|
|
|
|
|
|
static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
|
|
|
|
|
|
{
|
|
|
|
|
|
struct xhci_virt_device *virt_dev;
|
|
|
|
|
|
struct xhci_command *cmd;
|
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
int timeleft;
|
|
|
|
|
|
int ret;
|
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
|
|
ret = 0;
|
|
|
|
|
|
virt_dev = xhci->devs[slot_id];
|
|
|
|
|
|
cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
|
|
|
|
|
|
if (!cmd) {
|
|
|
|
|
|
xhci_dbg(xhci, "Couldn't allocate command structure.\n");
|
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
|
|
|
|
for (i = LAST_EP_INDEX; i > 0; i--) {
|
|
|
|
|
|
if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue)
|
|
|
|
|
|
xhci_queue_stop_endpoint(xhci, slot_id, i, suspend);
|
|
|
|
|
|
}
|
|
|
|
|
|
cmd->command_trb = xhci->cmd_ring->enqueue;
|
|
|
|
|
|
list_add_tail(&cmd->cmd_list, &virt_dev->cmd_list);
|
|
|
|
|
|
xhci_queue_stop_endpoint(xhci, slot_id, 0, suspend);
|
|
|
|
|
|
xhci_ring_cmd_db(xhci);
|
|
|
|
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
|
|
|
|
|
|
|
|
|
|
/* Wait for last stop endpoint command to finish */
|
|
|
|
|
|
timeleft = wait_for_completion_interruptible_timeout(
|
|
|
|
|
|
cmd->completion,
|
|
|
|
|
|
USB_CTRL_SET_TIMEOUT);
|
|
|
|
|
|
if (timeleft <= 0) {
|
|
|
|
|
|
xhci_warn(xhci, "%s while waiting for stop endpoint command\n",
|
|
|
|
|
|
timeleft == 0 ? "Timeout" : "Signal");
|
|
|
|
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
|
|
|
|
/* The timeout might have raced with the event ring handler, so
|
|
|
|
|
|
* only delete from the list if the item isn't poisoned.
|
|
|
|
|
|
*/
|
|
|
|
|
|
if (cmd->cmd_list.next != LIST_POISON1)
|
|
|
|
|
|
list_del(&cmd->cmd_list);
|
|
|
|
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
|
|
|
|
ret = -ETIME;
|
|
|
|
|
|
goto command_cleanup;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
command_cleanup:
|
|
|
|
|
|
xhci_free_command(xhci, cmd);
|
|
|
|
|
|
return ret;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
|
* Ring device, it rings the all doorbells unconditionally.
|
|
|
|
|
|
*/
|
2010-10-14 22:23:00 +08:00
|
|
|
|
void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
|
2010-10-14 22:22:57 +08:00
|
|
|
|
{
|
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < LAST_EP_INDEX + 1; i++)
|
|
|
|
|
|
if (xhci->devs[slot_id]->eps[i].ring &&
|
|
|
|
|
|
xhci->devs[slot_id]->eps[i].ring->dequeue)
|
|
|
|
|
|
xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
|
|
|
|
|
|
|
|
|
|
|
|
return;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
xhci: Register second xHCI roothub.
This patch changes the xHCI driver to allocate two roothubs. This touches
the driver initialization and shutdown paths, roothub emulation code, and
port status change event handlers. This is a rather large patch, but it
can't be broken up, or it would break git-bisect.
Make the xHCI driver register its own PCI probe function. This will call
the USB core to create the USB 2.0 roothub, and then create the USB 3.0
roothub. This gets the code for registering a shared roothub out of the
USB core, and allows other HCDs later to decide if and how many shared
roothubs they want to allocate.
Make sure the xHCI's reset method marks the xHCI host controller's primary
roothub as the USB 2.0 roothub. This ensures that the high speed bus will
be processed first when the PCI device is resumed, and any USB 3.0 devices
that have migrated over to high speed will migrate back after being reset.
This ensures that USB persist works with these odd devices.
The reset method will also mark the xHCI USB2 roothub as having an
integrated TT. Like EHCI host controllers with a "rate matching hub" the
xHCI USB 2.0 roothub doesn't have an OHCI or UHCI companion controller.
It doesn't really have a TT, but we'll lie and say it has an integrated
TT. We need to do this because the USB core will reject LS/FS devices
under a HS hub without a TT.
Other details:
-------------
The roothub emulation code is changed to return the correct number of
ports for the two roothubs. For the USB 3.0 roothub, it only reports the
USB 3.0 ports. For the USB 2.0 roothub, it reports all the LS/FS/HS
ports. The code to disable a port now checks the speed of the roothub,
and refuses to disable SuperSpeed ports under the USB 3.0 roothub.
The code for initializing a new device context must be changed to set the
proper roothub port number. Since we've split the xHCI host into two
roothubs, we can't just use the port number in the ancestor hub. Instead,
we loop through the array of hardware port status register speeds and find
the Nth port with a similar speed.
The port status change event handler is updated to figure out whether the
port that reported the change is a USB 3.0 port, or a non-SuperSpeed port.
Once it figures out the port speed, it kicks the proper roothub.
The function to find a slot ID based on the port index is updated to take
into account that the two roothubs will have over-lapping port indexes.
It checks that the virtual device with a matching port index is the same
speed as the passed in roothub.
There's also changes to the driver initialization and shutdown paths:
1. Make sure that the xhci_hcd pointer is shared across the two
usb_hcd structures. The xhci_hcd pointer is allocated and the
registers are mapped in when xhci_pci_setup() is called with the
primary HCD. When xhci_pci_setup() is called with the non-primary
HCD, the xhci_hcd pointer is stored.
2. Make sure to set the sg_tablesize for both usb_hcd structures. Set
the PCI DMA mask for the non-primary HCD to allow for 64-bit or 32-bit
DMA. (The PCI DMA mask is set from the primary HCD further down in
the xhci_pci_setup() function.)
3. Ensure that the host controller doesn't start kicking khubd in
response to port status changes before both usb_hcd structures are
registered. xhci_run() only starts the xHC running once it has been
called with the non-primary roothub. Similarly, the xhci_stop()
function only halts the host controller when it is called with the
non-primary HCD. Then on the second call, it resets and cleans up the
MSI-X irqs.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2010-12-17 03:21:10 +08:00
|
|
|
|
static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
|
|
|
|
|
|
u16 wIndex, u32 __iomem *addr, u32 port_status)
|
2009-12-10 07:59:11 +08:00
|
|
|
|
{
|
2010-11-17 07:58:52 +08:00
|
|
|
|
/* Don't allow the USB core to disable SuperSpeed ports. */
|
xhci: Register second xHCI roothub.
This patch changes the xHCI driver to allocate two roothubs. This touches
the driver initialization and shutdown paths, roothub emulation code, and
port status change event handlers. This is a rather large patch, but it
can't be broken up, or it would break git-bisect.
Make the xHCI driver register its own PCI probe function. This will call
the USB core to create the USB 2.0 roothub, and then create the USB 3.0
roothub. This gets the code for registering a shared roothub out of the
USB core, and allows other HCDs later to decide if and how many shared
roothubs they want to allocate.
Make sure the xHCI's reset method marks the xHCI host controller's primary
roothub as the USB 2.0 roothub. This ensures that the high speed bus will
be processed first when the PCI device is resumed, and any USB 3.0 devices
that have migrated over to high speed will migrate back after being reset.
This ensures that USB persist works with these odd devices.
The reset method will also mark the xHCI USB2 roothub as having an
integrated TT. Like EHCI host controllers with a "rate matching hub" the
xHCI USB 2.0 roothub doesn't have an OHCI or UHCI companion controller.
It doesn't really have a TT, but we'll lie and say it has an integrated
TT. We need to do this because the USB core will reject LS/FS devices
under a HS hub without a TT.
Other details:
-------------
The roothub emulation code is changed to return the correct number of
ports for the two roothubs. For the USB 3.0 roothub, it only reports the
USB 3.0 ports. For the USB 2.0 roothub, it reports all the LS/FS/HS
ports. The code to disable a port now checks the speed of the roothub,
and refuses to disable SuperSpeed ports under the USB 3.0 roothub.
The code for initializing a new device context must be changed to set the
proper roothub port number. Since we've split the xHCI host into two
roothubs, we can't just use the port number in the ancestor hub. Instead,
we loop through the array of hardware port status register speeds and find
the Nth port with a similar speed.
The port status change event handler is updated to figure out whether the
port that reported the change is a USB 3.0 port, or a non-SuperSpeed port.
Once it figures out the port speed, it kicks the proper roothub.
The function to find a slot ID based on the port index is updated to take
into account that the two roothubs will have over-lapping port indexes.
It checks that the virtual device with a matching port index is the same
speed as the passed in roothub.
There's also changes to the driver initialization and shutdown paths:
1. Make sure that the xhci_hcd pointer is shared across the two
usb_hcd structures. The xhci_hcd pointer is allocated and the
registers are mapped in when xhci_pci_setup() is called with the
primary HCD. When xhci_pci_setup() is called with the non-primary
HCD, the xhci_hcd pointer is stored.
2. Make sure to set the sg_tablesize for both usb_hcd structures. Set
the PCI DMA mask for the non-primary HCD to allow for 64-bit or 32-bit
DMA. (The PCI DMA mask is set from the primary HCD further down in
the xhci_pci_setup() function.)
3. Ensure that the host controller doesn't start kicking khubd in
response to port status changes before both usb_hcd structures are
registered. xhci_run() only starts the xHC running once it has been
called with the non-primary roothub. Similarly, the xhci_stop()
function only halts the host controller when it is called with the
non-primary HCD. Then on the second call, it resets and cleans up the
MSI-X irqs.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2010-12-17 03:21:10 +08:00
|
|
|
|
if (hcd->speed == HCD_USB3) {
|
2010-11-17 07:58:52 +08:00
|
|
|
|
xhci_dbg(xhci, "Ignoring request to disable "
|
|
|
|
|
|
"SuperSpeed port.\n");
|
|
|
|
|
|
return;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2009-12-10 07:59:11 +08:00
|
|
|
|
/* Write 1 to disable the port */
|
|
|
|
|
|
xhci_writel(xhci, port_status | PORT_PE, addr);
|
|
|
|
|
|
port_status = xhci_readl(xhci, addr);
|
|
|
|
|
|
xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
|
|
|
|
|
|
wIndex, port_status);
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2009-12-10 07:59:08 +08:00
|
|
|
|
static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
|
|
|
|
|
|
u16 wIndex, u32 __iomem *addr, u32 port_status)
|
|
|
|
|
|
{
|
|
|
|
|
|
char *port_change_bit;
|
|
|
|
|
|
u32 status;
|
|
|
|
|
|
|
|
|
|
|
|
switch (wValue) {
|
|
|
|
|
|
case USB_PORT_FEAT_C_RESET:
|
|
|
|
|
|
status = PORT_RC;
|
|
|
|
|
|
port_change_bit = "reset";
|
|
|
|
|
|
break;
|
|
|
|
|
|
case USB_PORT_FEAT_C_CONNECTION:
|
|
|
|
|
|
status = PORT_CSC;
|
|
|
|
|
|
port_change_bit = "connect";
|
|
|
|
|
|
break;
|
|
|
|
|
|
case USB_PORT_FEAT_C_OVER_CURRENT:
|
|
|
|
|
|
status = PORT_OCC;
|
|
|
|
|
|
port_change_bit = "over-current";
|
|
|
|
|
|
break;
|
2009-12-10 07:59:11 +08:00
|
|
|
|
case USB_PORT_FEAT_C_ENABLE:
|
|
|
|
|
|
status = PORT_PEC;
|
|
|
|
|
|
port_change_bit = "enable/disable";
|
|
|
|
|
|
break;
|
2010-10-14 22:22:57 +08:00
|
|
|
|
case USB_PORT_FEAT_C_SUSPEND:
|
|
|
|
|
|
status = PORT_PLC;
|
|
|
|
|
|
port_change_bit = "suspend/resume";
|
|
|
|
|
|
break;
|
2009-12-10 07:59:08 +08:00
|
|
|
|
default:
|
|
|
|
|
|
/* Should never happen */
|
|
|
|
|
|
return;
|
|
|
|
|
|
}
|
|
|
|
|
|
/* Change bits are all write 1 to clear */
|
|
|
|
|
|
xhci_writel(xhci, port_status | status, addr);
|
|
|
|
|
|
port_status = xhci_readl(xhci, addr);
|
|
|
|
|
|
xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
|
|
|
|
|
|
port_change_bit, wIndex, port_status);
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2009-04-28 10:57:12 +08:00
|
|
|
|
int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
|
|
|
|
|
|
u16 wIndex, char *buf, u16 wLength)
|
|
|
|
|
|
{
|
|
|
|
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
|
|
|
|
int ports;
|
|
|
|
|
|
unsigned long flags;
|
2010-10-14 22:23:00 +08:00
|
|
|
|
u32 temp, temp1, status;
|
2009-04-28 10:57:12 +08:00
|
|
|
|
int retval = 0;
|
xhci: Register second xHCI roothub.
This patch changes the xHCI driver to allocate two roothubs. This touches
the driver initialization and shutdown paths, roothub emulation code, and
port status change event handlers. This is a rather large patch, but it
can't be broken up, or it would break git-bisect.
Make the xHCI driver register its own PCI probe function. This will call
the USB core to create the USB 2.0 roothub, and then create the USB 3.0
roothub. This gets the code for registering a shared roothub out of the
USB core, and allows other HCDs later to decide if and how many shared
roothubs they want to allocate.
Make sure the xHCI's reset method marks the xHCI host controller's primary
roothub as the USB 2.0 roothub. This ensures that the high speed bus will
be processed first when the PCI device is resumed, and any USB 3.0 devices
that have migrated over to high speed will migrate back after being reset.
This ensures that USB persist works with these odd devices.
The reset method will also mark the xHCI USB2 roothub as having an
integrated TT. Like EHCI host controllers with a "rate matching hub" the
xHCI USB 2.0 roothub doesn't have an OHCI or UHCI companion controller.
It doesn't really have a TT, but we'll lie and say it has an integrated
TT. We need to do this because the USB core will reject LS/FS devices
under a HS hub without a TT.
Other details:
-------------
The roothub emulation code is changed to return the correct number of
ports for the two roothubs. For the USB 3.0 roothub, it only reports the
USB 3.0 ports. For the USB 2.0 roothub, it reports all the LS/FS/HS
ports. The code to disable a port now checks the speed of the roothub,
and refuses to disable SuperSpeed ports under the USB 3.0 roothub.
The code for initializing a new device context must be changed to set the
proper roothub port number. Since we've split the xHCI host into two
roothubs, we can't just use the port number in the ancestor hub. Instead,
we loop through the array of hardware port status register speeds and find
the Nth port with a similar speed.
The port status change event handler is updated to figure out whether the
port that reported the change is a USB 3.0 port, or a non-SuperSpeed port.
Once it figures out the port speed, it kicks the proper roothub.
The function to find a slot ID based on the port index is updated to take
into account that the two roothubs will have over-lapping port indexes.
It checks that the virtual device with a matching port index is the same
speed as the passed in roothub.
There's also changes to the driver initialization and shutdown paths:
1. Make sure that the xhci_hcd pointer is shared across the two
usb_hcd structures. The xhci_hcd pointer is allocated and the
registers are mapped in when xhci_pci_setup() is called with the
primary HCD. When xhci_pci_setup() is called with the non-primary
HCD, the xhci_hcd pointer is stored.
2. Make sure to set the sg_tablesize for both usb_hcd structures. Set
the PCI DMA mask for the non-primary HCD to allow for 64-bit or 32-bit
DMA. (The PCI DMA mask is set from the primary HCD further down in
the xhci_pci_setup() function.)
3. Ensure that the host controller doesn't start kicking khubd in
response to port status changes before both usb_hcd structures are
registered. xhci_run() only starts the xHC running once it has been
called with the non-primary roothub. Similarly, the xhci_stop()
function only halts the host controller when it is called with the
non-primary HCD. Then on the second call, it resets and cleans up the
MSI-X irqs.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2010-12-17 03:21:10 +08:00
|
|
|
|
u32 __iomem **port_array;
|
2010-10-14 22:22:57 +08:00
|
|
|
|
int slot_id;
|
2010-12-16 04:47:14 +08:00
|
|
|
|
struct xhci_bus_state *bus_state;
|
2009-04-28 10:57:12 +08:00
|
|
|
|
|
xhci: Register second xHCI roothub.
This patch changes the xHCI driver to allocate two roothubs. This touches
the driver initialization and shutdown paths, roothub emulation code, and
port status change event handlers. This is a rather large patch, but it
can't be broken up, or it would break git-bisect.
Make the xHCI driver register its own PCI probe function. This will call
the USB core to create the USB 2.0 roothub, and then create the USB 3.0
roothub. This gets the code for registering a shared roothub out of the
USB core, and allows other HCDs later to decide if and how many shared
roothubs they want to allocate.
Make sure the xHCI's reset method marks the xHCI host controller's primary
roothub as the USB 2.0 roothub. This ensures that the high speed bus will
be processed first when the PCI device is resumed, and any USB 3.0 devices
that have migrated over to high speed will migrate back after being reset.
This ensures that USB persist works with these odd devices.
The reset method will also mark the xHCI USB2 roothub as having an
integrated TT. Like EHCI host controllers with a "rate matching hub" the
xHCI USB 2.0 roothub doesn't have an OHCI or UHCI companion controller.
It doesn't really have a TT, but we'll lie and say it has an integrated
TT. We need to do this because the USB core will reject LS/FS devices
under a HS hub without a TT.
Other details:
-------------
The roothub emulation code is changed to return the correct number of
ports for the two roothubs. For the USB 3.0 roothub, it only reports the
USB 3.0 ports. For the USB 2.0 roothub, it reports all the LS/FS/HS
ports. The code to disable a port now checks the speed of the roothub,
and refuses to disable SuperSpeed ports under the USB 3.0 roothub.
The code for initializing a new device context must be changed to set the
proper roothub port number. Since we've split the xHCI host into two
roothubs, we can't just use the port number in the ancestor hub. Instead,
we loop through the array of hardware port status register speeds and find
the Nth port with a similar speed.
The port status change event handler is updated to figure out whether the
port that reported the change is a USB 3.0 port, or a non-SuperSpeed port.
Once it figures out the port speed, it kicks the proper roothub.
The function to find a slot ID based on the port index is updated to take
into account that the two roothubs will have over-lapping port indexes.
It checks that the virtual device with a matching port index is the same
speed as the passed in roothub.
There's also changes to the driver initialization and shutdown paths:
1. Make sure that the xhci_hcd pointer is shared across the two
usb_hcd structures. The xhci_hcd pointer is allocated and the
registers are mapped in when xhci_pci_setup() is called with the
primary HCD. When xhci_pci_setup() is called with the non-primary
HCD, the xhci_hcd pointer is stored.
2. Make sure to set the sg_tablesize for both usb_hcd structures. Set
the PCI DMA mask for the non-primary HCD to allow for 64-bit or 32-bit
DMA. (The PCI DMA mask is set from the primary HCD further down in
the xhci_pci_setup() function.)
3. Ensure that the host controller doesn't start kicking khubd in
response to port status changes before both usb_hcd structures are
registered. xhci_run() only starts the xHC running once it has been
called with the non-primary roothub. Similarly, the xhci_stop()
function only halts the host controller when it is called with the
non-primary HCD. Then on the second call, it resets and cleans up the
MSI-X irqs.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2010-12-17 03:21:10 +08:00
|
|
|
|
if (hcd->speed == HCD_USB3) {
|
|
|
|
|
|
ports = xhci->num_usb3_ports;
|
|
|
|
|
|
port_array = xhci->usb3_ports;
|
|
|
|
|
|
} else {
|
|
|
|
|
|
ports = xhci->num_usb2_ports;
|
|
|
|
|
|
port_array = xhci->usb2_ports;
|
2010-12-02 03:34:59 +08:00
|
|
|
|
}
|
2010-12-16 04:47:14 +08:00
|
|
|
|
bus_state = &xhci->bus_state[hcd_index(hcd)];
|
2009-04-28 10:57:12 +08:00
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
|
|
|
|
switch (typeReq) {
|
|
|
|
|
|
case GetHubStatus:
|
|
|
|
|
|
/* No power source, over-current reported per port */
|
|
|
|
|
|
memset(buf, 0, 4);
|
|
|
|
|
|
break;
|
|
|
|
|
|
case GetHubDescriptor:
|
xhci: Register second xHCI roothub.
This patch changes the xHCI driver to allocate two roothubs. This touches
the driver initialization and shutdown paths, roothub emulation code, and
port status change event handlers. This is a rather large patch, but it
can't be broken up, or it would break git-bisect.
Make the xHCI driver register its own PCI probe function. This will call
the USB core to create the USB 2.0 roothub, and then create the USB 3.0
roothub. This gets the code for registering a shared roothub out of the
USB core, and allows other HCDs later to decide if and how many shared
roothubs they want to allocate.
Make sure the xHCI's reset method marks the xHCI host controller's primary
roothub as the USB 2.0 roothub. This ensures that the high speed bus will
be processed first when the PCI device is resumed, and any USB 3.0 devices
that have migrated over to high speed will migrate back after being reset.
This ensures that USB persist works with these odd devices.
The reset method will also mark the xHCI USB2 roothub as having an
integrated TT. Like EHCI host controllers with a "rate matching hub" the
xHCI USB 2.0 roothub doesn't have an OHCI or UHCI companion controller.
It doesn't really have a TT, but we'll lie and say it has an integrated
TT. We need to do this because the USB core will reject LS/FS devices
under a HS hub without a TT.
Other details:
-------------
The roothub emulation code is changed to return the correct number of
ports for the two roothubs. For the USB 3.0 roothub, it only reports the
USB 3.0 ports. For the USB 2.0 roothub, it reports all the LS/FS/HS
ports. The code to disable a port now checks the speed of the roothub,
and refuses to disable SuperSpeed ports under the USB 3.0 roothub.
The code for initializing a new device context must be changed to set the
proper roothub port number. Since we've split the xHCI host into two
roothubs, we can't just use the port number in the ancestor hub. Instead,
we loop through the array of hardware port status register speeds and find
the Nth port with a similar speed.
The port status change event handler is updated to figure out whether the
port that reported the change is a USB 3.0 port, or a non-SuperSpeed port.
Once it figures out the port speed, it kicks the proper roothub.
The function to find a slot ID based on the port index is updated to take
into account that the two roothubs will have over-lapping port indexes.
It checks that the virtual device with a matching port index is the same
speed as the passed in roothub.
There's also changes to the driver initialization and shutdown paths:
1. Make sure that the xhci_hcd pointer is shared across the two
usb_hcd structures. The xhci_hcd pointer is allocated and the
registers are mapped in when xhci_pci_setup() is called with the
primary HCD. When xhci_pci_setup() is called with the non-primary
HCD, the xhci_hcd pointer is stored.
2. Make sure to set the sg_tablesize for both usb_hcd structures. Set
the PCI DMA mask for the non-primary HCD to allow for 64-bit or 32-bit
DMA. (The PCI DMA mask is set from the primary HCD further down in
the xhci_pci_setup() function.)
3. Ensure that the host controller doesn't start kicking khubd in
response to port status changes before both usb_hcd structures are
registered. xhci_run() only starts the xHC running once it has been
called with the non-primary roothub. Similarly, the xhci_stop()
function only halts the host controller when it is called with the
non-primary HCD. Then on the second call, it resets and cleans up the
MSI-X irqs.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2010-12-17 03:21:10 +08:00
|
|
|
|
xhci_hub_descriptor(hcd, xhci,
|
|
|
|
|
|
(struct usb_hub_descriptor *) buf);
|
2009-04-28 10:57:12 +08:00
|
|
|
|
break;
|
|
|
|
|
|
case GetPortStatus:
|
|
|
|
|
|
if (!wIndex || wIndex > ports)
|
|
|
|
|
|
goto error;
|
|
|
|
|
|
wIndex--;
|
|
|
|
|
|
status = 0;
|
2010-12-02 03:34:59 +08:00
|
|
|
|
temp = xhci_readl(xhci, port_array[wIndex]);
|
2009-04-28 10:57:12 +08:00
|
|
|
|
xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp);
|
|
|
|
|
|
|
|
|
|
|
|
/* wPortChange bits */
|
|
|
|
|
|
if (temp & PORT_CSC)
|
2010-03-05 06:05:08 +08:00
|
|
|
|
status |= USB_PORT_STAT_C_CONNECTION << 16;
|
2009-04-28 10:57:12 +08:00
|
|
|
|
if (temp & PORT_PEC)
|
2010-03-05 06:05:08 +08:00
|
|
|
|
status |= USB_PORT_STAT_C_ENABLE << 16;
|
2009-04-28 10:57:12 +08:00
|
|
|
|
if ((temp & PORT_OCC))
|
2010-03-05 06:05:08 +08:00
|
|
|
|
status |= USB_PORT_STAT_C_OVERCURRENT << 16;
|
2009-04-28 10:57:12 +08:00
|
|
|
|
/*
|
2010-10-14 22:22:57 +08:00
|
|
|
|
* FIXME ignoring reset and USB 2.1/3.0 specific
|
2009-04-28 10:57:12 +08:00
|
|
|
|
* changes
|
|
|
|
|
|
*/
|
2010-10-14 22:22:57 +08:00
|
|
|
|
if ((temp & PORT_PLS_MASK) == XDEV_U3
|
|
|
|
|
|
&& (temp & PORT_POWER))
|
|
|
|
|
|
status |= 1 << USB_PORT_FEAT_SUSPEND;
|
2010-10-14 22:23:00 +08:00
|
|
|
|
if ((temp & PORT_PLS_MASK) == XDEV_RESUME) {
|
|
|
|
|
|
if ((temp & PORT_RESET) || !(temp & PORT_PE))
|
|
|
|
|
|
goto error;
|
|
|
|
|
|
if (!DEV_SUPERSPEED(temp) && time_after_eq(jiffies,
|
2010-12-16 04:47:14 +08:00
|
|
|
|
bus_state->resume_done[wIndex])) {
|
2010-10-14 22:23:00 +08:00
|
|
|
|
xhci_dbg(xhci, "Resume USB2 port %d\n",
|
|
|
|
|
|
wIndex + 1);
|
2010-12-16 04:47:14 +08:00
|
|
|
|
bus_state->resume_done[wIndex] = 0;
|
2010-10-14 22:23:00 +08:00
|
|
|
|
temp1 = xhci_port_state_to_neutral(temp);
|
|
|
|
|
|
temp1 &= ~PORT_PLS_MASK;
|
|
|
|
|
|
temp1 |= PORT_LINK_STROBE | XDEV_U0;
|
2010-12-02 03:34:59 +08:00
|
|
|
|
xhci_writel(xhci, temp1, port_array[wIndex]);
|
2010-10-14 22:23:00 +08:00
|
|
|
|
|
|
|
|
|
|
xhci_dbg(xhci, "set port %d resume\n",
|
|
|
|
|
|
wIndex + 1);
|
2010-12-17 02:49:09 +08:00
|
|
|
|
slot_id = xhci_find_slot_id_by_port(hcd, xhci,
|
2010-10-14 22:23:00 +08:00
|
|
|
|
wIndex + 1);
|
|
|
|
|
|
if (!slot_id) {
|
|
|
|
|
|
xhci_dbg(xhci, "slot_id is zero\n");
|
|
|
|
|
|
goto error;
|
|
|
|
|
|
}
|
|
|
|
|
|
xhci_ring_device(xhci, slot_id);
|
2010-12-16 04:47:14 +08:00
|
|
|
|
bus_state->port_c_suspend |= 1 << wIndex;
|
|
|
|
|
|
bus_state->suspended_ports &= ~(1 << wIndex);
|
2010-10-14 22:23:00 +08:00
|
|
|
|
}
|
|
|
|
|
|
}
|
2010-10-14 22:22:57 +08:00
|
|
|
|
if ((temp & PORT_PLS_MASK) == XDEV_U0
|
|
|
|
|
|
&& (temp & PORT_POWER)
|
2010-12-16 04:47:14 +08:00
|
|
|
|
&& (bus_state->suspended_ports & (1 << wIndex))) {
|
|
|
|
|
|
bus_state->suspended_ports &= ~(1 << wIndex);
|
|
|
|
|
|
bus_state->port_c_suspend |= 1 << wIndex;
|
2010-10-14 22:22:57 +08:00
|
|
|
|
}
|
2009-04-28 10:57:12 +08:00
|
|
|
|
if (temp & PORT_CONNECT) {
|
2010-03-05 06:05:08 +08:00
|
|
|
|
status |= USB_PORT_STAT_CONNECTION;
|
2009-04-28 10:57:12 +08:00
|
|
|
|
status |= xhci_port_speed(temp);
|
|
|
|
|
|
}
|
|
|
|
|
|
if (temp & PORT_PE)
|
2010-03-05 06:05:08 +08:00
|
|
|
|
status |= USB_PORT_STAT_ENABLE;
|
2009-04-28 10:57:12 +08:00
|
|
|
|
if (temp & PORT_OC)
|
2010-03-05 06:05:08 +08:00
|
|
|
|
status |= USB_PORT_STAT_OVERCURRENT;
|
2009-04-28 10:57:12 +08:00
|
|
|
|
if (temp & PORT_RESET)
|
2010-03-05 06:05:08 +08:00
|
|
|
|
status |= USB_PORT_STAT_RESET;
|
2009-04-28 10:57:12 +08:00
|
|
|
|
if (temp & PORT_POWER)
|
2010-03-05 06:05:08 +08:00
|
|
|
|
status |= USB_PORT_STAT_POWER;
|
2010-12-16 04:47:14 +08:00
|
|
|
|
if (bus_state->port_c_suspend & (1 << wIndex))
|
2010-10-14 22:22:57 +08:00
|
|
|
|
status |= 1 << USB_PORT_FEAT_C_SUSPEND;
|
2009-04-28 10:57:12 +08:00
|
|
|
|
xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
|
|
|
|
|
|
put_unaligned(cpu_to_le32(status), (__le32 *) buf);
|
|
|
|
|
|
break;
|
|
|
|
|
|
case SetPortFeature:
|
|
|
|
|
|
wIndex &= 0xff;
|
|
|
|
|
|
if (!wIndex || wIndex > ports)
|
|
|
|
|
|
goto error;
|
|
|
|
|
|
wIndex--;
|
2010-12-02 03:34:59 +08:00
|
|
|
|
temp = xhci_readl(xhci, port_array[wIndex]);
|
2009-04-28 10:57:12 +08:00
|
|
|
|
temp = xhci_port_state_to_neutral(temp);
|
|
|
|
|
|
switch (wValue) {
|
2010-10-14 22:22:57 +08:00
|
|
|
|
case USB_PORT_FEAT_SUSPEND:
|
2010-12-02 03:34:59 +08:00
|
|
|
|
temp = xhci_readl(xhci, port_array[wIndex]);
|
2010-10-14 22:22:57 +08:00
|
|
|
|
/* In spec software should not attempt to suspend
|
|
|
|
|
|
* a port unless the port reports that it is in the
|
|
|
|
|
|
* enabled (PED = ‘1’,PLS < ‘3’) state.
|
|
|
|
|
|
*/
|
|
|
|
|
|
if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
|
|
|
|
|
|
|| (temp & PORT_PLS_MASK) >= XDEV_U3) {
|
|
|
|
|
|
xhci_warn(xhci, "USB core suspending device "
|
|
|
|
|
|
"not in U0/U1/U2.\n");
|
|
|
|
|
|
goto error;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2010-12-17 02:49:09 +08:00
|
|
|
|
slot_id = xhci_find_slot_id_by_port(hcd, xhci,
|
|
|
|
|
|
wIndex + 1);
|
2010-10-14 22:22:57 +08:00
|
|
|
|
if (!slot_id) {
|
|
|
|
|
|
xhci_warn(xhci, "slot_id is zero\n");
|
|
|
|
|
|
goto error;
|
|
|
|
|
|
}
|
|
|
|
|
|
/* unlock to execute stop endpoint commands */
|
|
|
|
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
|
|
|
|
xhci_stop_device(xhci, slot_id, 1);
|
|
|
|
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
|
|
|
|
|
|
|
|
|
|
temp = xhci_port_state_to_neutral(temp);
|
|
|
|
|
|
temp &= ~PORT_PLS_MASK;
|
|
|
|
|
|
temp |= PORT_LINK_STROBE | XDEV_U3;
|
2010-12-02 03:34:59 +08:00
|
|
|
|
xhci_writel(xhci, temp, port_array[wIndex]);
|
2010-10-14 22:22:57 +08:00
|
|
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
|
|
|
|
msleep(10); /* wait device to enter */
|
|
|
|
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
|
|
|
|
|
2010-12-02 03:34:59 +08:00
|
|
|
|
temp = xhci_readl(xhci, port_array[wIndex]);
|
2010-12-16 04:47:14 +08:00
|
|
|
|
bus_state->suspended_ports |= 1 << wIndex;
|
2010-10-14 22:22:57 +08:00
|
|
|
|
break;
|
2009-04-28 10:57:12 +08:00
|
|
|
|
case USB_PORT_FEAT_POWER:
|
|
|
|
|
|
/*
|
|
|
|
|
|
* Turn on ports, even if there isn't per-port switching.
|
|
|
|
|
|
* HC will report connect events even before this is set.
|
|
|
|
|
|
* However, khubd will ignore the roothub events until
|
|
|
|
|
|
* the roothub is registered.
|
|
|
|
|
|
*/
|
2010-12-02 03:34:59 +08:00
|
|
|
|
xhci_writel(xhci, temp | PORT_POWER,
|
|
|
|
|
|
port_array[wIndex]);
|
2009-04-28 10:57:12 +08:00
|
|
|
|
|
2010-12-02 03:34:59 +08:00
|
|
|
|
temp = xhci_readl(xhci, port_array[wIndex]);
|
2009-04-28 10:57:12 +08:00
|
|
|
|
xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
|
|
|
|
|
|
break;
|
|
|
|
|
|
case USB_PORT_FEAT_RESET:
|
|
|
|
|
|
temp = (temp | PORT_RESET);
|
2010-12-02 03:34:59 +08:00
|
|
|
|
xhci_writel(xhci, temp, port_array[wIndex]);
|
2009-04-28 10:57:12 +08:00
|
|
|
|
|
2010-12-02 03:34:59 +08:00
|
|
|
|
temp = xhci_readl(xhci, port_array[wIndex]);
|
2009-04-28 10:57:12 +08:00
|
|
|
|
xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
|
|
|
|
|
|
break;
|
|
|
|
|
|
default:
|
|
|
|
|
|
goto error;
|
|
|
|
|
|
}
|
2010-12-02 03:34:59 +08:00
|
|
|
|
/* unblock any posted writes */
|
|
|
|
|
|
temp = xhci_readl(xhci, port_array[wIndex]);
|
2009-04-28 10:57:12 +08:00
|
|
|
|
break;
|
|
|
|
|
|
case ClearPortFeature:
|
|
|
|
|
|
if (!wIndex || wIndex > ports)
|
|
|
|
|
|
goto error;
|
|
|
|
|
|
wIndex--;
|
2010-12-02 03:34:59 +08:00
|
|
|
|
temp = xhci_readl(xhci, port_array[wIndex]);
|
2009-04-28 10:57:12 +08:00
|
|
|
|
temp = xhci_port_state_to_neutral(temp);
|
|
|
|
|
|
switch (wValue) {
|
2010-10-14 22:22:57 +08:00
|
|
|
|
case USB_PORT_FEAT_SUSPEND:
|
2010-12-02 03:34:59 +08:00
|
|
|
|
temp = xhci_readl(xhci, port_array[wIndex]);
|
2010-10-14 22:22:57 +08:00
|
|
|
|
xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
|
|
|
|
|
|
xhci_dbg(xhci, "PORTSC %04x\n", temp);
|
|
|
|
|
|
if (temp & PORT_RESET)
|
|
|
|
|
|
goto error;
|
|
|
|
|
|
if (temp & XDEV_U3) {
|
|
|
|
|
|
if ((temp & PORT_PE) == 0)
|
|
|
|
|
|
goto error;
|
|
|
|
|
|
if (DEV_SUPERSPEED(temp)) {
|
|
|
|
|
|
temp = xhci_port_state_to_neutral(temp);
|
|
|
|
|
|
temp &= ~PORT_PLS_MASK;
|
|
|
|
|
|
temp |= PORT_LINK_STROBE | XDEV_U0;
|
2010-12-02 03:34:59 +08:00
|
|
|
|
xhci_writel(xhci, temp,
|
|
|
|
|
|
port_array[wIndex]);
|
|
|
|
|
|
xhci_readl(xhci, port_array[wIndex]);
|
2010-10-14 22:22:57 +08:00
|
|
|
|
} else {
|
|
|
|
|
|
temp = xhci_port_state_to_neutral(temp);
|
|
|
|
|
|
temp &= ~PORT_PLS_MASK;
|
|
|
|
|
|
temp |= PORT_LINK_STROBE | XDEV_RESUME;
|
2010-12-02 03:34:59 +08:00
|
|
|
|
xhci_writel(xhci, temp,
|
|
|
|
|
|
port_array[wIndex]);
|
2010-10-14 22:22:57 +08:00
|
|
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&xhci->lock,
|
|
|
|
|
|
flags);
|
|
|
|
|
|
msleep(20);
|
|
|
|
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
|
|
|
|
|
2010-12-02 03:34:59 +08:00
|
|
|
|
temp = xhci_readl(xhci,
|
|
|
|
|
|
port_array[wIndex]);
|
2010-10-14 22:22:57 +08:00
|
|
|
|
temp = xhci_port_state_to_neutral(temp);
|
|
|
|
|
|
temp &= ~PORT_PLS_MASK;
|
|
|
|
|
|
temp |= PORT_LINK_STROBE | XDEV_U0;
|
2010-12-02 03:34:59 +08:00
|
|
|
|
xhci_writel(xhci, temp,
|
|
|
|
|
|
port_array[wIndex]);
|
2010-10-14 22:22:57 +08:00
|
|
|
|
}
|
2010-12-16 04:47:14 +08:00
|
|
|
|
bus_state->port_c_suspend |= 1 << wIndex;
|
2010-10-14 22:22:57 +08:00
|
|
|
|
}
|
|
|
|
|
|
|
2010-12-17 02:49:09 +08:00
|
|
|
|
slot_id = xhci_find_slot_id_by_port(hcd, xhci,
|
|
|
|
|
|
wIndex + 1);
|
2010-10-14 22:22:57 +08:00
|
|
|
|
if (!slot_id) {
|
|
|
|
|
|
xhci_dbg(xhci, "slot_id is zero\n");
|
|
|
|
|
|
goto error;
|
|
|
|
|
|
}
|
|
|
|
|
|
xhci_ring_device(xhci, slot_id);
|
|
|
|
|
|
break;
|
|
|
|
|
|
case USB_PORT_FEAT_C_SUSPEND:
|
2010-12-16 04:47:14 +08:00
|
|
|
|
bus_state->port_c_suspend &= ~(1 << wIndex);
|
2009-04-28 10:57:12 +08:00
|
|
|
|
case USB_PORT_FEAT_C_RESET:
|
|
|
|
|
|
case USB_PORT_FEAT_C_CONNECTION:
|
|
|
|
|
|
case USB_PORT_FEAT_C_OVER_CURRENT:
|
2009-12-10 07:59:11 +08:00
|
|
|
|
case USB_PORT_FEAT_C_ENABLE:
|
2009-12-10 07:59:08 +08:00
|
|
|
|
xhci_clear_port_change_bit(xhci, wValue, wIndex,
|
2010-12-02 03:34:59 +08:00
|
|
|
|
port_array[wIndex], temp);
|
2009-04-28 10:57:12 +08:00
|
|
|
|
break;
|
2009-12-10 07:59:11 +08:00
|
|
|
|
case USB_PORT_FEAT_ENABLE:
|
xhci: Register second xHCI roothub.
This patch changes the xHCI driver to allocate two roothubs. This touches
the driver initialization and shutdown paths, roothub emulation code, and
port status change event handlers. This is a rather large patch, but it
can't be broken up, or it would break git-bisect.
Make the xHCI driver register its own PCI probe function. This will call
the USB core to create the USB 2.0 roothub, and then create the USB 3.0
roothub. This gets the code for registering a shared roothub out of the
USB core, and allows other HCDs later to decide if and how many shared
roothubs they want to allocate.
Make sure the xHCI's reset method marks the xHCI host controller's primary
roothub as the USB 2.0 roothub. This ensures that the high speed bus will
be processed first when the PCI device is resumed, and any USB 3.0 devices
that have migrated over to high speed will migrate back after being reset.
This ensures that USB persist works with these odd devices.
The reset method will also mark the xHCI USB2 roothub as having an
integrated TT. Like EHCI host controllers with a "rate matching hub" the
xHCI USB 2.0 roothub doesn't have an OHCI or UHCI companion controller.
It doesn't really have a TT, but we'll lie and say it has an integrated
TT. We need to do this because the USB core will reject LS/FS devices
under a HS hub without a TT.
Other details:
-------------
The roothub emulation code is changed to return the correct number of
ports for the two roothubs. For the USB 3.0 roothub, it only reports the
USB 3.0 ports. For the USB 2.0 roothub, it reports all the LS/FS/HS
ports. The code to disable a port now checks the speed of the roothub,
and refuses to disable SuperSpeed ports under the USB 3.0 roothub.
The code for initializing a new device context must be changed to set the
proper roothub port number. Since we've split the xHCI host into two
roothubs, we can't just use the port number in the ancestor hub. Instead,
we loop through the array of hardware port status register speeds and find
the Nth port with a similar speed.
The port status change event handler is updated to figure out whether the
port that reported the change is a USB 3.0 port, or a non-SuperSpeed port.
Once it figures out the port speed, it kicks the proper roothub.
The function to find a slot ID based on the port index is updated to take
into account that the two roothubs will have over-lapping port indexes.
It checks that the virtual device with a matching port index is the same
speed as the passed in roothub.
There's also changes to the driver initialization and shutdown paths:
1. Make sure that the xhci_hcd pointer is shared across the two
usb_hcd structures. The xhci_hcd pointer is allocated and the
registers are mapped in when xhci_pci_setup() is called with the
primary HCD. When xhci_pci_setup() is called with the non-primary
HCD, the xhci_hcd pointer is stored.
2. Make sure to set the sg_tablesize for both usb_hcd structures. Set
the PCI DMA mask for the non-primary HCD to allow for 64-bit or 32-bit
DMA. (The PCI DMA mask is set from the primary HCD further down in
the xhci_pci_setup() function.)
3. Ensure that the host controller doesn't start kicking khubd in
response to port status changes before both usb_hcd structures are
registered. xhci_run() only starts the xHC running once it has been
called with the non-primary roothub. Similarly, the xhci_stop()
function only halts the host controller when it is called with the
non-primary HCD. Then on the second call, it resets and cleans up the
MSI-X irqs.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2010-12-17 03:21:10 +08:00
|
|
|
|
xhci_disable_port(hcd, xhci, wIndex,
|
2010-12-02 03:34:59 +08:00
|
|
|
|
port_array[wIndex], temp);
|
2009-12-10 07:59:11 +08:00
|
|
|
|
break;
|
2009-04-28 10:57:12 +08:00
|
|
|
|
default:
|
|
|
|
|
|
goto error;
|
|
|
|
|
|
}
|
|
|
|
|
|
break;
|
|
|
|
|
|
default:
|
|
|
|
|
|
error:
|
|
|
|
|
|
/* "stall" on error */
|
|
|
|
|
|
retval = -EPIPE;
|
|
|
|
|
|
}
|
|
|
|
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
|
|
|
|
return retval;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
|
* Returns 0 if the status hasn't changed, or the number of bytes in buf.
|
|
|
|
|
|
* Ports are 0-indexed from the HCD point of view,
|
|
|
|
|
|
* and 1-indexed from the USB core pointer of view.
|
|
|
|
|
|
*
|
|
|
|
|
|
* Note that the status change bits will be cleared as soon as a port status
|
|
|
|
|
|
* change event is generated, so we use the saved status from that event.
|
|
|
|
|
|
*/
|
|
|
|
|
|
int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
|
|
|
|
|
|
{
|
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
u32 temp, status;
|
2010-10-14 22:23:00 +08:00
|
|
|
|
u32 mask;
|
2009-04-28 10:57:12 +08:00
|
|
|
|
int i, retval;
|
|
|
|
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
|
|
|
|
int ports;
|
xhci: Register second xHCI roothub.
This patch changes the xHCI driver to allocate two roothubs. This touches
the driver initialization and shutdown paths, roothub emulation code, and
port status change event handlers. This is a rather large patch, but it
can't be broken up, or it would break git-bisect.
Make the xHCI driver register its own PCI probe function. This will call
the USB core to create the USB 2.0 roothub, and then create the USB 3.0
roothub. This gets the code for registering a shared roothub out of the
USB core, and allows other HCDs later to decide if and how many shared
roothubs they want to allocate.
Make sure the xHCI's reset method marks the xHCI host controller's primary
roothub as the USB 2.0 roothub. This ensures that the high speed bus will
be processed first when the PCI device is resumed, and any USB 3.0 devices
that have migrated over to high speed will migrate back after being reset.
This ensures that USB persist works with these odd devices.
The reset method will also mark the xHCI USB2 roothub as having an
integrated TT. Like EHCI host controllers with a "rate matching hub" the
xHCI USB 2.0 roothub doesn't have an OHCI or UHCI companion controller.
It doesn't really have a TT, but we'll lie and say it has an integrated
TT. We need to do this because the USB core will reject LS/FS devices
under a HS hub without a TT.
Other details:
-------------
The roothub emulation code is changed to return the correct number of
ports for the two roothubs. For the USB 3.0 roothub, it only reports the
USB 3.0 ports. For the USB 2.0 roothub, it reports all the LS/FS/HS
ports. The code to disable a port now checks the speed of the roothub,
and refuses to disable SuperSpeed ports under the USB 3.0 roothub.
The code for initializing a new device context must be changed to set the
proper roothub port number. Since we've split the xHCI host into two
roothubs, we can't just use the port number in the ancestor hub. Instead,
we loop through the array of hardware port status register speeds and find
the Nth port with a similar speed.
The port status change event handler is updated to figure out whether the
port that reported the change is a USB 3.0 port, or a non-SuperSpeed port.
Once it figures out the port speed, it kicks the proper roothub.
The function to find a slot ID based on the port index is updated to take
into account that the two roothubs will have over-lapping port indexes.
It checks that the virtual device with a matching port index is the same
speed as the passed in roothub.
There's also changes to the driver initialization and shutdown paths:
1. Make sure that the xhci_hcd pointer is shared across the two
usb_hcd structures. The xhci_hcd pointer is allocated and the
registers are mapped in when xhci_pci_setup() is called with the
primary HCD. When xhci_pci_setup() is called with the non-primary
HCD, the xhci_hcd pointer is stored.
2. Make sure to set the sg_tablesize for both usb_hcd structures. Set
the PCI DMA mask for the non-primary HCD to allow for 64-bit or 32-bit
DMA. (The PCI DMA mask is set from the primary HCD further down in
the xhci_pci_setup() function.)
3. Ensure that the host controller doesn't start kicking khubd in
response to port status changes before both usb_hcd structures are
registered. xhci_run() only starts the xHC running once it has been
called with the non-primary roothub. Similarly, the xhci_stop()
function only halts the host controller when it is called with the
non-primary HCD. Then on the second call, it resets and cleans up the
MSI-X irqs.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2010-12-17 03:21:10 +08:00
|
|
|
|
u32 __iomem **port_array;
|
2010-12-16 04:47:14 +08:00
|
|
|
|
struct xhci_bus_state *bus_state;
|
2009-04-28 10:57:12 +08:00
|
|
|
|
|
xhci: Register second xHCI roothub.
This patch changes the xHCI driver to allocate two roothubs. This touches
the driver initialization and shutdown paths, roothub emulation code, and
port status change event handlers. This is a rather large patch, but it
can't be broken up, or it would break git-bisect.
Make the xHCI driver register its own PCI probe function. This will call
the USB core to create the USB 2.0 roothub, and then create the USB 3.0
roothub. This gets the code for registering a shared roothub out of the
USB core, and allows other HCDs later to decide if and how many shared
roothubs they want to allocate.
Make sure the xHCI's reset method marks the xHCI host controller's primary
roothub as the USB 2.0 roothub. This ensures that the high speed bus will
be processed first when the PCI device is resumed, and any USB 3.0 devices
that have migrated over to high speed will migrate back after being reset.
This ensures that USB persist works with these odd devices.
The reset method will also mark the xHCI USB2 roothub as having an
integrated TT. Like EHCI host controllers with a "rate matching hub" the
xHCI USB 2.0 roothub doesn't have an OHCI or UHCI companion controller.
It doesn't really have a TT, but we'll lie and say it has an integrated
TT. We need to do this because the USB core will reject LS/FS devices
under a HS hub without a TT.
Other details:
-------------
The roothub emulation code is changed to return the correct number of
ports for the two roothubs. For the USB 3.0 roothub, it only reports the
USB 3.0 ports. For the USB 2.0 roothub, it reports all the LS/FS/HS
ports. The code to disable a port now checks the speed of the roothub,
and refuses to disable SuperSpeed ports under the USB 3.0 roothub.
The code for initializing a new device context must be changed to set the
proper roothub port number. Since we've split the xHCI host into two
roothubs, we can't just use the port number in the ancestor hub. Instead,
we loop through the array of hardware port status register speeds and find
the Nth port with a similar speed.
The port status change event handler is updated to figure out whether the
port that reported the change is a USB 3.0 port, or a non-SuperSpeed port.
Once it figures out the port speed, it kicks the proper roothub.
The function to find a slot ID based on the port index is updated to take
into account that the two roothubs will have over-lapping port indexes.
It checks that the virtual device with a matching port index is the same
speed as the passed in roothub.
There's also changes to the driver initialization and shutdown paths:
1. Make sure that the xhci_hcd pointer is shared across the two
usb_hcd structures. The xhci_hcd pointer is allocated and the
registers are mapped in when xhci_pci_setup() is called with the
primary HCD. When xhci_pci_setup() is called with the non-primary
HCD, the xhci_hcd pointer is stored.
2. Make sure to set the sg_tablesize for both usb_hcd structures. Set
the PCI DMA mask for the non-primary HCD to allow for 64-bit or 32-bit
DMA. (The PCI DMA mask is set from the primary HCD further down in
the xhci_pci_setup() function.)
3. Ensure that the host controller doesn't start kicking khubd in
response to port status changes before both usb_hcd structures are
registered. xhci_run() only starts the xHC running once it has been
called with the non-primary roothub. Similarly, the xhci_stop()
function only halts the host controller when it is called with the
non-primary HCD. Then on the second call, it resets and cleans up the
MSI-X irqs.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2010-12-17 03:21:10 +08:00
|
|
|
|
if (hcd->speed == HCD_USB3) {
|
|
|
|
|
|
ports = xhci->num_usb3_ports;
|
|
|
|
|
|
port_array = xhci->usb3_ports;
|
|
|
|
|
|
} else {
|
|
|
|
|
|
ports = xhci->num_usb2_ports;
|
|
|
|
|
|
port_array = xhci->usb2_ports;
|
2010-12-02 03:34:59 +08:00
|
|
|
|
}
|
2010-12-16 04:47:14 +08:00
|
|
|
|
bus_state = &xhci->bus_state[hcd_index(hcd)];
|
2009-04-28 10:57:12 +08:00
|
|
|
|
|
|
|
|
|
|
/* Initial status is no changes */
|
2010-05-13 01:20:34 +08:00
|
|
|
|
retval = (ports + 8) / 8;
|
|
|
|
|
|
memset(buf, 0, retval);
|
2009-04-28 10:57:12 +08:00
|
|
|
|
status = 0;
|
|
|
|
|
|
|
2010-10-14 22:23:00 +08:00
|
|
|
|
mask = PORT_CSC | PORT_PEC | PORT_OCC;
|
|
|
|
|
|
|
2009-04-28 10:57:12 +08:00
|
|
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
|
|
|
|
/* For each port, did anything change? If so, set that bit in buf. */
|
|
|
|
|
|
for (i = 0; i < ports; i++) {
|
2010-12-02 03:34:59 +08:00
|
|
|
|
temp = xhci_readl(xhci, port_array[i]);
|
2010-10-14 22:23:00 +08:00
|
|
|
|
if ((temp & mask) != 0 ||
|
2010-12-16 04:47:14 +08:00
|
|
|
|
(bus_state->port_c_suspend & 1 << i) ||
|
|
|
|
|
|
(bus_state->resume_done[i] && time_after_eq(
|
|
|
|
|
|
jiffies, bus_state->resume_done[i]))) {
|
2010-05-13 01:20:34 +08:00
|
|
|
|
buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
|
2009-04-28 10:57:12 +08:00
|
|
|
|
status = 1;
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
|
|
|
|
return status ? retval : 0;
|
|
|
|
|
|
}
|
2010-10-14 22:23:03 +08:00
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
|
|
|
|
|
|
|
|
int xhci_bus_suspend(struct usb_hcd *hcd)
|
|
|
|
|
|
{
|
|
|
|
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
2010-12-16 03:56:29 +08:00
|
|
|
|
int max_ports, port_index;
|
xhci: Register second xHCI roothub.
This patch changes the xHCI driver to allocate two roothubs. This touches
the driver initialization and shutdown paths, roothub emulation code, and
port status change event handlers. This is a rather large patch, but it
can't be broken up, or it would break git-bisect.
Make the xHCI driver register its own PCI probe function. This will call
the USB core to create the USB 2.0 roothub, and then create the USB 3.0
roothub. This gets the code for registering a shared roothub out of the
USB core, and allows other HCDs later to decide if and how many shared
roothubs they want to allocate.
Make sure the xHCI's reset method marks the xHCI host controller's primary
roothub as the USB 2.0 roothub. This ensures that the high speed bus will
be processed first when the PCI device is resumed, and any USB 3.0 devices
that have migrated over to high speed will migrate back after being reset.
This ensures that USB persist works with these odd devices.
The reset method will also mark the xHCI USB2 roothub as having an
integrated TT. Like EHCI host controllers with a "rate matching hub" the
xHCI USB 2.0 roothub doesn't have an OHCI or UHCI companion controller.
It doesn't really have a TT, but we'll lie and say it has an integrated
TT. We need to do this because the USB core will reject LS/FS devices
under a HS hub without a TT.
Other details:
-------------
The roothub emulation code is changed to return the correct number of
ports for the two roothubs. For the USB 3.0 roothub, it only reports the
USB 3.0 ports. For the USB 2.0 roothub, it reports all the LS/FS/HS
ports. The code to disable a port now checks the speed of the roothub,
and refuses to disable SuperSpeed ports under the USB 3.0 roothub.
The code for initializing a new device context must be changed to set the
proper roothub port number. Since we've split the xHCI host into two
roothubs, we can't just use the port number in the ancestor hub. Instead,
we loop through the array of hardware port status register speeds and find
the Nth port with a similar speed.
The port status change event handler is updated to figure out whether the
port that reported the change is a USB 3.0 port, or a non-SuperSpeed port.
Once it figures out the port speed, it kicks the proper roothub.
The function to find a slot ID based on the port index is updated to take
into account that the two roothubs will have over-lapping port indexes.
It checks that the virtual device with a matching port index is the same
speed as the passed in roothub.
There's also changes to the driver initialization and shutdown paths:
1. Make sure that the xhci_hcd pointer is shared across the two
usb_hcd structures. The xhci_hcd pointer is allocated and the
registers are mapped in when xhci_pci_setup() is called with the
primary HCD. When xhci_pci_setup() is called with the non-primary
HCD, the xhci_hcd pointer is stored.
2. Make sure to set the sg_tablesize for both usb_hcd structures. Set
the PCI DMA mask for the non-primary HCD to allow for 64-bit or 32-bit
DMA. (The PCI DMA mask is set from the primary HCD further down in
the xhci_pci_setup() function.)
3. Ensure that the host controller doesn't start kicking khubd in
response to port status changes before both usb_hcd structures are
registered. xhci_run() only starts the xHC running once it has been
called with the non-primary roothub. Similarly, the xhci_stop()
function only halts the host controller when it is called with the
non-primary HCD. Then on the second call, it resets and cleans up the
MSI-X irqs.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2010-12-17 03:21:10 +08:00
|
|
|
|
u32 __iomem **port_array;
|
2010-12-16 04:47:14 +08:00
|
|
|
|
struct xhci_bus_state *bus_state;
|
2010-10-14 22:23:03 +08:00
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
xhci: Register second xHCI roothub.
This patch changes the xHCI driver to allocate two roothubs. This touches
the driver initialization and shutdown paths, roothub emulation code, and
port status change event handlers. This is a rather large patch, but it
can't be broken up, or it would break git-bisect.
Make the xHCI driver register its own PCI probe function. This will call
the USB core to create the USB 2.0 roothub, and then create the USB 3.0
roothub. This gets the code for registering a shared roothub out of the
USB core, and allows other HCDs later to decide if and how many shared
roothubs they want to allocate.
Make sure the xHCI's reset method marks the xHCI host controller's primary
roothub as the USB 2.0 roothub. This ensures that the high speed bus will
be processed first when the PCI device is resumed, and any USB 3.0 devices
that have migrated over to high speed will migrate back after being reset.
This ensures that USB persist works with these odd devices.
The reset method will also mark the xHCI USB2 roothub as having an
integrated TT. Like EHCI host controllers with a "rate matching hub" the
xHCI USB 2.0 roothub doesn't have an OHCI or UHCI companion controller.
It doesn't really have a TT, but we'll lie and say it has an integrated
TT. We need to do this because the USB core will reject LS/FS devices
under a HS hub without a TT.
Other details:
-------------
The roothub emulation code is changed to return the correct number of
ports for the two roothubs. For the USB 3.0 roothub, it only reports the
USB 3.0 ports. For the USB 2.0 roothub, it reports all the LS/FS/HS
ports. The code to disable a port now checks the speed of the roothub,
and refuses to disable SuperSpeed ports under the USB 3.0 roothub.
The code for initializing a new device context must be changed to set the
proper roothub port number. Since we've split the xHCI host into two
roothubs, we can't just use the port number in the ancestor hub. Instead,
we loop through the array of hardware port status register speeds and find
the Nth port with a similar speed.
The port status change event handler is updated to figure out whether the
port that reported the change is a USB 3.0 port, or a non-SuperSpeed port.
Once it figures out the port speed, it kicks the proper roothub.
The function to find a slot ID based on the port index is updated to take
into account that the two roothubs will have over-lapping port indexes.
It checks that the virtual device with a matching port index is the same
speed as the passed in roothub.
There's also changes to the driver initialization and shutdown paths:
1. Make sure that the xhci_hcd pointer is shared across the two
usb_hcd structures. The xhci_hcd pointer is allocated and the
registers are mapped in when xhci_pci_setup() is called with the
primary HCD. When xhci_pci_setup() is called with the non-primary
HCD, the xhci_hcd pointer is stored.
2. Make sure to set the sg_tablesize for both usb_hcd structures. Set
the PCI DMA mask for the non-primary HCD to allow for 64-bit or 32-bit
DMA. (The PCI DMA mask is set from the primary HCD further down in
the xhci_pci_setup() function.)
3. Ensure that the host controller doesn't start kicking khubd in
response to port status changes before both usb_hcd structures are
registered. xhci_run() only starts the xHC running once it has been
called with the non-primary roothub. Similarly, the xhci_stop()
function only halts the host controller when it is called with the
non-primary HCD. Then on the second call, it resets and cleans up the
MSI-X irqs.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2010-12-17 03:21:10 +08:00
|
|
|
|
if (hcd->speed == HCD_USB3) {
|
|
|
|
|
|
max_ports = xhci->num_usb3_ports;
|
|
|
|
|
|
port_array = xhci->usb3_ports;
|
|
|
|
|
|
xhci_dbg(xhci, "suspend USB 3.0 root hub\n");
|
|
|
|
|
|
} else {
|
|
|
|
|
|
max_ports = xhci->num_usb2_ports;
|
|
|
|
|
|
port_array = xhci->usb2_ports;
|
|
|
|
|
|
xhci_dbg(xhci, "suspend USB 2.0 root hub\n");
|
2010-12-02 03:34:59 +08:00
|
|
|
|
}
|
2010-12-16 04:47:14 +08:00
|
|
|
|
bus_state = &xhci->bus_state[hcd_index(hcd)];
|
2010-10-14 22:23:03 +08:00
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
|
|
|
|
|
|
|
|
|
|
if (hcd->self.root_hub->do_remote_wakeup) {
|
2010-12-16 03:56:29 +08:00
|
|
|
|
port_index = max_ports;
|
|
|
|
|
|
while (port_index--) {
|
2010-12-16 04:47:14 +08:00
|
|
|
|
if (bus_state->resume_done[port_index] != 0) {
|
2010-10-14 22:23:03 +08:00
|
|
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
|
|
|
|
xhci_dbg(xhci, "suspend failed because "
|
|
|
|
|
|
"port %d is resuming\n",
|
2010-12-16 03:56:29 +08:00
|
|
|
|
port_index + 1);
|
2010-10-14 22:23:03 +08:00
|
|
|
|
return -EBUSY;
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2010-12-16 03:56:29 +08:00
|
|
|
|
port_index = max_ports;
|
2010-12-16 04:47:14 +08:00
|
|
|
|
bus_state->bus_suspended = 0;
|
2010-12-16 03:56:29 +08:00
|
|
|
|
while (port_index--) {
|
2010-10-14 22:23:03 +08:00
|
|
|
|
/* suspend the port if the port is not suspended */
|
|
|
|
|
|
u32 t1, t2;
|
|
|
|
|
|
int slot_id;
|
|
|
|
|
|
|
2010-12-02 03:34:59 +08:00
|
|
|
|
t1 = xhci_readl(xhci, port_array[port_index]);
|
2010-10-14 22:23:03 +08:00
|
|
|
|
t2 = xhci_port_state_to_neutral(t1);
|
|
|
|
|
|
|
|
|
|
|
|
if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
|
2010-12-16 03:56:29 +08:00
|
|
|
|
xhci_dbg(xhci, "port %d not suspended\n", port_index);
|
2010-12-17 02:49:09 +08:00
|
|
|
|
slot_id = xhci_find_slot_id_by_port(hcd, xhci,
|
2010-12-16 03:56:29 +08:00
|
|
|
|
port_index + 1);
|
2010-10-14 22:23:03 +08:00
|
|
|
|
if (slot_id) {
|
|
|
|
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
|
|
|
|
xhci_stop_device(xhci, slot_id, 1);
|
|
|
|
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
|
|
|
|
}
|
|
|
|
|
|
t2 &= ~PORT_PLS_MASK;
|
|
|
|
|
|
t2 |= PORT_LINK_STROBE | XDEV_U3;
|
2010-12-16 04:47:14 +08:00
|
|
|
|
set_bit(port_index, &bus_state->bus_suspended);
|
2010-10-14 22:23:03 +08:00
|
|
|
|
}
|
|
|
|
|
|
if (hcd->self.root_hub->do_remote_wakeup) {
|
|
|
|
|
|
if (t1 & PORT_CONNECT) {
|
|
|
|
|
|
t2 |= PORT_WKOC_E | PORT_WKDISC_E;
|
|
|
|
|
|
t2 &= ~PORT_WKCONN_E;
|
|
|
|
|
|
} else {
|
|
|
|
|
|
t2 |= PORT_WKOC_E | PORT_WKCONN_E;
|
|
|
|
|
|
t2 &= ~PORT_WKDISC_E;
|
|
|
|
|
|
}
|
|
|
|
|
|
} else
|
|
|
|
|
|
t2 &= ~PORT_WAKE_BITS;
|
|
|
|
|
|
|
|
|
|
|
|
t1 = xhci_port_state_to_neutral(t1);
|
|
|
|
|
|
if (t1 != t2)
|
2010-12-02 03:34:59 +08:00
|
|
|
|
xhci_writel(xhci, t2, port_array[port_index]);
|
2010-10-14 22:23:03 +08:00
|
|
|
|
|
|
|
|
|
|
if (DEV_HIGHSPEED(t1)) {
|
|
|
|
|
|
/* enable remote wake up for USB 2.0 */
|
|
|
|
|
|
u32 __iomem *addr;
|
|
|
|
|
|
u32 tmp;
|
|
|
|
|
|
|
2010-12-02 03:34:59 +08:00
|
|
|
|
/* Add one to the port status register address to get
|
|
|
|
|
|
* the port power control register address.
|
|
|
|
|
|
*/
|
|
|
|
|
|
addr = port_array[port_index] + 1;
|
2010-10-14 22:23:03 +08:00
|
|
|
|
tmp = xhci_readl(xhci, addr);
|
|
|
|
|
|
tmp |= PORT_RWE;
|
|
|
|
|
|
xhci_writel(xhci, tmp, addr);
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
hcd->state = HC_STATE_SUSPENDED;
|
2010-12-16 04:47:14 +08:00
|
|
|
|
bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
|
2010-10-14 22:23:03 +08:00
|
|
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
int xhci_bus_resume(struct usb_hcd *hcd)
|
|
|
|
|
|
{
|
|
|
|
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
2010-12-16 03:56:29 +08:00
|
|
|
|
int max_ports, port_index;
|
xhci: Register second xHCI roothub.
This patch changes the xHCI driver to allocate two roothubs. This touches
the driver initialization and shutdown paths, roothub emulation code, and
port status change event handlers. This is a rather large patch, but it
can't be broken up, or it would break git-bisect.
Make the xHCI driver register its own PCI probe function. This will call
the USB core to create the USB 2.0 roothub, and then create the USB 3.0
roothub. This gets the code for registering a shared roothub out of the
USB core, and allows other HCDs later to decide if and how many shared
roothubs they want to allocate.
Make sure the xHCI's reset method marks the xHCI host controller's primary
roothub as the USB 2.0 roothub. This ensures that the high speed bus will
be processed first when the PCI device is resumed, and any USB 3.0 devices
that have migrated over to high speed will migrate back after being reset.
This ensures that USB persist works with these odd devices.
The reset method will also mark the xHCI USB2 roothub as having an
integrated TT. Like EHCI host controllers with a "rate matching hub" the
xHCI USB 2.0 roothub doesn't have an OHCI or UHCI companion controller.
It doesn't really have a TT, but we'll lie and say it has an integrated
TT. We need to do this because the USB core will reject LS/FS devices
under a HS hub without a TT.
Other details:
-------------
The roothub emulation code is changed to return the correct number of
ports for the two roothubs. For the USB 3.0 roothub, it only reports the
USB 3.0 ports. For the USB 2.0 roothub, it reports all the LS/FS/HS
ports. The code to disable a port now checks the speed of the roothub,
and refuses to disable SuperSpeed ports under the USB 3.0 roothub.
The code for initializing a new device context must be changed to set the
proper roothub port number. Since we've split the xHCI host into two
roothubs, we can't just use the port number in the ancestor hub. Instead,
we loop through the array of hardware port status register speeds and find
the Nth port with a similar speed.
The port status change event handler is updated to figure out whether the
port that reported the change is a USB 3.0 port, or a non-SuperSpeed port.
Once it figures out the port speed, it kicks the proper roothub.
The function to find a slot ID based on the port index is updated to take
into account that the two roothubs will have over-lapping port indexes.
It checks that the virtual device with a matching port index is the same
speed as the passed in roothub.
There's also changes to the driver initialization and shutdown paths:
1. Make sure that the xhci_hcd pointer is shared across the two
usb_hcd structures. The xhci_hcd pointer is allocated and the
registers are mapped in when xhci_pci_setup() is called with the
primary HCD. When xhci_pci_setup() is called with the non-primary
HCD, the xhci_hcd pointer is stored.
2. Make sure to set the sg_tablesize for both usb_hcd structures. Set
the PCI DMA mask for the non-primary HCD to allow for 64-bit or 32-bit
DMA. (The PCI DMA mask is set from the primary HCD further down in
the xhci_pci_setup() function.)
3. Ensure that the host controller doesn't start kicking khubd in
response to port status changes before both usb_hcd structures are
registered. xhci_run() only starts the xHC running once it has been
called with the non-primary roothub. Similarly, the xhci_stop()
function only halts the host controller when it is called with the
non-primary HCD. Then on the second call, it resets and cleans up the
MSI-X irqs.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2010-12-17 03:21:10 +08:00
|
|
|
|
u32 __iomem **port_array;
|
2010-12-16 04:47:14 +08:00
|
|
|
|
struct xhci_bus_state *bus_state;
|
2010-10-14 22:23:03 +08:00
|
|
|
|
u32 temp;
|
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
xhci: Register second xHCI roothub.
This patch changes the xHCI driver to allocate two roothubs. This touches
the driver initialization and shutdown paths, roothub emulation code, and
port status change event handlers. This is a rather large patch, but it
can't be broken up, or it would break git-bisect.
Make the xHCI driver register its own PCI probe function. This will call
the USB core to create the USB 2.0 roothub, and then create the USB 3.0
roothub. This gets the code for registering a shared roothub out of the
USB core, and allows other HCDs later to decide if and how many shared
roothubs they want to allocate.
Make sure the xHCI's reset method marks the xHCI host controller's primary
roothub as the USB 2.0 roothub. This ensures that the high speed bus will
be processed first when the PCI device is resumed, and any USB 3.0 devices
that have migrated over to high speed will migrate back after being reset.
This ensures that USB persist works with these odd devices.
The reset method will also mark the xHCI USB2 roothub as having an
integrated TT. Like EHCI host controllers with a "rate matching hub" the
xHCI USB 2.0 roothub doesn't have an OHCI or UHCI companion controller.
It doesn't really have a TT, but we'll lie and say it has an integrated
TT. We need to do this because the USB core will reject LS/FS devices
under a HS hub without a TT.
Other details:
-------------
The roothub emulation code is changed to return the correct number of
ports for the two roothubs. For the USB 3.0 roothub, it only reports the
USB 3.0 ports. For the USB 2.0 roothub, it reports all the LS/FS/HS
ports. The code to disable a port now checks the speed of the roothub,
and refuses to disable SuperSpeed ports under the USB 3.0 roothub.
The code for initializing a new device context must be changed to set the
proper roothub port number. Since we've split the xHCI host into two
roothubs, we can't just use the port number in the ancestor hub. Instead,
we loop through the array of hardware port status register speeds and find
the Nth port with a similar speed.
The port status change event handler is updated to figure out whether the
port that reported the change is a USB 3.0 port, or a non-SuperSpeed port.
Once it figures out the port speed, it kicks the proper roothub.
The function to find a slot ID based on the port index is updated to take
into account that the two roothubs will have over-lapping port indexes.
It checks that the virtual device with a matching port index is the same
speed as the passed in roothub.
There's also changes to the driver initialization and shutdown paths:
1. Make sure that the xhci_hcd pointer is shared across the two
usb_hcd structures. The xhci_hcd pointer is allocated and the
registers are mapped in when xhci_pci_setup() is called with the
primary HCD. When xhci_pci_setup() is called with the non-primary
HCD, the xhci_hcd pointer is stored.
2. Make sure to set the sg_tablesize for both usb_hcd structures. Set
the PCI DMA mask for the non-primary HCD to allow for 64-bit or 32-bit
DMA. (The PCI DMA mask is set from the primary HCD further down in
the xhci_pci_setup() function.)
3. Ensure that the host controller doesn't start kicking khubd in
response to port status changes before both usb_hcd structures are
registered. xhci_run() only starts the xHC running once it has been
called with the non-primary roothub. Similarly, the xhci_stop()
function only halts the host controller when it is called with the
non-primary HCD. Then on the second call, it resets and cleans up the
MSI-X irqs.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2010-12-17 03:21:10 +08:00
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|
|
|
if (hcd->speed == HCD_USB3) {
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max_ports = xhci->num_usb3_ports;
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port_array = xhci->usb3_ports;
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xhci_dbg(xhci, "resume USB 3.0 root hub\n");
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} else {
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max_ports = xhci->num_usb2_ports;
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port_array = xhci->usb2_ports;
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xhci_dbg(xhci, "resume USB 2.0 root hub\n");
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2010-12-02 03:34:59 +08:00
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}
|
2010-12-16 04:47:14 +08:00
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bus_state = &xhci->bus_state[hcd_index(hcd)];
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2010-10-14 22:23:03 +08:00
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2010-12-16 04:47:14 +08:00
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if (time_before(jiffies, bus_state->next_statechange))
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2010-10-14 22:23:03 +08:00
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msleep(5);
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spin_lock_irqsave(&xhci->lock, flags);
|
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|
|
|
|
if (!HCD_HW_ACCESSIBLE(hcd)) {
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|
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spin_unlock_irqrestore(&xhci->lock, flags);
|
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return -ESHUTDOWN;
|
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}
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/* delay the irqs */
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|
temp = xhci_readl(xhci, &xhci->op_regs->command);
|
|
|
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temp &= ~CMD_EIE;
|
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|
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|
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xhci_writel(xhci, temp, &xhci->op_regs->command);
|
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|
|
|
2010-12-16 03:56:29 +08:00
|
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|
|
port_index = max_ports;
|
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|
|
|
|
while (port_index--) {
|
2010-10-14 22:23:03 +08:00
|
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|
|
/* Check whether need resume ports. If needed
|
|
|
|
|
|
resume port and disable remote wakeup */
|
|
|
|
|
|
u32 temp;
|
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|
|
|
|
int slot_id;
|
|
|
|
|
|
|
2010-12-02 03:34:59 +08:00
|
|
|
|
temp = xhci_readl(xhci, port_array[port_index]);
|
2010-10-14 22:23:03 +08:00
|
|
|
|
if (DEV_SUPERSPEED(temp))
|
|
|
|
|
|
temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
|
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|
|
|
|
else
|
|
|
|
|
|
temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
|
2010-12-16 04:47:14 +08:00
|
|
|
|
if (test_bit(port_index, &bus_state->bus_suspended) &&
|
2010-10-14 22:23:03 +08:00
|
|
|
|
(temp & PORT_PLS_MASK)) {
|
|
|
|
|
|
if (DEV_SUPERSPEED(temp)) {
|
|
|
|
|
|
temp = xhci_port_state_to_neutral(temp);
|
|
|
|
|
|
temp &= ~PORT_PLS_MASK;
|
|
|
|
|
|
temp |= PORT_LINK_STROBE | XDEV_U0;
|
2010-12-02 03:34:59 +08:00
|
|
|
|
xhci_writel(xhci, temp, port_array[port_index]);
|
2010-10-14 22:23:03 +08:00
|
|
|
|
} else {
|
|
|
|
|
|
temp = xhci_port_state_to_neutral(temp);
|
|
|
|
|
|
temp &= ~PORT_PLS_MASK;
|
|
|
|
|
|
temp |= PORT_LINK_STROBE | XDEV_RESUME;
|
2010-12-02 03:34:59 +08:00
|
|
|
|
xhci_writel(xhci, temp, port_array[port_index]);
|
2010-10-14 22:23:03 +08:00
|
|
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
|
|
|
|
msleep(20);
|
|
|
|
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
|
|
|
|
|
2010-12-02 03:34:59 +08:00
|
|
|
|
temp = xhci_readl(xhci, port_array[port_index]);
|
2010-10-14 22:23:03 +08:00
|
|
|
|
temp = xhci_port_state_to_neutral(temp);
|
|
|
|
|
|
temp &= ~PORT_PLS_MASK;
|
|
|
|
|
|
temp |= PORT_LINK_STROBE | XDEV_U0;
|
2010-12-02 03:34:59 +08:00
|
|
|
|
xhci_writel(xhci, temp, port_array[port_index]);
|
2010-10-14 22:23:03 +08:00
|
|
|
|
}
|
2010-12-17 02:49:09 +08:00
|
|
|
|
slot_id = xhci_find_slot_id_by_port(hcd,
|
|
|
|
|
|
xhci, port_index + 1);
|
2010-10-14 22:23:03 +08:00
|
|
|
|
if (slot_id)
|
|
|
|
|
|
xhci_ring_device(xhci, slot_id);
|
|
|
|
|
|
} else
|
2010-12-02 03:34:59 +08:00
|
|
|
|
xhci_writel(xhci, temp, port_array[port_index]);
|
2010-10-14 22:23:03 +08:00
|
|
|
|
|
|
|
|
|
|
if (DEV_HIGHSPEED(temp)) {
|
|
|
|
|
|
/* disable remote wake up for USB 2.0 */
|
|
|
|
|
|
u32 __iomem *addr;
|
|
|
|
|
|
u32 tmp;
|
|
|
|
|
|
|
2010-12-02 03:34:59 +08:00
|
|
|
|
/* Add one to the port status register address to get
|
|
|
|
|
|
* the port power control register address.
|
|
|
|
|
|
*/
|
|
|
|
|
|
addr = port_array[port_index] + 1;
|
2010-10-14 22:23:03 +08:00
|
|
|
|
tmp = xhci_readl(xhci, addr);
|
|
|
|
|
|
tmp &= ~PORT_RWE;
|
|
|
|
|
|
xhci_writel(xhci, tmp, addr);
|
|
|
|
|
|
}
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
(void) xhci_readl(xhci, &xhci->op_regs->command);
|
|
|
|
|
|
|
2010-12-16 04:47:14 +08:00
|
|
|
|
bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
|
2010-10-14 22:23:03 +08:00
|
|
|
|
/* re-enable irqs */
|
|
|
|
|
|
temp = xhci_readl(xhci, &xhci->op_regs->command);
|
|
|
|
|
|
temp |= CMD_EIE;
|
|
|
|
|
|
xhci_writel(xhci, temp, &xhci->op_regs->command);
|
|
|
|
|
|
temp = xhci_readl(xhci, &xhci->op_regs->command);
|
|
|
|
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
}
|
|
|
|
|
|
|
2010-10-16 05:59:15 +08:00
|
|
|
|
#endif /* CONFIG_PM */
|