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arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
/*
ARM: socfpga: dts: rename socdk board file to socdk_sdmmc Rename the socfpga_arria10_socdk board file to socfpga_arria10_socdk_sdmmc as Arria 10 devkit cannot support SDMMC and QSPI at the same time. Thus we will need to have 2 separate board files, one for SDMMC and one for QSPI. We also add a new base board dtsi file, socfpga_arria10_socdk.dtsi so that we use common peripherals for each flavor of the devkits. Add the sdmmc node to the socfpga_arria10_socdk_sdmmc.dts board file. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-03-10 11:57:04 +08:00
* Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/dts-v1/;
ARM: socfpga: dts: rename socdk board file to socdk_sdmmc Rename the socfpga_arria10_socdk board file to socfpga_arria10_socdk_sdmmc as Arria 10 devkit cannot support SDMMC and QSPI at the same time. Thus we will need to have 2 separate board files, one for SDMMC and one for QSPI. We also add a new base board dtsi file, socfpga_arria10_socdk.dtsi so that we use common peripherals for each flavor of the devkits. Add the sdmmc node to the socfpga_arria10_socdk_sdmmc.dts board file. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-03-10 11:57:04 +08:00
#include "socfpga_arria10_socdk.dtsi"
arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2014-09-05 05:45:56 +08:00
ARM: socfpga: dts: rename socdk board file to socdk_sdmmc Rename the socfpga_arria10_socdk board file to socfpga_arria10_socdk_sdmmc as Arria 10 devkit cannot support SDMMC and QSPI at the same time. Thus we will need to have 2 separate board files, one for SDMMC and one for QSPI. We also add a new base board dtsi file, socfpga_arria10_socdk.dtsi so that we use common peripherals for each flavor of the devkits. Add the sdmmc node to the socfpga_arria10_socdk_sdmmc.dts board file. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-03-10 11:57:04 +08:00
&mmc {
ARM: socfpga: dts: enable UART1 for the debug uart Arria10 devkit is using UART1 for the debug uart port. Remove unused aliases. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: Add removal of unused aliases
2015-04-03 02:26:35 +08:00
status = "okay";
ARM: socfpga: dts: rename socdk board file to socdk_sdmmc Rename the socfpga_arria10_socdk board file to socfpga_arria10_socdk_sdmmc as Arria 10 devkit cannot support SDMMC and QSPI at the same time. Thus we will need to have 2 separate board files, one for SDMMC and one for QSPI. We also add a new base board dtsi file, socfpga_arria10_socdk.dtsi so that we use common peripherals for each flavor of the devkits. Add the sdmmc node to the socfpga_arria10_socdk_sdmmc.dts board file. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-03-10 11:57:04 +08:00
num-slots = <1>;
broken-cd;
bus-width = <4>;
ARM: socfpga: dts: enable UART1 for the debug uart Arria10 devkit is using UART1 for the debug uart port. Remove unused aliases. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- v2: Add removal of unused aliases
2015-04-03 02:26:35 +08:00
};