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OpenCloudOS-Kernel/arch/arm/boot/dts/tegra124.dtsi

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ARM: tegra: add clock properties for devices of Tegra124 This patch adds clock properties for devices in the DT for basic support of Tegra124 SoC. Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren, added missing unit address to "clock" node] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 15:47:40 +08:00
#include <dt-bindings/clock/tegra124-car.h>
ARM: tegra: add GPIO controller to tegra124.dtsi The Tegra124 GPIO controller is identical to Tegra30, so copy the DT node from tegra30.dtsi to tegra124.dtsi. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2013-08-06 07:10:02 +08:00
#include <dt-bindings/gpio/tegra-gpio.h>
ARM: tegra: add default pinctrl nodes for Venice2 Add the default pinmux configuration for the Tegra124 based Venice2 platform. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-09 18:33:51 +08:00
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
ARM: tegra: Add initial device tree for Tegra124 Initial support for Tegra 124 SoC. This is expected to be included in the board DTS files. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 12:50:05 +08:00
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
/ {
compatible = "nvidia,tegra124";
interrupt-parent = <&gic>;
gic: interrupt-controller@50041000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x50041000 0x1000>,
<0x50042000 0x1000>,
<0x50044000 0x2000>,
<0x50046000 0x2000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
timer@60005000 {
compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
reg = <0x60005000 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
ARM: tegra: add clock properties for devices of Tegra124 This patch adds clock properties for devices in the DT for basic support of Tegra124 SoC. Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren, added missing unit address to "clock" node] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 15:47:40 +08:00
clocks = <&tegra_car TEGRA124_CLK_TIMER>;
};
tegra_car: clock@60006000 {
compatible = "nvidia,tegra124-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
ARM: tegra: add reset properties to Tegra124 DTs The DT bindings now require module resets to be specified. The earlier patches which added these nodes were originally written before that requirement. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2013-11-08 03:20:57 +08:00
#reset-cells = <1>;
ARM: tegra: Add initial device tree for Tegra124 Initial support for Tegra 124 SoC. This is expected to be included in the board DTS files. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 12:50:05 +08:00
};
ARM: tegra: add GPIO controller to tegra124.dtsi The Tegra124 GPIO controller is identical to Tegra30, so copy the DT node from tegra30.dtsi to tegra124.dtsi. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2013-08-06 07:10:02 +08:00
gpio: gpio@6000d000 {
compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
reg = <0x6000d000 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};
ARM: tegra: add APB DMA controller to Tegra124 DT Instantiate the APB DMA controller in the Tegra124 DT, and add all DMA-related properties to other DT nodes that rely on (reference) the DMA controller's node. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2013-11-16 03:22:53 +08:00
apbdma: dma@60020000 {
compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
reg = <0x60020000 0x1400>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
resets = <&tegra_car 34>;
reset-names = "dma";
#dma-cells = <1>;
};
ARM: tegra: add Tegra124 pinmux node to DT Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked by: Laxman Dewangan <ldewangan@nvidia.com>
2013-11-02 04:03:59 +08:00
pinmux: pinmux@70000868 {
compatible = "nvidia,tegra124-pinmux";
reg = <0x70000868 0x164>, /* Pad control registers */
<0x70003000 0x434>; /* Mux registers */
};
ARM: tegra: Add initial device tree for Tegra124 Initial support for Tegra 124 SoC. This is expected to be included in the board DTS files. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 12:50:05 +08:00
/*
* There are two serial driver i.e. 8250 based simple serial
* driver and APB DMA based serial driver for higher baudrate
* and performace. To enable the 8250 based driver, the compatible
* is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
* the APB DMA based serial driver, the comptible is
* "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
*/
serial@70006000 {
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
reg = <0x70006000 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
ARM: tegra: add clock properties for devices of Tegra124 This patch adds clock properties for devices in the DT for basic support of Tegra124 SoC. Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren, added missing unit address to "clock" node] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 15:47:40 +08:00
clocks = <&tegra_car TEGRA124_CLK_UARTA>;
ARM: tegra: add reset properties to Tegra124 DTs The DT bindings now require module resets to be specified. The earlier patches which added these nodes were originally written before that requirement. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2013-11-08 03:20:57 +08:00
resets = <&tegra_car 6>;
reset-names = "serial";
ARM: tegra: add APB DMA controller to Tegra124 DT Instantiate the APB DMA controller in the Tegra124 DT, and add all DMA-related properties to other DT nodes that rely on (reference) the DMA controller's node. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2013-11-16 03:22:53 +08:00
dmas = <&apbdma 8>, <&apbdma 8>;
dma-names = "rx", "tx";
ARM: tegra: Add initial device tree for Tegra124 Initial support for Tegra 124 SoC. This is expected to be included in the board DTS files. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 12:50:05 +08:00
status = "disabled";
};
serial@70006040 {
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
reg = <0x70006040 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
ARM: tegra: add clock properties for devices of Tegra124 This patch adds clock properties for devices in the DT for basic support of Tegra124 SoC. Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren, added missing unit address to "clock" node] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 15:47:40 +08:00
clocks = <&tegra_car TEGRA124_CLK_UARTB>;
ARM: tegra: add reset properties to Tegra124 DTs The DT bindings now require module resets to be specified. The earlier patches which added these nodes were originally written before that requirement. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2013-11-08 03:20:57 +08:00
resets = <&tegra_car 7>;
reset-names = "serial";
ARM: tegra: add APB DMA controller to Tegra124 DT Instantiate the APB DMA controller in the Tegra124 DT, and add all DMA-related properties to other DT nodes that rely on (reference) the DMA controller's node. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2013-11-16 03:22:53 +08:00
dmas = <&apbdma 9>, <&apbdma 9>;
dma-names = "rx", "tx";
ARM: tegra: Add initial device tree for Tegra124 Initial support for Tegra 124 SoC. This is expected to be included in the board DTS files. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 12:50:05 +08:00
status = "disabled";
};
serial@70006200 {
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
reg = <0x70006200 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
ARM: tegra: add clock properties for devices of Tegra124 This patch adds clock properties for devices in the DT for basic support of Tegra124 SoC. Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren, added missing unit address to "clock" node] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 15:47:40 +08:00
clocks = <&tegra_car TEGRA124_CLK_UARTC>;
ARM: tegra: add reset properties to Tegra124 DTs The DT bindings now require module resets to be specified. The earlier patches which added these nodes were originally written before that requirement. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2013-11-08 03:20:57 +08:00
resets = <&tegra_car 55>;
reset-names = "serial";
ARM: tegra: add APB DMA controller to Tegra124 DT Instantiate the APB DMA controller in the Tegra124 DT, and add all DMA-related properties to other DT nodes that rely on (reference) the DMA controller's node. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2013-11-16 03:22:53 +08:00
dmas = <&apbdma 10>, <&apbdma 10>;
dma-names = "rx", "tx";
ARM: tegra: Add initial device tree for Tegra124 Initial support for Tegra 124 SoC. This is expected to be included in the board DTS files. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 12:50:05 +08:00
status = "disabled";
};
serial@70006300 {
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
reg = <0x70006300 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
ARM: tegra: add clock properties for devices of Tegra124 This patch adds clock properties for devices in the DT for basic support of Tegra124 SoC. Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren, added missing unit address to "clock" node] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 15:47:40 +08:00
clocks = <&tegra_car TEGRA124_CLK_UARTD>;
ARM: tegra: add reset properties to Tegra124 DTs The DT bindings now require module resets to be specified. The earlier patches which added these nodes were originally written before that requirement. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2013-11-08 03:20:57 +08:00
resets = <&tegra_car 65>;
reset-names = "serial";
ARM: tegra: add APB DMA controller to Tegra124 DT Instantiate the APB DMA controller in the Tegra124 DT, and add all DMA-related properties to other DT nodes that rely on (reference) the DMA controller's node. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2013-11-16 03:22:53 +08:00
dmas = <&apbdma 19>, <&apbdma 19>;
dma-names = "rx", "tx";
ARM: tegra: Add initial device tree for Tegra124 Initial support for Tegra 124 SoC. This is expected to be included in the board DTS files. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 12:50:05 +08:00
status = "disabled";
};
serial@70006400 {
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
reg = <0x70006400 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
ARM: tegra: add clock properties for devices of Tegra124 This patch adds clock properties for devices in the DT for basic support of Tegra124 SoC. Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren, added missing unit address to "clock" node] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 15:47:40 +08:00
clocks = <&tegra_car TEGRA124_CLK_UARTE>;
ARM: tegra: add reset properties to Tegra124 DTs The DT bindings now require module resets to be specified. The earlier patches which added these nodes were originally written before that requirement. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2013-11-08 03:20:57 +08:00
resets = <&tegra_car 66>;
reset-names = "serial";
ARM: tegra: add APB DMA controller to Tegra124 DT Instantiate the APB DMA controller in the Tegra124 DT, and add all DMA-related properties to other DT nodes that rely on (reference) the DMA controller's node. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
2013-11-16 03:22:53 +08:00
dmas = <&apbdma 20>, <&apbdma 20>;
dma-names = "rx", "tx";
ARM: tegra: Add initial device tree for Tegra124 Initial support for Tegra 124 SoC. This is expected to be included in the board DTS files. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 12:50:05 +08:00
status = "disabled";
};
ARM: tegra: Add Tegra124 PWM support The PWM controller on Tegra124 is the same as the one on earlier SoC generations. Signed-off-by: Thierry Reding <treding@nvidia.com> [swarren, added reset properties] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-11-19 00:00:34 +08:00
pwm@7000a000 {
compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
#pwm-cells = <2>;
clocks = <&tegra_car TEGRA124_CLK_PWM>;
resets = <&tegra_car 17>;
reset-names = "pwm";
status = "disabled";
};
ARM: tegra: add I2C controllers to Tegra124 DT Tegra124 has 6 I2C controllers. The first 5 have identical configuration to Tegra114, but the sixth obviously has different interrupt/... IDs. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-04 07:29:04 +08:00
i2c@7000c000 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x7000c000 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA124_CLK_I2C1>;
clock-names = "div-clk";
resets = <&tegra_car 12>;
reset-names = "i2c";
dmas = <&apbdma 21>, <&apbdma 21>;
dma-names = "rx", "tx";
status = "disabled";
};
i2c@7000c400 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x7000c400 0x100>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA124_CLK_I2C2>;
clock-names = "div-clk";
resets = <&tegra_car 54>;
reset-names = "i2c";
dmas = <&apbdma 22>, <&apbdma 22>;
dma-names = "rx", "tx";
status = "disabled";
};
i2c@7000c500 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x7000c500 0x100>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA124_CLK_I2C3>;
clock-names = "div-clk";
resets = <&tegra_car 67>;
reset-names = "i2c";
dmas = <&apbdma 23>, <&apbdma 23>;
dma-names = "rx", "tx";
status = "disabled";
};
i2c@7000c700 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x7000c700 0x100>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA124_CLK_I2C4>;
clock-names = "div-clk";
resets = <&tegra_car 103>;
reset-names = "i2c";
dmas = <&apbdma 26>, <&apbdma 26>;
dma-names = "rx", "tx";
status = "disabled";
};
i2c@7000d000 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x7000d000 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA124_CLK_I2C5>;
clock-names = "div-clk";
resets = <&tegra_car 47>;
reset-names = "i2c";
dmas = <&apbdma 24>, <&apbdma 24>;
dma-names = "rx", "tx";
status = "disabled";
};
i2c@7000d100 {
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
reg = <0x7000d100 0x100>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car TEGRA124_CLK_I2C6>;
clock-names = "div-clk";
resets = <&tegra_car 166>;
reset-names = "i2c";
dmas = <&apbdma 30>, <&apbdma 30>;
dma-names = "rx", "tx";
status = "disabled";
};
ARM: tegra: Add initial device tree for Tegra124 Initial support for Tegra 124 SoC. This is expected to be included in the board DTS files. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 12:50:05 +08:00
rtc@7000e000 {
compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
ARM: tegra: add clock properties for devices of Tegra124 This patch adds clock properties for devices in the DT for basic support of Tegra124 SoC. Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren, added missing unit address to "clock" node] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 15:47:40 +08:00
clocks = <&tegra_car TEGRA124_CLK_RTC>;
ARM: tegra: Add initial device tree for Tegra124 Initial support for Tegra 124 SoC. This is expected to be included in the board DTS files. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 12:50:05 +08:00
};
pmc@7000e400 {
compatible = "nvidia,tegra124-pmc";
reg = <0x7000e400 0x400>;
ARM: tegra: add clock properties for devices of Tegra124 This patch adds clock properties for devices in the DT for basic support of Tegra124 SoC. Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren, added missing unit address to "clock" node] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 15:47:40 +08:00
clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
ARM: tegra: Add initial device tree for Tegra124 Initial support for Tegra 124 SoC. This is expected to be included in the board DTS files. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 12:50:05 +08:00
};
ARM: tegra: add MMC controllers to Tegra124 DT Tegra124 has 4 MMC controllers just like previous versions of the SoC. Note that there are some non-backwards-compatible HW differences, and hence a new DT compatible value must be used to describe the HW. Also enable the relevant controllers in the Venice2 board DT. power-gpios property suggested by Thierry Reding. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com>
2013-11-01 07:23:05 +08:00
sdhci@700b0000 {
compatible = "nvidia,tegra124-sdhci";
reg = <0x700b0000 0x200>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
resets = <&tegra_car 14>;
reset-names = "sdhci";
status = "disable";
};
sdhci@700b0200 {
compatible = "nvidia,tegra124-sdhci";
reg = <0x700b0200 0x200>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
resets = <&tegra_car 9>;
reset-names = "sdhci";
status = "disable";
};
sdhci@700b0400 {
compatible = "nvidia,tegra124-sdhci";
reg = <0x700b0400 0x200>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
resets = <&tegra_car 69>;
reset-names = "sdhci";
status = "disable";
};
sdhci@700b0600 {
compatible = "nvidia,tegra124-sdhci";
reg = <0x700b0600 0x200>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
resets = <&tegra_car 15>;
reset-names = "sdhci";
status = "disable";
};
ARM: tegra: add audio-related device to Tegra124 DT Tegra124 contains a similar set of audio devices to previous Tegra chips. Specifically, there is an AHUB device which contains DMA FIFOs and audio routing, and which hosts various audio-related components such as I2S controllers. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-12-05 06:05:51 +08:00
ahub@70300000 {
compatible = "nvidia,tegra124-ahub";
reg = <0x70300000 0x200>,
<0x70300800 0x800>,
<0x70300200 0x600>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
<&tegra_car TEGRA124_CLK_APBIF>;
clock-names = "d_audio", "apbif";
resets = <&tegra_car 106>, /* d_audio */
<&tegra_car 107>, /* apbif */
<&tegra_car 30>, /* i2s0 */
<&tegra_car 11>, /* i2s1 */
<&tegra_car 18>, /* i2s2 */
<&tegra_car 101>, /* i2s3 */
<&tegra_car 102>, /* i2s4 */
<&tegra_car 108>, /* dam0 */
<&tegra_car 109>, /* dam1 */
<&tegra_car 110>, /* dam2 */
<&tegra_car 10>, /* spdif */
<&tegra_car 153>, /* amx */
<&tegra_car 185>, /* amx1 */
<&tegra_car 154>, /* adx */
<&tegra_car 180>, /* adx1 */
<&tegra_car 186>, /* afc0 */
<&tegra_car 187>, /* afc1 */
<&tegra_car 188>, /* afc2 */
<&tegra_car 189>, /* afc3 */
<&tegra_car 190>, /* afc4 */
<&tegra_car 191>; /* afc5 */
reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
"i2s3", "i2s4", "dam0", "dam1", "dam2",
"spdif", "amx", "amx1", "adx", "adx1",
"afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
dmas = <&apbdma 1>, <&apbdma 1>,
<&apbdma 2>, <&apbdma 2>,
<&apbdma 3>, <&apbdma 3>,
<&apbdma 4>, <&apbdma 4>,
<&apbdma 6>, <&apbdma 6>,
<&apbdma 7>, <&apbdma 7>,
<&apbdma 12>, <&apbdma 12>,
<&apbdma 13>, <&apbdma 13>,
<&apbdma 14>, <&apbdma 14>,
<&apbdma 29>, <&apbdma 29>;
dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
"rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
"rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
"rx9", "tx9";
ranges;
#address-cells = <1>;
#size-cells = <1>;
tegra_i2s0: i2s@70301000 {
compatible = "nvidia,tegra124-i2s";
reg = <0x70301000 0x100>;
nvidia,ahub-cif-ids = <4 4>;
clocks = <&tegra_car TEGRA124_CLK_I2S0>;
resets = <&tegra_car 30>;
reset-names = "i2s";
status = "disabled";
};
tegra_i2s1: i2s@70301100 {
compatible = "nvidia,tegra124-i2s";
reg = <0x70301100 0x100>;
nvidia,ahub-cif-ids = <5 5>;
clocks = <&tegra_car TEGRA124_CLK_I2S1>;
resets = <&tegra_car 11>;
reset-names = "i2s";
status = "disabled";
};
tegra_i2s2: i2s@70301200 {
compatible = "nvidia,tegra124-i2s";
reg = <0x70301200 0x100>;
nvidia,ahub-cif-ids = <6 6>;
clocks = <&tegra_car TEGRA124_CLK_I2S2>;
resets = <&tegra_car 18>;
reset-names = "i2s";
status = "disabled";
};
tegra_i2s3: i2s@70301300 {
compatible = "nvidia,tegra124-i2s";
reg = <0x70301300 0x100>;
nvidia,ahub-cif-ids = <7 7>;
clocks = <&tegra_car TEGRA124_CLK_I2S3>;
resets = <&tegra_car 101>;
reset-names = "i2s";
status = "disabled";
};
tegra_i2s4: i2s@70301400 {
compatible = "nvidia,tegra124-i2s";
reg = <0x70301400 0x100>;
nvidia,ahub-cif-ids = <8 8>;
clocks = <&tegra_car TEGRA124_CLK_I2S4>;
resets = <&tegra_car 102>;
reset-names = "i2s";
status = "disabled";
};
};
ARM: tegra: Add initial device tree for Tegra124 Initial support for Tegra 124 SoC. This is expected to be included in the board DTS files. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-10-08 12:50:05 +08:00
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <2>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <3>;
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
};