2012-10-31 17:41:17 +08:00
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/*
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* Copyright (C) 2010 Google, Inc.
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* Copyright (c) 2010-2012 NVIDIA Corporation. All rights reserved.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _MACH_TEGRA_PM_H_
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#define _MACH_TEGRA_PM_H_
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2013-08-12 17:40:03 +08:00
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struct tegra_lp1_iram {
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void *start_addr;
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void *end_addr;
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};
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2014-07-11 19:19:06 +08:00
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2013-08-12 17:40:03 +08:00
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extern struct tegra_lp1_iram tegra_lp1_iram;
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extern void (*tegra_sleep_core_finish)(unsigned long v2p);
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2013-08-12 17:40:05 +08:00
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void tegra20_lp1_iram_hook(void);
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void tegra20_sleep_core_init(void);
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ARM: tegra: add LP1 suspend support for Tegra30
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put
SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The
sequence when LP1 suspending:
* tunning off L1 data cache and the MMU
* storing some EMC registers, DPD (deep power down) status, clk source of
mselect and SCLK burst policy
* putting SDRAM into self-refresh
* switching CPU to CLK_M (12MHz OSC)
* tunning off PLLM, PLLP, PLLA, PLLC and PLLX
* switching SCLK to CLK_S (32KHz OSC)
* shutting off the CPU rail
The sequence of LP1 resuming:
* re-enabling PLLM, PLLP, PLLA, PLLC and PLLX
* restoring the clk source of mselect and SCLK burst policy
* setting up CCLK burst policy to PLLX
* restoring DPD status and some EMC registers
* resuming SDRAM to normal mode
* jumping to the "tegra_resume" from PMC_SCRATCH41
Due to the SDRAM will be put into self-refresh mode, the low level
procedures of LP1 suspending and resuming should be copied to
TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before
restoring the CPU context when resuming, the SDRAM needs to be switched
back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy
be restored, CCLK burst policy be set in PLLX. Then jumping to
"tegra_resume" that was expected to be stored in PMC_SCRATCH41 to restore
CPU context and back to kernel.
Based on the work by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12 17:40:04 +08:00
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void tegra30_lp1_iram_hook(void);
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void tegra30_sleep_core_init(void);
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2013-06-04 18:47:35 +08:00
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void tegra_clear_cpu_in_lp2(void);
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bool tegra_set_cpu_in_lp2(void);
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2016-04-28 20:55:15 +08:00
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int tegra_cpu_do_idle(void);
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2013-04-02 09:20:50 +08:00
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void tegra_idle_lp2_last(void);
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2012-10-31 17:41:21 +08:00
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extern void (*tegra_tear_down_cpu)(void);
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2013-04-03 19:31:47 +08:00
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#ifdef CONFIG_PM_SLEEP
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void tegra_init_suspend(void);
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#else
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static inline void tegra_init_suspend(void) {}
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#endif
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2012-10-31 17:41:17 +08:00
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#endif /* _MACH_TEGRA_PM_H_ */
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