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OpenCloudOS-Kernel/drivers/soc/qcom/Kconfig

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soc: qcom: Add GSBI driver The GSBI (General Serial Bus Interface) driver controls the overarching configuration of the shared serial bus infrastructure on APQ8064, IPQ8064, and earlier QCOM processors. The GSBI supports UART, I2C, SPI, and UIM functionality in various combinations. Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
2014-04-25 00:31:21 +08:00
#
# QCOM Soc drivers
#
config QCOM_GSBI
tristate "QCOM General Serial Bus Interface"
depends on ARCH_QCOM
soc: qcom: gsbi: Add support for ADM CRCI muxing This patch adds automatic configuration for the ADM CRCI muxing required to support DMA operations for GSBI clients. The GSBI mode and instance determine the correct TCSR ADM CRCI MUX value that must be programmed so that the DMA works properly. Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
2015-02-10 06:01:06 +08:00
select MFD_SYSCON
soc: qcom: Add GSBI driver The GSBI (General Serial Bus Interface) driver controls the overarching configuration of the shared serial bus infrastructure on APQ8064, IPQ8064, and earlier QCOM processors. The GSBI supports UART, I2C, SPI, and UIM functionality in various combinations. Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
2014-04-25 00:31:21 +08:00
help
Say y here to enable GSBI support. The GSBI provides control
functions for connecting the underlying serial UART, SPI, and I2C
devices to the output pins.
ARM: qcom: Add Subsystem Power Manager (SPM) driver SPM is a hardware block that controls the peripheral logic surrounding the application cores (cpu/l$). When the core executes WFI instruction, the SPM takes over the putting the core in low power state as configured. The wake up for the SPM is an interrupt at the GIC, which then completes the rest of low power mode sequence and brings the core out of low power mode. The SPM has a set of control registers that configure the SPMs individually based on the type of the core and the runtime conditions. SPM is a finite state machine block to which a sequence is provided and it interprets the bytes and executes them in sequence. Each low power mode that the core can enter into is provided to the SPM as a sequence. Configure the SPM to set the core (cpu or L2) into its low power mode, the index of the first command in the sequence is set in the SPM_CTL register. When the core executes ARM wfi instruction, it triggers the SPM state machine to start executing from that index. The SPM state machine waits until the interrupt occurs and starts executing the rest of the sequence until it hits the end of the sequence. The end of the sequence jumps the core out of its low power mode. Add support for an idle driver to set up the SPM to place the core in Standby or Standalone power collapse mode when the core is idle. Based on work by: Mahesh Sivasubramanian <msivasub@codeaurora.org>, Ai Li <ali@codeaurora.org>, Praveen Chidambaram <pchidamb@codeaurora.org> Original tree available at - git://codeaurora.org/quic/la/kernel/msm-3.10.git Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Kevin Hilman <khilman@linaro.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kevin Hilman <khilman@linaro.org> Acked-by: Kumar Gala <galak@codeaurora.org> Acked-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
2015-04-10 03:20:41 +08:00
config QCOM_PM
bool "Qualcomm Power Management"
depends on ARCH_QCOM && !ARM64
drivers: qcom: Select QCOM_SCM unconditionally for QCOM_PM Enable QCOM_SCM for QCOM power management driver Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-07-11 04:18:00 +08:00
select QCOM_SCM
ARM: qcom: Add Subsystem Power Manager (SPM) driver SPM is a hardware block that controls the peripheral logic surrounding the application cores (cpu/l$). When the core executes WFI instruction, the SPM takes over the putting the core in low power state as configured. The wake up for the SPM is an interrupt at the GIC, which then completes the rest of low power mode sequence and brings the core out of low power mode. The SPM has a set of control registers that configure the SPMs individually based on the type of the core and the runtime conditions. SPM is a finite state machine block to which a sequence is provided and it interprets the bytes and executes them in sequence. Each low power mode that the core can enter into is provided to the SPM as a sequence. Configure the SPM to set the core (cpu or L2) into its low power mode, the index of the first command in the sequence is set in the SPM_CTL register. When the core executes ARM wfi instruction, it triggers the SPM state machine to start executing from that index. The SPM state machine waits until the interrupt occurs and starts executing the rest of the sequence until it hits the end of the sequence. The end of the sequence jumps the core out of its low power mode. Add support for an idle driver to set up the SPM to place the core in Standby or Standalone power collapse mode when the core is idle. Based on work by: Mahesh Sivasubramanian <msivasub@codeaurora.org>, Ai Li <ali@codeaurora.org>, Praveen Chidambaram <pchidamb@codeaurora.org> Original tree available at - git://codeaurora.org/quic/la/kernel/msm-3.10.git Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Kevin Hilman <khilman@linaro.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kevin Hilman <khilman@linaro.org> Acked-by: Kumar Gala <galak@codeaurora.org> Acked-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
2015-04-10 03:20:41 +08:00
help
QCOM Platform specific power driver to manage cores and L2 low power
modes. It interface with various system drivers to put the cores in
low power modes.
soc: qcom: Add Shared Memory Manager driver The Shared Memory Manager driver implements an interface for allocating and accessing items in the memory area shared among all of the processors in a Qualcomm platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Acked-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-06-27 05:50:10 +08:00
soc: qcom: Add Shared Memory Driver This adds the Qualcomm Shared Memory Driver (SMD) providing communication channels to remote processors, ontop of SMEM. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-07-28 11:20:30 +08:00
config QCOM_SMD
tristate "Qualcomm Shared Memory Driver (SMD)"
depends on QCOM_SMEM
help
Say y here to enable support for the Qualcomm Shared Memory Driver
providing communication channels to remote processors in Qualcomm
platforms.
soc: qcom: Add Shared Memory Manager driver The Shared Memory Manager driver implements an interface for allocating and accessing items in the memory area shared among all of the processors in a Qualcomm platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Acked-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Andy Gross <agross@codeaurora.org>
2015-06-27 05:50:10 +08:00
config QCOM_SMEM
tristate "Qualcomm Shared Memory Manager (SMEM)"
depends on ARCH_QCOM
help
Say y here to enable support for the Qualcomm Shared Memory Manager.
The driver provides an interface to items in a heap shared among all
processors in a Qualcomm platform.