2020-06-14 03:18:34 +08:00
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// SPDX-License-Identifier: GPL-2.0
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//
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// RPC-IF SPI/QSPI/Octa driver
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//
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// Copyright (C) 2018 ~ 2019 Renesas Solutions Corp.
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// Copyright (C) 2019 Macronix International Co., Ltd.
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// Copyright (C) 2019 - 2020 Cogent Embedded, Inc.
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//
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi-mem.h>
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#include <memory/renesas-rpc-if.h>
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#include <asm/unaligned.h>
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static void rpcif_spi_mem_prepare(struct spi_device *spi_dev,
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const struct spi_mem_op *spi_op,
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u64 *offs, size_t *len)
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{
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struct rpcif *rpc = spi_controller_get_devdata(spi_dev->controller);
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struct rpcif_op rpc_op = { };
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rpc_op.cmd.opcode = spi_op->cmd.opcode;
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rpc_op.cmd.buswidth = spi_op->cmd.buswidth;
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if (spi_op->addr.nbytes) {
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rpc_op.addr.buswidth = spi_op->addr.buswidth;
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rpc_op.addr.nbytes = spi_op->addr.nbytes;
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rpc_op.addr.val = spi_op->addr.val;
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}
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if (spi_op->dummy.nbytes) {
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rpc_op.dummy.buswidth = spi_op->dummy.buswidth;
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rpc_op.dummy.ncycles = spi_op->dummy.nbytes * 8 /
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spi_op->dummy.buswidth;
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}
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if (spi_op->data.nbytes || (offs && len)) {
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rpc_op.data.buswidth = spi_op->data.buswidth;
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rpc_op.data.nbytes = spi_op->data.nbytes;
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switch (spi_op->data.dir) {
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case SPI_MEM_DATA_IN:
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rpc_op.data.dir = RPCIF_DATA_IN;
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rpc_op.data.buf.in = spi_op->data.buf.in;
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break;
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case SPI_MEM_DATA_OUT:
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rpc_op.data.dir = RPCIF_DATA_OUT;
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rpc_op.data.buf.out = spi_op->data.buf.out;
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break;
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case SPI_MEM_NO_DATA:
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rpc_op.data.dir = RPCIF_NO_DATA;
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break;
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}
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} else {
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rpc_op.data.dir = RPCIF_NO_DATA;
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}
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2022-11-23 22:41:21 +08:00
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rpcif_prepare(rpc->dev, &rpc_op, offs, len);
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2020-06-14 03:18:34 +08:00
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}
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static bool rpcif_spi_mem_supports_op(struct spi_mem *mem,
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const struct spi_mem_op *op)
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{
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if (!spi_mem_default_supports_op(mem, op))
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return false;
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if (op->data.buswidth > 4 || op->addr.buswidth > 4 ||
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op->dummy.buswidth > 4 || op->cmd.buswidth > 4 ||
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op->addr.nbytes > 4)
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return false;
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return true;
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}
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static ssize_t rpcif_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc,
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u64 offs, size_t len, void *buf)
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{
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struct rpcif *rpc =
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spi_controller_get_devdata(desc->mem->spi->controller);
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if (offs + desc->info.offset + len > U32_MAX)
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return -EINVAL;
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rpcif_spi_mem_prepare(desc->mem->spi, &desc->info.op_tmpl, &offs, &len);
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2022-11-23 22:41:21 +08:00
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return rpcif_dirmap_read(rpc->dev, offs, len, buf);
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2020-06-14 03:18:34 +08:00
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}
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static int rpcif_spi_mem_dirmap_create(struct spi_mem_dirmap_desc *desc)
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{
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struct rpcif *rpc =
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spi_controller_get_devdata(desc->mem->spi->controller);
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if (desc->info.offset + desc->info.length > U32_MAX)
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return -ENOTSUPP;
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if (!rpcif_spi_mem_supports_op(desc->mem, &desc->info.op_tmpl))
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return -ENOTSUPP;
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if (!rpc->dirmap && desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN)
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return -ENOTSUPP;
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if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT)
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return -ENOTSUPP;
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return 0;
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}
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static int rpcif_spi_mem_exec_op(struct spi_mem *mem,
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const struct spi_mem_op *op)
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{
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struct rpcif *rpc =
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spi_controller_get_devdata(mem->spi->controller);
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rpcif_spi_mem_prepare(mem->spi, op, NULL, NULL);
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2022-11-23 22:41:21 +08:00
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return rpcif_manual_xfer(rpc->dev);
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2020-06-14 03:18:34 +08:00
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}
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static const struct spi_controller_mem_ops rpcif_spi_mem_ops = {
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.supports_op = rpcif_spi_mem_supports_op,
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.exec_op = rpcif_spi_mem_exec_op,
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.dirmap_create = rpcif_spi_mem_dirmap_create,
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.dirmap_read = rpcif_spi_mem_dirmap_read,
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};
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static int rpcif_spi_probe(struct platform_device *pdev)
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{
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struct device *parent = pdev->dev.parent;
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struct spi_controller *ctlr;
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struct rpcif *rpc;
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int error;
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2020-12-07 16:17:06 +08:00
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ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*rpc));
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2020-06-14 03:18:34 +08:00
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if (!ctlr)
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return -ENOMEM;
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rpc = spi_controller_get_devdata(ctlr);
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2021-10-26 04:56:27 +08:00
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error = rpcif_sw_init(rpc, parent);
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if (error)
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return error;
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2020-06-14 03:18:34 +08:00
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platform_set_drvdata(pdev, ctlr);
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ctlr->dev.of_node = parent->of_node;
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2022-11-23 22:41:22 +08:00
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pm_runtime_enable(rpc->dev);
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2020-06-14 03:18:34 +08:00
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ctlr->num_chipselect = 1;
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ctlr->mem_ops = &rpcif_spi_mem_ops;
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ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
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ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_TX_QUAD | SPI_RX_QUAD;
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ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX;
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2022-11-23 22:41:21 +08:00
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error = rpcif_hw_init(rpc->dev, false);
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2021-10-26 04:56:31 +08:00
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if (error)
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2022-03-29 22:00:39 +08:00
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goto out_disable_rpm;
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2020-06-14 03:18:34 +08:00
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error = spi_register_controller(ctlr);
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if (error) {
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dev_err(&pdev->dev, "spi_register_controller failed\n");
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2022-03-29 22:00:39 +08:00
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goto out_disable_rpm;
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2020-06-14 03:18:34 +08:00
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}
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2022-03-29 22:00:39 +08:00
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return 0;
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out_disable_rpm:
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2022-11-23 22:41:22 +08:00
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pm_runtime_disable(rpc->dev);
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2020-06-14 03:18:34 +08:00
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return error;
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}
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2023-03-04 01:20:14 +08:00
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static void rpcif_spi_remove(struct platform_device *pdev)
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2020-06-14 03:18:34 +08:00
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{
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struct spi_controller *ctlr = platform_get_drvdata(pdev);
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struct rpcif *rpc = spi_controller_get_devdata(ctlr);
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spi_unregister_controller(ctlr);
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2022-11-23 22:41:22 +08:00
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pm_runtime_disable(rpc->dev);
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2020-06-14 03:18:34 +08:00
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}
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2020-12-30 22:57:08 +08:00
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static int __maybe_unused rpcif_spi_suspend(struct device *dev)
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2020-06-14 03:18:34 +08:00
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{
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struct spi_controller *ctlr = dev_get_drvdata(dev);
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return spi_controller_suspend(ctlr);
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}
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2020-12-30 22:57:08 +08:00
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static int __maybe_unused rpcif_spi_resume(struct device *dev)
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2020-06-14 03:18:34 +08:00
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{
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struct spi_controller *ctlr = dev_get_drvdata(dev);
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return spi_controller_resume(ctlr);
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}
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static SIMPLE_DEV_PM_OPS(rpcif_spi_pm_ops, rpcif_spi_suspend, rpcif_spi_resume);
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static struct platform_driver rpcif_spi_driver = {
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.probe = rpcif_spi_probe,
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2023-03-04 01:20:14 +08:00
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.remove_new = rpcif_spi_remove,
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2020-06-14 03:18:34 +08:00
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.driver = {
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.name = "rpc-if-spi",
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2021-01-07 22:53:29 +08:00
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#ifdef CONFIG_PM_SLEEP
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2020-12-30 22:57:08 +08:00
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.pm = &rpcif_spi_pm_ops,
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2021-01-07 22:53:29 +08:00
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#endif
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2020-06-14 03:18:34 +08:00
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},
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};
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module_platform_driver(rpcif_spi_driver);
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MODULE_DESCRIPTION("Renesas RPC-IF SPI driver");
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MODULE_LICENSE("GPL v2");
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