2016-09-30 00:21:53 +08:00
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/*
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* Marvell 88E6xxx Switch Global (1) Registers support
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*
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* Copyright (c) 2016 Vivien Didelot <vivien.didelot@savoirfairelinux.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include "mv88e6xxx.h"
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#include "global1.h"
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int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
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{
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int addr = chip->info->global1_addr;
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return mv88e6xxx_read(chip, addr, reg, val);
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}
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int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
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{
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int addr = chip->info->global1_addr;
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return mv88e6xxx_write(chip, addr, reg, val);
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}
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int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
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{
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return mv88e6xxx_wait(chip, chip->info->global1_addr, reg, mask);
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}
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2016-11-22 06:26:58 +08:00
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2016-11-22 06:27:01 +08:00
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/* Offset 0x1c: Global Control 2 */
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int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
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{
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u16 val;
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int err;
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err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL_2, &val);
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if (err)
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return err;
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val |= GLOBAL_CONTROL_2_HIST_RX_TX;
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err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2, val);
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return err;
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}
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/* Offset 0x1d: Statistics Operation 2 */
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2016-11-22 06:27:05 +08:00
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int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip)
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2016-11-22 06:26:58 +08:00
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{
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return mv88e6xxx_g1_wait(chip, GLOBAL_STATS_OP, GLOBAL_STATS_OP_BUSY);
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}
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int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
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{
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int err;
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/* Snapshot the hardware statistics counters for this port. */
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err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
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GLOBAL_STATS_OP_CAPTURE_PORT |
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GLOBAL_STATS_OP_HIST_RX_TX | port);
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if (err)
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return err;
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/* Wait for the snapshotting to complete. */
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return mv88e6xxx_g1_stats_wait(chip);
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}
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int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
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{
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port = (port + 1) << 5;
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return mv88e6xxx_g1_stats_snapshot(chip, port);
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}
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2016-11-22 06:27:00 +08:00
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int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
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{
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int err;
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port = (port + 1) << 5;
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/* Snapshot the hardware statistics counters for this port. */
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err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
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GLOBAL_STATS_OP_CAPTURE_PORT | port);
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if (err)
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return err;
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/* Wait for the snapshotting to complete. */
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return mv88e6xxx_g1_stats_wait(chip);
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}
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2016-11-22 06:27:05 +08:00
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void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val)
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{
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u32 value;
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u16 reg;
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int err;
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*val = 0;
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err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
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GLOBAL_STATS_OP_READ_CAPTURED | stat);
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if (err)
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return;
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err = mv88e6xxx_g1_stats_wait(chip);
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if (err)
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return;
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err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_32, ®);
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if (err)
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return;
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value = reg << 16;
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err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_01, ®);
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if (err)
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return;
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*val = value | reg;
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}
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