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OpenCloudOS-Kernel/drivers/clk/clk-axi-clkgen.c

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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 177 Based on 1 normalized pattern(s): licensed under the gpl 2 extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 135 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528170026.071193225@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-29 00:57:06 +08:00
// SPDX-License-Identifier: GPL-2.0-only
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
/*
* AXI clkgen driver
*
* Copyright 2012-2013 Analog Devices Inc.
* Author: Lars-Peter Clausen <lars@metafoo.de>
*/
#include <linux/platform_device.h>
#include <linux/clk-provider.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/err.h>
clk: axi-clkgen: Add support for v2 This patch adds support for the new v2 version of the axi-clkgen core. Unfortunately the method of accessing the registers is quite different on v2, while the content still stays largely the same. So the patch adds a small abstraction layer which implements the specific read and write functions for v1 and v2 in callback functions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-02-17 17:31:53 +08:00
#define AXI_CLKGEN_V2_REG_RESET 0x40
clk: axi-clkgen: Add multi-parent support The clock generator has two clock inputs that can be used as the reference clock. Add support for switching between them at runtime. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-12-01 00:54:56 +08:00
#define AXI_CLKGEN_V2_REG_CLKSEL 0x44
clk: axi-clkgen: Add support for v2 This patch adds support for the new v2 version of the axi-clkgen core. Unfortunately the method of accessing the registers is quite different on v2, while the content still stays largely the same. So the patch adds a small abstraction layer which implements the specific read and write functions for v1 and v2 in callback functions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-02-17 17:31:53 +08:00
#define AXI_CLKGEN_V2_REG_DRP_CNTRL 0x70
#define AXI_CLKGEN_V2_REG_DRP_STATUS 0x74
#define AXI_CLKGEN_V2_RESET_MMCM_ENABLE BIT(1)
#define AXI_CLKGEN_V2_RESET_ENABLE BIT(0)
#define AXI_CLKGEN_V2_DRP_CNTRL_SEL BIT(29)
#define AXI_CLKGEN_V2_DRP_CNTRL_READ BIT(28)
#define AXI_CLKGEN_V2_DRP_STATUS_BUSY BIT(16)
clk: axi-clkgen: Add support for fractional dividers The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:47 +08:00
#define MMCM_REG_CLKOUT5_2 0x07
clk: axi-clkgen: Add support for v2 This patch adds support for the new v2 version of the axi-clkgen core. Unfortunately the method of accessing the registers is quite different on v2, while the content still stays largely the same. So the patch adds a small abstraction layer which implements the specific read and write functions for v1 and v2 in callback functions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-02-17 17:31:53 +08:00
#define MMCM_REG_CLKOUT0_1 0x08
#define MMCM_REG_CLKOUT0_2 0x09
clk: axi-clkgen: Add support for fractional dividers The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:47 +08:00
#define MMCM_REG_CLKOUT6_2 0x13
clk: axi-clkgen: Add support for v2 This patch adds support for the new v2 version of the axi-clkgen core. Unfortunately the method of accessing the registers is quite different on v2, while the content still stays largely the same. So the patch adds a small abstraction layer which implements the specific read and write functions for v1 and v2 in callback functions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-02-17 17:31:53 +08:00
#define MMCM_REG_CLK_FB1 0x14
#define MMCM_REG_CLK_FB2 0x15
#define MMCM_REG_CLK_DIV 0x16
#define MMCM_REG_LOCK1 0x18
#define MMCM_REG_LOCK2 0x19
#define MMCM_REG_LOCK3 0x1a
clk: axi-clkgen: Set power bits for fractional mode Using the fractional dividers requires some additional power bits to be set. The fractional power bits are not documented and the current heuristic for setting them seems be insufficient for some cases. Just always set all the fractional power bits when in fractional mode. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-2-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:48 +08:00
#define MMCM_REG_POWER 0x28
clk: axi-clkgen: Add support for v2 This patch adds support for the new v2 version of the axi-clkgen core. Unfortunately the method of accessing the registers is quite different on v2, while the content still stays largely the same. So the patch adds a small abstraction layer which implements the specific read and write functions for v1 and v2 in callback functions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-02-17 17:31:53 +08:00
#define MMCM_REG_FILTER1 0x4e
#define MMCM_REG_FILTER2 0x4f
clk: axi-clkgen: Correctly handle nocount bit in recalc_rate() If the nocount bit is set the divider is bypassed and the settings for the divider count should be ignored and a divider value of 1 should be assumed. Handle this correctly in the driver recalc_rate() callback. While the driver sets up the part so that the read back dividers values yield the correct result the power-on reset settings of the part might not reflect this and hence calling e.g. clk_get_rate() without prior calls to clk_set_rate() will yield the wrong result. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-09-05 17:32:40 +08:00
#define MMCM_CLKOUT_NOCOUNT BIT(6)
clk: axi-clkgen: Add support for fractional dividers The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:47 +08:00
#define MMCM_CLK_DIV_DIVIDE BIT(11)
clk: axi-clkgen: Correctly handle nocount bit in recalc_rate() If the nocount bit is set the divider is bypassed and the settings for the divider count should be ignored and a divider value of 1 should be assumed. Handle this correctly in the driver recalc_rate() callback. While the driver sets up the part so that the read back dividers values yield the correct result the power-on reset settings of the part might not reflect this and hence calling e.g. clk_get_rate() without prior calls to clk_set_rate() will yield the wrong result. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-09-05 17:32:40 +08:00
#define MMCM_CLK_DIV_NOCOUNT BIT(12)
clk: axi-clkgen: wrap limits in a struct and keep copy on the state object Up until the these limits were global/hard-coded, since they are typically limits of the fabric. However, since this is an FPGA generated clock, this may run on setups where one clock is on a fabric, and another one synthesized on another fabric connected via PCIe (or some other inter-connect, and then these limits need to be adjusted for each instance of the AXI CLKGEN. This change wraps the current constants in 'axi_clkgen_limits' struct and the 'axi_clkgen' instance keeps a copy of these limits, which is initialized at probe from the default limits. The limits are stored on the device-tree OF table, so that we can adjust them via the compatible string. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201203074037.26940-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-03 15:40:36 +08:00
struct axi_clkgen_limits {
unsigned int fpfd_min;
unsigned int fpfd_max;
unsigned int fvco_min;
unsigned int fvco_max;
};
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
struct axi_clkgen {
void __iomem *base;
struct clk_hw clk_hw;
clk: axi-clkgen: wrap limits in a struct and keep copy on the state object Up until the these limits were global/hard-coded, since they are typically limits of the fabric. However, since this is an FPGA generated clock, this may run on setups where one clock is on a fabric, and another one synthesized on another fabric connected via PCIe (or some other inter-connect, and then these limits need to be adjusted for each instance of the AXI CLKGEN. This change wraps the current constants in 'axi_clkgen_limits' struct and the 'axi_clkgen' instance keeps a copy of these limits, which is initialized at probe from the default limits. The limits are stored on the device-tree OF table, so that we can adjust them via the compatible string. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201203074037.26940-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-03 15:40:36 +08:00
struct axi_clkgen_limits limits;
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
};
static uint32_t axi_clkgen_lookup_filter(unsigned int m)
{
switch (m) {
case 0:
return 0x01001990;
case 1:
return 0x01001190;
case 2:
return 0x01009890;
case 3:
return 0x01001890;
case 4:
return 0x01008890;
case 5 ... 8:
return 0x01009090;
case 9 ... 11:
return 0x01000890;
case 12:
return 0x08009090;
case 13 ... 22:
return 0x01001090;
case 23 ... 36:
return 0x01008090;
case 37 ... 46:
return 0x08001090;
default:
return 0x08008090;
}
}
static const uint32_t axi_clkgen_lock_table[] = {
0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8,
0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8,
0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339,
0x1f1f02ee, 0x1f1f02bc, 0x1f1f028a, 0x1f1f0271,
0x1f1f023f, 0x1f1f0226, 0x1f1f020d, 0x1f1f01f4,
0x1f1f01db, 0x1f1f01c2, 0x1f1f01a9, 0x1f1f0190,
0x1f1f0190, 0x1f1f0177, 0x1f1f015e, 0x1f1f015e,
0x1f1f0145, 0x1f1f0145, 0x1f1f012c, 0x1f1f012c,
0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113,
};
static uint32_t axi_clkgen_lookup_lock(unsigned int m)
{
if (m < ARRAY_SIZE(axi_clkgen_lock_table))
return axi_clkgen_lock_table[m];
return 0x1f1f00fa;
}
clk: clk-axiclkgen: add ZynqMP PFD and VCO limits For ZynqMP (Ultrascale) the PFD and VCO limits are different. In order to support these, this change adds a compatible string (i.e. 'adi,zynqmp-axi-clkgen-2.00.a') which will take into account for these limits and apply them. Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com> Signed-off-by: Mathias Tausen <mta@gomspace.com> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20210201151245.21845-3-alexandru.ardelean@analog.com Acked-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-01 23:12:43 +08:00
static const struct axi_clkgen_limits axi_clkgen_zynqmp_default_limits = {
.fpfd_min = 10000,
.fpfd_max = 450000,
.fvco_min = 800000,
.fvco_max = 1600000,
};
clk: axi-clkgen: wrap limits in a struct and keep copy on the state object Up until the these limits were global/hard-coded, since they are typically limits of the fabric. However, since this is an FPGA generated clock, this may run on setups where one clock is on a fabric, and another one synthesized on another fabric connected via PCIe (or some other inter-connect, and then these limits need to be adjusted for each instance of the AXI CLKGEN. This change wraps the current constants in 'axi_clkgen_limits' struct and the 'axi_clkgen' instance keeps a copy of these limits, which is initialized at probe from the default limits. The limits are stored on the device-tree OF table, so that we can adjust them via the compatible string. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201203074037.26940-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-03 15:40:36 +08:00
static const struct axi_clkgen_limits axi_clkgen_zynq_default_limits = {
.fpfd_min = 10000,
.fpfd_max = 300000,
.fvco_min = 600000,
.fvco_max = 1200000,
};
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
clk: axi-clkgen: wrap limits in a struct and keep copy on the state object Up until the these limits were global/hard-coded, since they are typically limits of the fabric. However, since this is an FPGA generated clock, this may run on setups where one clock is on a fabric, and another one synthesized on another fabric connected via PCIe (or some other inter-connect, and then these limits need to be adjusted for each instance of the AXI CLKGEN. This change wraps the current constants in 'axi_clkgen_limits' struct and the 'axi_clkgen' instance keeps a copy of these limits, which is initialized at probe from the default limits. The limits are stored on the device-tree OF table, so that we can adjust them via the compatible string. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201203074037.26940-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-03 15:40:36 +08:00
static void axi_clkgen_calc_params(const struct axi_clkgen_limits *limits,
unsigned long fin, unsigned long fout,
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout)
{
unsigned long d, d_min, d_max, _d_min, _d_max;
unsigned long m, m_min, m_max;
unsigned long f, dout, best_f, fvco;
clk: axi-clkgen: Add support for fractional dividers The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:47 +08:00
unsigned long fract_shift = 0;
unsigned long fvco_min_fract, fvco_max_fract;
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
fin /= 1000;
fout /= 1000;
best_f = ULONG_MAX;
*best_d = 0;
*best_m = 0;
*best_dout = 0;
clk: axi-clkgen: wrap limits in a struct and keep copy on the state object Up until the these limits were global/hard-coded, since they are typically limits of the fabric. However, since this is an FPGA generated clock, this may run on setups where one clock is on a fabric, and another one synthesized on another fabric connected via PCIe (or some other inter-connect, and then these limits need to be adjusted for each instance of the AXI CLKGEN. This change wraps the current constants in 'axi_clkgen_limits' struct and the 'axi_clkgen' instance keeps a copy of these limits, which is initialized at probe from the default limits. The limits are stored on the device-tree OF table, so that we can adjust them via the compatible string. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201203074037.26940-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-03 15:40:36 +08:00
d_min = max_t(unsigned long, DIV_ROUND_UP(fin, limits->fpfd_max), 1);
d_max = min_t(unsigned long, fin / limits->fpfd_min, 80);
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
clk: axi-clkgen: Add support for fractional dividers The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:47 +08:00
again:
clk: axi-clkgen: wrap limits in a struct and keep copy on the state object Up until the these limits were global/hard-coded, since they are typically limits of the fabric. However, since this is an FPGA generated clock, this may run on setups where one clock is on a fabric, and another one synthesized on another fabric connected via PCIe (or some other inter-connect, and then these limits need to be adjusted for each instance of the AXI CLKGEN. This change wraps the current constants in 'axi_clkgen_limits' struct and the 'axi_clkgen' instance keeps a copy of these limits, which is initialized at probe from the default limits. The limits are stored on the device-tree OF table, so that we can adjust them via the compatible string. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201203074037.26940-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-03 15:40:36 +08:00
fvco_min_fract = limits->fvco_min << fract_shift;
fvco_max_fract = limits->fvco_max << fract_shift;
clk: axi-clkgen: Add support for fractional dividers The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:47 +08:00
m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min_fract, fin) * d_min, 1);
m_max = min_t(unsigned long, fvco_max_fract * d_max / fin, 64 << fract_shift);
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
for (m = m_min; m <= m_max; m++) {
clk: axi-clkgen: Add support for fractional dividers The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:47 +08:00
_d_min = max(d_min, DIV_ROUND_UP(fin * m, fvco_max_fract));
_d_max = min(d_max, fin * m / fvco_min_fract);
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
for (d = _d_min; d <= _d_max; d++) {
fvco = fin * m / d;
dout = DIV_ROUND_CLOSEST(fvco, fout);
clk: axi-clkgen: Add support for fractional dividers The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:47 +08:00
dout = clamp_t(unsigned long, dout, 1, 128 << fract_shift);
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
f = fvco / dout;
if (abs(f - fout) < abs(best_f - fout)) {
best_f = f;
*best_d = d;
clk: axi-clkgen: Add support for fractional dividers The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:47 +08:00
*best_m = m << (3 - fract_shift);
*best_dout = dout << (3 - fract_shift);
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
if (best_f == fout)
return;
}
}
}
clk: axi-clkgen: Add support for fractional dividers The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:47 +08:00
/* Lets see if we find a better setting in fractional mode */
if (fract_shift == 0) {
fract_shift = 3;
goto again;
}
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
}
clk: axi-clkgen: Add support for fractional dividers The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:47 +08:00
struct axi_clkgen_div_params {
unsigned int low;
unsigned int high;
unsigned int edge;
unsigned int nocount;
unsigned int frac_en;
unsigned int frac;
unsigned int frac_wf_f;
unsigned int frac_wf_r;
unsigned int frac_phase;
};
static void axi_clkgen_calc_clk_params(unsigned int divider,
unsigned int frac_divider, struct axi_clkgen_div_params *params)
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
{
clk: axi-clkgen: Add support for fractional dividers The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:47 +08:00
memset(params, 0x0, sizeof(*params));
if (divider == 1) {
params->nocount = 1;
return;
}
if (frac_divider == 0) {
params->high = divider / 2;
params->edge = divider % 2;
params->low = divider - params->high;
} else {
params->frac_en = 1;
params->frac = frac_divider;
params->high = divider / 2;
params->edge = divider % 2;
params->low = params->high;
if (params->edge == 0) {
params->high--;
params->frac_wf_r = 1;
}
if (params->edge == 0 || frac_divider == 1)
params->low--;
if (((params->edge == 0) ^ (frac_divider == 1)) ||
(divider == 2 && frac_divider == 1))
params->frac_wf_f = 1;
params->frac_phase = params->edge * 4 + frac_divider / 2;
}
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
}
static void axi_clkgen_write(struct axi_clkgen *axi_clkgen,
unsigned int reg, unsigned int val)
{
writel(val, axi_clkgen->base + reg);
}
static void axi_clkgen_read(struct axi_clkgen *axi_clkgen,
unsigned int reg, unsigned int *val)
{
*val = readl(axi_clkgen->base + reg);
}
clk: axi-clkgen: Add support for v2 This patch adds support for the new v2 version of the axi-clkgen core. Unfortunately the method of accessing the registers is quite different on v2, while the content still stays largely the same. So the patch adds a small abstraction layer which implements the specific read and write functions for v1 and v2 in callback functions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-02-17 17:31:53 +08:00
static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen)
{
unsigned int timeout = 10000;
unsigned int val;
do {
axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_STATUS, &val);
} while ((val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) && --timeout);
if (val & AXI_CLKGEN_V2_DRP_STATUS_BUSY)
return -EIO;
return val & 0xffff;
}
clk: axi-clkgen: Remove version 1 support Version 1 of the axi-clkgen core has not been used in new designs for over two years now. This is a soft peripheral used in FPGAs and anybody who has updated their kernel to the latest version will also have updated the bitstream containing the clock generator. So it should be safe to drop support for this now. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-12-01 00:54:55 +08:00
static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen,
clk: axi-clkgen: Add support for v2 This patch adds support for the new v2 version of the axi-clkgen core. Unfortunately the method of accessing the registers is quite different on v2, while the content still stays largely the same. So the patch adds a small abstraction layer which implements the specific read and write functions for v1 and v2 in callback functions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-02-17 17:31:53 +08:00
unsigned int reg, unsigned int *val)
{
unsigned int reg_val;
int ret;
ret = axi_clkgen_wait_non_busy(axi_clkgen);
if (ret < 0)
return ret;
reg_val = AXI_CLKGEN_V2_DRP_CNTRL_SEL | AXI_CLKGEN_V2_DRP_CNTRL_READ;
reg_val |= (reg << 16);
axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
ret = axi_clkgen_wait_non_busy(axi_clkgen);
if (ret < 0)
return ret;
*val = ret;
return 0;
}
clk: axi-clkgen: Remove version 1 support Version 1 of the axi-clkgen core has not been used in new designs for over two years now. This is a soft peripheral used in FPGAs and anybody who has updated their kernel to the latest version will also have updated the bitstream containing the clock generator. So it should be safe to drop support for this now. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-12-01 00:54:55 +08:00
static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen,
clk: axi-clkgen: Add support for v2 This patch adds support for the new v2 version of the axi-clkgen core. Unfortunately the method of accessing the registers is quite different on v2, while the content still stays largely the same. So the patch adds a small abstraction layer which implements the specific read and write functions for v1 and v2 in callback functions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-02-17 17:31:53 +08:00
unsigned int reg, unsigned int val, unsigned int mask)
{
unsigned int reg_val = 0;
int ret;
ret = axi_clkgen_wait_non_busy(axi_clkgen);
if (ret < 0)
return ret;
if (mask != 0xffff) {
clk: axi-clkgen: Remove version 1 support Version 1 of the axi-clkgen core has not been used in new designs for over two years now. This is a soft peripheral used in FPGAs and anybody who has updated their kernel to the latest version will also have updated the bitstream containing the clock generator. So it should be safe to drop support for this now. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-12-01 00:54:55 +08:00
axi_clkgen_mmcm_read(axi_clkgen, reg, &reg_val);
clk: axi-clkgen: Add support for v2 This patch adds support for the new v2 version of the axi-clkgen core. Unfortunately the method of accessing the registers is quite different on v2, while the content still stays largely the same. So the patch adds a small abstraction layer which implements the specific read and write functions for v1 and v2 in callback functions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-02-17 17:31:53 +08:00
reg_val &= ~mask;
}
reg_val |= AXI_CLKGEN_V2_DRP_CNTRL_SEL | (reg << 16) | (val & mask);
axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
return 0;
}
clk: axi-clkgen: Remove version 1 support Version 1 of the axi-clkgen core has not been used in new designs for over two years now. This is a soft peripheral used in FPGAs and anybody who has updated their kernel to the latest version will also have updated the bitstream containing the clock generator. So it should be safe to drop support for this now. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-12-01 00:54:55 +08:00
static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen,
clk: axi-clkgen: Add support for v2 This patch adds support for the new v2 version of the axi-clkgen core. Unfortunately the method of accessing the registers is quite different on v2, while the content still stays largely the same. So the patch adds a small abstraction layer which implements the specific read and write functions for v1 and v2 in callback functions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-02-17 17:31:53 +08:00
bool enable)
{
unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE;
if (enable)
val |= AXI_CLKGEN_V2_RESET_MMCM_ENABLE;
axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_RESET, val);
}
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw)
{
return container_of(clk_hw, struct axi_clkgen, clk_hw);
}
clk: axi-clkgen: Add support for fractional dividers The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:47 +08:00
static void axi_clkgen_set_div(struct axi_clkgen *axi_clkgen,
unsigned int reg1, unsigned int reg2, unsigned int reg3,
struct axi_clkgen_div_params *params)
{
axi_clkgen_mmcm_write(axi_clkgen, reg1,
(params->high << 6) | params->low, 0xefff);
axi_clkgen_mmcm_write(axi_clkgen, reg2,
(params->frac << 12) | (params->frac_en << 11) |
(params->frac_wf_r << 10) | (params->edge << 7) |
(params->nocount << 6), 0x7fff);
if (reg3 != 0) {
axi_clkgen_mmcm_write(axi_clkgen, reg3,
(params->frac_phase << 11) | (params->frac_wf_f << 10), 0x3c00);
}
}
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
unsigned long rate, unsigned long parent_rate)
{
struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
clk: axi-clkgen: wrap limits in a struct and keep copy on the state object Up until the these limits were global/hard-coded, since they are typically limits of the fabric. However, since this is an FPGA generated clock, this may run on setups where one clock is on a fabric, and another one synthesized on another fabric connected via PCIe (or some other inter-connect, and then these limits need to be adjusted for each instance of the AXI CLKGEN. This change wraps the current constants in 'axi_clkgen_limits' struct and the 'axi_clkgen' instance keeps a copy of these limits, which is initialized at probe from the default limits. The limits are stored on the device-tree OF table, so that we can adjust them via the compatible string. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201203074037.26940-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-03 15:40:36 +08:00
const struct axi_clkgen_limits *limits = &axi_clkgen->limits;
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
unsigned int d, m, dout;
clk: axi-clkgen: Add support for fractional dividers The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:47 +08:00
struct axi_clkgen_div_params params;
clk: axi-clkgen: Set power bits for fractional mode Using the fractional dividers requires some additional power bits to be set. The fractional power bits are not documented and the current heuristic for setting them seems be insufficient for some cases. Just always set all the fractional power bits when in fractional mode. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-2-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:48 +08:00
uint32_t power = 0;
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
uint32_t filter;
uint32_t lock;
if (parent_rate == 0 || rate == 0)
return -EINVAL;
clk: axi-clkgen: wrap limits in a struct and keep copy on the state object Up until the these limits were global/hard-coded, since they are typically limits of the fabric. However, since this is an FPGA generated clock, this may run on setups where one clock is on a fabric, and another one synthesized on another fabric connected via PCIe (or some other inter-connect, and then these limits need to be adjusted for each instance of the AXI CLKGEN. This change wraps the current constants in 'axi_clkgen_limits' struct and the 'axi_clkgen' instance keeps a copy of these limits, which is initialized at probe from the default limits. The limits are stored on the device-tree OF table, so that we can adjust them via the compatible string. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201203074037.26940-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-03 15:40:36 +08:00
axi_clkgen_calc_params(limits, parent_rate, rate, &d, &m, &dout);
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
if (d == 0 || dout == 0 || m == 0)
return -EINVAL;
clk: axi-clkgen: Set power bits for fractional mode Using the fractional dividers requires some additional power bits to be set. The fractional power bits are not documented and the current heuristic for setting them seems be insufficient for some cases. Just always set all the fractional power bits when in fractional mode. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-2-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:48 +08:00
if ((dout & 0x7) != 0 || (m & 0x7) != 0)
power |= 0x9800;
axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_POWER, power, 0x9800);
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
filter = axi_clkgen_lookup_filter(m - 1);
lock = axi_clkgen_lookup_lock(m - 1);
clk: axi-clkgen: Add support for fractional dividers The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:47 +08:00
axi_clkgen_calc_clk_params(dout >> 3, dout & 0x7, &params);
axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLKOUT0_1, MMCM_REG_CLKOUT0_2,
MMCM_REG_CLKOUT5_2, &params);
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
clk: axi-clkgen: Add support for fractional dividers The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:47 +08:00
axi_clkgen_calc_clk_params(d, 0, &params);
clk: axi-clkgen: Add support for v2 This patch adds support for the new v2 version of the axi-clkgen core. Unfortunately the method of accessing the registers is quite different on v2, while the content still stays largely the same. So the patch adds a small abstraction layer which implements the specific read and write functions for v1 and v2 in callback functions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-02-17 17:31:53 +08:00
axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_DIV,
clk: axi-clkgen: Add support for fractional dividers The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:47 +08:00
(params.edge << 13) | (params.nocount << 12) |
(params.high << 6) | params.low, 0x3fff);
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
clk: axi-clkgen: Add support for fractional dividers The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:47 +08:00
axi_clkgen_calc_clk_params(m >> 3, m & 0x7, &params);
axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLK_FB1, MMCM_REG_CLK_FB2,
MMCM_REG_CLKOUT6_2, &params);
clk: axi-clkgen: Add support for v2 This patch adds support for the new v2 version of the axi-clkgen core. Unfortunately the method of accessing the registers is quite different on v2, while the content still stays largely the same. So the patch adds a small abstraction layer which implements the specific read and write functions for v1 and v2 in callback functions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-02-17 17:31:53 +08:00
axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK1, lock & 0x3ff, 0x3ff);
axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK2,
(((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff);
axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK3,
(((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff);
axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER1, filter >> 16, 0x9900);
axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER2, filter, 0x9900);
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
return 0;
}
static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
clk: axi-clkgen: wrap limits in a struct and keep copy on the state object Up until the these limits were global/hard-coded, since they are typically limits of the fabric. However, since this is an FPGA generated clock, this may run on setups where one clock is on a fabric, and another one synthesized on another fabric connected via PCIe (or some other inter-connect, and then these limits need to be adjusted for each instance of the AXI CLKGEN. This change wraps the current constants in 'axi_clkgen_limits' struct and the 'axi_clkgen' instance keeps a copy of these limits, which is initialized at probe from the default limits. The limits are stored on the device-tree OF table, so that we can adjust them via the compatible string. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201203074037.26940-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-03 15:40:36 +08:00
struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(hw);
const struct axi_clkgen_limits *limits = &axi_clkgen->limits;
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
unsigned int d, m, dout;
clk: axi-clkgen: Round closest in round_rate() and recalc_rate() To minimize the rounding error round to the closest integer when calculating the result in the recalc_rate() and set_rate() callbacks. Also in order to improve precision multiply first and then divide. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-09-05 17:32:41 +08:00
unsigned long long tmp;
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
clk: axi-clkgen: wrap limits in a struct and keep copy on the state object Up until the these limits were global/hard-coded, since they are typically limits of the fabric. However, since this is an FPGA generated clock, this may run on setups where one clock is on a fabric, and another one synthesized on another fabric connected via PCIe (or some other inter-connect, and then these limits need to be adjusted for each instance of the AXI CLKGEN. This change wraps the current constants in 'axi_clkgen_limits' struct and the 'axi_clkgen' instance keeps a copy of these limits, which is initialized at probe from the default limits. The limits are stored on the device-tree OF table, so that we can adjust them via the compatible string. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201203074037.26940-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-03 15:40:36 +08:00
axi_clkgen_calc_params(limits, *parent_rate, rate, &d, &m, &dout);
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
if (d == 0 || dout == 0 || m == 0)
return -EINVAL;
clk: axi-clkgen: Round closest in round_rate() and recalc_rate() To minimize the rounding error round to the closest integer when calculating the result in the recalc_rate() and set_rate() callbacks. Also in order to improve precision multiply first and then divide. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-09-05 17:32:41 +08:00
tmp = (unsigned long long)*parent_rate * m;
tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
return min_t(unsigned long long, tmp, LONG_MAX);
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
}
clk: axi-clkgen: Add support for fractional dividers The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:47 +08:00
static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen,
unsigned int reg1, unsigned int reg2)
{
unsigned int val1, val2;
unsigned int div;
axi_clkgen_mmcm_read(axi_clkgen, reg2, &val2);
if (val2 & MMCM_CLKOUT_NOCOUNT)
return 8;
axi_clkgen_mmcm_read(axi_clkgen, reg1, &val1);
div = (val1 & 0x3f) + ((val1 >> 6) & 0x3f);
div <<= 3;
if (val2 & MMCM_CLK_DIV_DIVIDE) {
if ((val2 & BIT(7)) && (val2 & 0x7000) != 0x1000)
div += 8;
else
div += 16;
div += (val2 >> 12) & 0x7;
}
return div;
}
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
unsigned long parent_rate)
{
struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
unsigned int d, m, dout;
unsigned long long tmp;
clk: axi-clkgen: Add support for fractional dividers The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:47 +08:00
unsigned int val;
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
clk: axi-clkgen: Add support for fractional dividers The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:47 +08:00
dout = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLKOUT0_1,
MMCM_REG_CLKOUT0_2);
m = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLK_FB1,
MMCM_REG_CLK_FB2);
clk: axi-clkgen: Correctly handle nocount bit in recalc_rate() If the nocount bit is set the divider is bypassed and the settings for the divider count should be ignored and a divider value of 1 should be assumed. Handle this correctly in the driver recalc_rate() callback. While the driver sets up the part so that the read back dividers values yield the correct result the power-on reset settings of the part might not reflect this and hence calling e.g. clk_get_rate() without prior calls to clk_set_rate() will yield the wrong result. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-09-05 17:32:40 +08:00
clk: axi-clkgen: Add support for fractional dividers The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:47 +08:00
axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, &val);
if (val & MMCM_CLK_DIV_NOCOUNT)
clk: axi-clkgen: Correctly handle nocount bit in recalc_rate() If the nocount bit is set the divider is bypassed and the settings for the divider count should be ignored and a divider value of 1 should be assumed. Handle this correctly in the driver recalc_rate() callback. While the driver sets up the part so that the read back dividers values yield the correct result the power-on reset settings of the part might not reflect this and hence calling e.g. clk_get_rate() without prior calls to clk_set_rate() will yield the wrong result. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-09-05 17:32:40 +08:00
d = 1;
else
clk: axi-clkgen: Add support for fractional dividers The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-01 16:59:47 +08:00
d = (val & 0x3f) + ((val >> 6) & 0x3f);
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
if (d == 0 || dout == 0)
return 0;
clk: axi-clkgen: Round closest in round_rate() and recalc_rate() To minimize the rounding error round to the closest integer when calculating the result in the recalc_rate() and set_rate() callbacks. Also in order to improve precision multiply first and then divide. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-09-05 17:32:41 +08:00
tmp = (unsigned long long)parent_rate * m;
tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
clk: axi-clkgen: Remove sometimes impossible check The size of unsigned long on 64-bit architectures is equal to the size of u64, so this check is impossible there. This throws off static checkers: drivers/clk/clk-axi-clkgen.c:331 axi_clkgen_recalc_rate() warn: impossible condition '(tmp > (~0)) => (0-u64max > u64max)' Let's change this code to use min_t() instead so that we get the same effect on architectures where sizeof(unsigned long) doesn't equal sizeof(u64). Cc: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-01-30 09:09:01 +08:00
return min_t(unsigned long long, tmp, ULONG_MAX);
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
}
clk: axi-clkgen: Add support for v2 This patch adds support for the new v2 version of the axi-clkgen core. Unfortunately the method of accessing the registers is quite different on v2, while the content still stays largely the same. So the patch adds a small abstraction layer which implements the specific read and write functions for v1 and v2 in callback functions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-02-17 17:31:53 +08:00
static int axi_clkgen_enable(struct clk_hw *clk_hw)
{
struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
axi_clkgen_mmcm_enable(axi_clkgen, true);
return 0;
}
static void axi_clkgen_disable(struct clk_hw *clk_hw)
{
struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
axi_clkgen_mmcm_enable(axi_clkgen, false);
}
clk: axi-clkgen: Add multi-parent support The clock generator has two clock inputs that can be used as the reference clock. Add support for switching between them at runtime. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-12-01 00:54:56 +08:00
static int axi_clkgen_set_parent(struct clk_hw *clk_hw, u8 index)
{
struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, index);
return 0;
}
static u8 axi_clkgen_get_parent(struct clk_hw *clk_hw)
{
struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
unsigned int parent;
axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, &parent);
return parent;
}
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
static const struct clk_ops axi_clkgen_ops = {
.recalc_rate = axi_clkgen_recalc_rate,
.round_rate = axi_clkgen_round_rate,
.set_rate = axi_clkgen_set_rate,
clk: axi-clkgen: Add support for v2 This patch adds support for the new v2 version of the axi-clkgen core. Unfortunately the method of accessing the registers is quite different on v2, while the content still stays largely the same. So the patch adds a small abstraction layer which implements the specific read and write functions for v1 and v2 in callback functions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-02-17 17:31:53 +08:00
.enable = axi_clkgen_enable,
.disable = axi_clkgen_disable,
clk: axi-clkgen: Add multi-parent support The clock generator has two clock inputs that can be used as the reference clock. Add support for switching between them at runtime. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-12-01 00:54:56 +08:00
.set_parent = axi_clkgen_set_parent,
.get_parent = axi_clkgen_get_parent,
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
};
static int axi_clkgen_probe(struct platform_device *pdev)
{
clk: axi-clkgen: wrap limits in a struct and keep copy on the state object Up until the these limits were global/hard-coded, since they are typically limits of the fabric. However, since this is an FPGA generated clock, this may run on setups where one clock is on a fabric, and another one synthesized on another fabric connected via PCIe (or some other inter-connect, and then these limits need to be adjusted for each instance of the AXI CLKGEN. This change wraps the current constants in 'axi_clkgen_limits' struct and the 'axi_clkgen' instance keeps a copy of these limits, which is initialized at probe from the default limits. The limits are stored on the device-tree OF table, so that we can adjust them via the compatible string. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201203074037.26940-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-03 15:40:36 +08:00
const struct axi_clkgen_limits *dflt_limits;
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
struct axi_clkgen *axi_clkgen;
struct clk_init_data init;
clk: axi-clkgen: Add multi-parent support The clock generator has two clock inputs that can be used as the reference clock. Add support for switching between them at runtime. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-12-01 00:54:56 +08:00
const char *parent_names[2];
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
const char *clk_name;
clk: axi-clkgen: Add multi-parent support The clock generator has two clock inputs that can be used as the reference clock. Add support for switching between them at runtime. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-12-01 00:54:56 +08:00
unsigned int i;
clk: axi-clkgen: Migrate to clk_hw based OF and registration APIs Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. Cc: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-02 07:15:08 +08:00
int ret;
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
clk: axi-clkgen: wrap limits in a struct and keep copy on the state object Up until the these limits were global/hard-coded, since they are typically limits of the fabric. However, since this is an FPGA generated clock, this may run on setups where one clock is on a fabric, and another one synthesized on another fabric connected via PCIe (or some other inter-connect, and then these limits need to be adjusted for each instance of the AXI CLKGEN. This change wraps the current constants in 'axi_clkgen_limits' struct and the 'axi_clkgen' instance keeps a copy of these limits, which is initialized at probe from the default limits. The limits are stored on the device-tree OF table, so that we can adjust them via the compatible string. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201203074037.26940-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-03 15:40:36 +08:00
dflt_limits = device_get_match_data(&pdev->dev);
if (!dflt_limits)
clk: axi-clkgen: Add support for v2 This patch adds support for the new v2 version of the axi-clkgen core. Unfortunately the method of accessing the registers is quite different on v2, while the content still stays largely the same. So the patch adds a small abstraction layer which implements the specific read and write functions for v1 and v2 in callback functions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-02-17 17:31:53 +08:00
return -ENODEV;
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
axi_clkgen = devm_kzalloc(&pdev->dev, sizeof(*axi_clkgen), GFP_KERNEL);
if (!axi_clkgen)
return -ENOMEM;
clk: axi-clkgen: use devm_platform_ioremap_resource() short-hand No major functional change. Noticed while checking the driver code that this could be used. Saves two lines. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20210201151245.21845-5-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-01 23:12:45 +08:00
axi_clkgen->base = devm_platform_ioremap_resource(pdev, 0);
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
if (IS_ERR(axi_clkgen->base))
return PTR_ERR(axi_clkgen->base);
clk: axi-clkgen: Add multi-parent support The clock generator has two clock inputs that can be used as the reference clock. Add support for switching between them at runtime. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-12-01 00:54:56 +08:00
init.num_parents = of_clk_get_parent_count(pdev->dev.of_node);
if (init.num_parents < 1 || init.num_parents > 2)
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
return -EINVAL;
clk: axi-clkgen: Add multi-parent support The clock generator has two clock inputs that can be used as the reference clock. Add support for switching between them at runtime. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-12-01 00:54:56 +08:00
for (i = 0; i < init.num_parents; i++) {
parent_names[i] = of_clk_get_parent_name(pdev->dev.of_node, i);
if (!parent_names[i])
return -EINVAL;
}
clk: axi-clkgen: wrap limits in a struct and keep copy on the state object Up until the these limits were global/hard-coded, since they are typically limits of the fabric. However, since this is an FPGA generated clock, this may run on setups where one clock is on a fabric, and another one synthesized on another fabric connected via PCIe (or some other inter-connect, and then these limits need to be adjusted for each instance of the AXI CLKGEN. This change wraps the current constants in 'axi_clkgen_limits' struct and the 'axi_clkgen' instance keeps a copy of these limits, which is initialized at probe from the default limits. The limits are stored on the device-tree OF table, so that we can adjust them via the compatible string. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201203074037.26940-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-03 15:40:36 +08:00
memcpy(&axi_clkgen->limits, dflt_limits, sizeof(axi_clkgen->limits));
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
clk_name = pdev->dev.of_node->name;
of_property_read_string(pdev->dev.of_node, "clock-output-names",
&clk_name);
init.name = clk_name;
init.ops = &axi_clkgen_ops;
clk: axi-clkgen: Add multi-parent support The clock generator has two clock inputs that can be used as the reference clock. Add support for switching between them at runtime. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-12-01 00:54:56 +08:00
init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
init.parent_names = parent_names;
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
clk: axi-clkgen: Add support for v2 This patch adds support for the new v2 version of the axi-clkgen core. Unfortunately the method of accessing the registers is quite different on v2, while the content still stays largely the same. So the patch adds a small abstraction layer which implements the specific read and write functions for v1 and v2 in callback functions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-02-17 17:31:53 +08:00
axi_clkgen_mmcm_enable(axi_clkgen, false);
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
axi_clkgen->clk_hw.init = &init;
clk: axi-clkgen: Migrate to clk_hw based OF and registration APIs Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. Cc: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-02 07:15:08 +08:00
ret = devm_clk_hw_register(&pdev->dev, &axi_clkgen->clk_hw);
if (ret)
return ret;
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
clk: axi-clkgen: Migrate to clk_hw based OF and registration APIs Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. Cc: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-06-02 07:15:08 +08:00
return of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_simple_get,
&axi_clkgen->clk_hw);
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
}
static int axi_clkgen_remove(struct platform_device *pdev)
{
of_clk_del_provider(pdev->dev.of_node);
return 0;
}
clk: axi-clkgen: move the OF table at the bottom of the file The change is mostly cosmetic. No functional changes. Since the driver now uses of_device_get_match_data() to obtain some driver specific info, there is no need to define the OF table before the probe function. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201203074037.26940-2-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-03 15:40:37 +08:00
static const struct of_device_id axi_clkgen_ids[] = {
clk: clk-axiclkgen: add ZynqMP PFD and VCO limits For ZynqMP (Ultrascale) the PFD and VCO limits are different. In order to support these, this change adds a compatible string (i.e. 'adi,zynqmp-axi-clkgen-2.00.a') which will take into account for these limits and apply them. Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com> Signed-off-by: Mathias Tausen <mta@gomspace.com> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20210201151245.21845-3-alexandru.ardelean@analog.com Acked-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-01 23:12:43 +08:00
{
.compatible = "adi,zynqmp-axi-clkgen-2.00.a",
.data = &axi_clkgen_zynqmp_default_limits,
},
clk: axi-clkgen: move the OF table at the bottom of the file The change is mostly cosmetic. No functional changes. Since the driver now uses of_device_get_match_data() to obtain some driver specific info, there is no need to define the OF table before the probe function. Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201203074037.26940-2-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-12-03 15:40:37 +08:00
{
.compatible = "adi,axi-clkgen-2.00.a",
.data = &axi_clkgen_zynq_default_limits,
},
{ }
};
MODULE_DEVICE_TABLE(of, axi_clkgen_ids);
clk: Add axi-clkgen driver This driver adds support for the AXI clkgen pcore to the common clock framework. The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer commonly found in Xilinx FPGAs. The AXI clkgen pcore is used in Analog Devices' reference designs targeting Xilinx FPGAs. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-03-11 23:22:29 +08:00
static struct platform_driver axi_clkgen_driver = {
.driver = {
.name = "adi-axi-clkgen",
.of_match_table = axi_clkgen_ids,
},
.probe = axi_clkgen_probe,
.remove = axi_clkgen_remove,
};
module_platform_driver(axi_clkgen_driver);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
MODULE_DESCRIPTION("Driver for the Analog Devices' AXI clkgen pcore clock generator");