196 lines
5.7 KiB
C
196 lines
5.7 KiB
C
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/*
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* Copyright (C) 2003 - 2006 NetXen, Inc.
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston,
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* MA 02111-1307, USA.
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*
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.
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*
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* Contact Information:
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* info@netxen.com
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* NetXen,
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* 3965 Freedom Circle, Fourth floor,
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* Santa Clara, CA 95054
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*/
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#ifndef __NIC_PHAN_REG_H_
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#define __NIC_PHAN_REG_H_
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/*
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* CRB Registers or queue message done only at initialization time.
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*/
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/*
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* The following 2 are the base adresses for the CRB registers and their
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* offsets will be added to get addresses for the index addresses.
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*/
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#define NIC_CRB_BASE_PORT1 NETXEN_CAM_RAM(0x200)
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#define NIC_CRB_BASE_PORT2 NETXEN_CAM_RAM(0x250)
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#define NETXEN_NIC_REG(X) (NIC_CRB_BASE_PORT1+(X))
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/*
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* CrbPortPhanCntrHi/Lo is used to pass the address of HostPhantomIndex address
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* which can be read by the Phantom host to get producer/consumer indexes from
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* Phantom/Casper. If it is not HOST_SHARED_MEMORY, then the following
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* registers will be used for the addresses of the ring's shared memory
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* on the Phantom.
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*/
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#define CRB_PHAN_CNTRL_LO_OFFSET NETXEN_NIC_REG(0x00)
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#define CRB_PHAN_CNTRL_HI_OFFSET NETXEN_NIC_REG(0x04)
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/* point to the indexes */
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#define CRB_CMD_PRODUCER_OFFSET NETXEN_NIC_REG(0x08)
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#define CRB_CMD_CONSUMER_OFFSET NETXEN_NIC_REG(0x0c)
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/* address of command descriptors in the host memory */
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#define CRB_HOST_CMD_ADDR_HI NETXEN_NIC_REG(0x30)
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#define CRB_HOST_CMD_ADDR_LO NETXEN_NIC_REG(0x34)
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/* The following 4 CRB registers are for doing performance coal */
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#define CRB_CMD_INTR_LOOP NETXEN_NIC_REG(0x38)
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#define CRB_CMD_DMA_LOOP NETXEN_NIC_REG(0x3c)
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#define CRB_RCV_INTR_LOOP NETXEN_NIC_REG(0x40)
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#define CRB_RCV_DMA_LOOP NETXEN_NIC_REG(0x44)
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/* Needed by the host to find out the state of Phantom's initialization */
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#define CRB_ENABLE_TX_INTR NETXEN_NIC_REG(0x4c)
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#define CRB_CMDPEG_STATE NETXEN_NIC_REG(0x50)
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#define CRB_CMDPEG_CMDRING NETXEN_NIC_REG(0x54)
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/* Interrupt coalescing parameters */
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#define CRB_GLOBAL_INT_COAL NETXEN_NIC_REG(0x80)
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#define CRB_INT_COAL_MODE NETXEN_NIC_REG(0x84)
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#define CRB_MAX_RCV_BUFS NETXEN_NIC_REG(0x88)
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#define CRB_TX_INT_THRESHOLD NETXEN_NIC_REG(0x8c)
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#define CRB_RX_PKT_TIMER NETXEN_NIC_REG(0x90)
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#define CRB_TX_PKT_TIMER NETXEN_NIC_REG(0x94)
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#define CRB_RX_PKT_CNT NETXEN_NIC_REG(0x98)
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#define CRB_RX_TMR_CNT NETXEN_NIC_REG(0x9c)
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/* Register for communicating XG link status */
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#define CRB_XG_STATE NETXEN_NIC_REG(0xa0)
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/* Debug registers for controlling NIC pkt gen agent */
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#define CRB_AGENT_GO NETXEN_NIC_REG(0xb0)
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#define CRB_AGENT_TX_SIZE NETXEN_NIC_REG(0xb4)
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#define CRB_AGENT_TX_TYPE NETXEN_NIC_REG(0xb8)
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#define CRB_AGENT_TX_ADDR NETXEN_NIC_REG(0xbc)
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#define CRB_AGENT_TX_MSS NETXEN_NIC_REG(0xc0)
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/* Debug registers for observing NIC performance */
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#define CRB_TX_STATE NETXEN_NIC_REG(0xd0)
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#define CRB_TX_COUNT NETXEN_NIC_REG(0xd4)
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#define CRB_RX_STATE NETXEN_NIC_REG(0xd8)
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/* CRB registers per Rcv Descriptor ring */
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struct netxen_rcv_desc_crb {
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u32 crb_rcv_producer_offset __attribute__ ((aligned(512)));
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u32 crb_rcv_consumer_offset;
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u32 crb_globalrcv_ring;
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};
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/*
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* CRB registers used by the receive peg logic. One instance of these
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* needs to be instantiated per instance of the receive peg.
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*/
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struct netxen_recv_crb {
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struct netxen_rcv_desc_crb rcv_desc_crb[NUM_RCV_DESC_RINGS];
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u32 crb_rcvstatus_ring;
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u32 crb_rcv_status_producer;
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u32 crb_rcv_status_consumer;
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u32 crb_rcvpeg_state;
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};
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#if defined(DEFINE_GLOBAL_RECV_CRB)
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struct netxen_recv_crb recv_crb_registers[] = {
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/*
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* Instance 0.
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*/
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{
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/* rcv_desc_crb: */
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{
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{
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/* crb_rcv_producer_offset: */
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NETXEN_NIC_REG(0x18),
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/* crb_rcv_consumer_offset: */
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NETXEN_NIC_REG(0x1c),
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/* crb_gloablrcv_ring: */
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NETXEN_NIC_REG(0x20),
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},
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/* Jumbo frames */
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{
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/* crb_rcv_producer_offset: */
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NETXEN_NIC_REG(0x100),
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/* crb_rcv_consumer_offset: */
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NETXEN_NIC_REG(0x104),
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/* crb_gloablrcv_ring: */
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NETXEN_NIC_REG(0x108),
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}
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},
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/* crb_rcvstatus_ring: */
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NETXEN_NIC_REG(0x24),
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/* crb_rcv_status_producer: */
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NETXEN_NIC_REG(0x28),
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/* crb_rcv_status_consumer: */
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NETXEN_NIC_REG(0x2c),
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/* crb_rcvpeg_state: */
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NETXEN_NIC_REG(0x48),
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},
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/*
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* Instance 1,
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*/
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{
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/* rcv_desc_crb: */
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{
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{
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/* crb_rcv_producer_offset: */
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NETXEN_NIC_REG(0x80),
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/* crb_rcv_consumer_offset: */
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NETXEN_NIC_REG(0x84),
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/* crb_globalrcv_ring: */
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NETXEN_NIC_REG(0x88),
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},
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/* Jumbo frames */
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{
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/* crb_rcv_producer_offset: */
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NETXEN_NIC_REG(0x10C),
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/* crb_rcv_consumer_offset: */
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NETXEN_NIC_REG(0x110),
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/* crb_globalrcv_ring: */
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NETXEN_NIC_REG(0x114),
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}
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},
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/* crb_rcvstatus_ring: */
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NETXEN_NIC_REG(0x8c),
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/* crb_rcv_status_producer: */
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NETXEN_NIC_REG(0x90),
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/* crb_rcv_status_consumer: */
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NETXEN_NIC_REG(0x94),
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/* crb_rcvpeg_state: */
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NETXEN_NIC_REG(0x98),
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},
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};
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#else
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extern struct netxen_recv_crb recv_crb_registers[];
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#endif /* DEFINE_GLOBAL_RECEIVE_CRB */
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#endif /* __NIC_PHAN_REG_H_ */
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