2014-09-30 16:56:38 +08:00
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/*
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* Copyright © 2012-2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eugeni Dodonov <eugeni.dodonov@intel.com>
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* Daniel Vetter <daniel.vetter@ffwll.ch>
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*
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*/
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#include <linux/pm_runtime.h>
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#include <linux/vgaarb.h>
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#include "i915_drv.h"
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#include "intel_drv.h"
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2014-09-30 16:56:42 +08:00
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/**
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* DOC: runtime pm
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*
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* The i915 driver supports dynamic enabling and disabling of entire hardware
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* blocks at runtime. This is especially important on the display side where
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* software is supposed to control many power gates manually on recent hardware,
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* since on the GT side a lot of the power management is done by the hardware.
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* But even there some manual control at the device level is required.
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*
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* Since i915 supports a diverse set of platforms with a unified codebase and
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* hardware engineers just love to shuffle functionality around between power
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* domains there's a sizeable amount of indirection required. This file provides
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* generic functions to the driver for grabbing and releasing references for
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* abstract power domains. It then maps those to the actual power wells
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* present for a given platform.
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*/
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2015-04-16 16:52:11 +08:00
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#define GEN9_ENABLE_DC5(dev) 0
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#define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev)
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drm/i915/skl: Add DC5 Trigger Sequence
Add triggers as per expectations mentioned in gen9_enable_dc5
and gen9_disable_dc5 patch.
Also call POSTING_READ for every write to a register to ensure that
its written immediately.
v1: Remove POSTING_READ calls as they've already been added in previous patches.
v2: Rebase to move all runtime pm specific changes to intel_runtime_pm.c file.
Modified as per review comments from Imre:
1] Change variable name 'dc5_allowed' to 'dc5_enabled' to correspond to relevant
functions.
2] Move the check dc5_enabled in skl_set_power_well() to disable DC5 into
gen9_disable_DC5 which is a more appropriate place.
3] Convert checks for 'pm.dc5_enabled' and 'pm.suspended' in skl_set_power_well()
to warnings. However, removing them for now as they'll be included in a future patch
asserting DC-state entry/exit criteria.
4] Enable DC5, only when CSR firmware is verified to be loaded. Create new structure
to track 'enabled' and 'deferred' status of DC5.
5] Ensure runtime PM reference is obtained, if CSR is not loaded, to avoid entering
runtime-suspend and release it when it's loaded.
6] Protect necessary CSR-related code with locks.
7] Move CSR-loading call to runtime PM initialization, as power domains needed to be
accessed during deferred DC5-enabling, are not initialized earlier.
v3: Rebase to latest.
Modified as per review comments from Imre:
1] Use blocking wait for CSR-loading to finish to enable DC5 for simplicity, instead of
deferring enabling DC5 until CSR is loaded.
2] Obtain runtime PM reference during CSR-loading initialization itself as deferred DC5-
enabling is removed and release it at the end of CSR-loading functionality.
3] Revert calling CSR-loading functionality to the beginning of i915 driver-load
functionality to avoid any delay in loading.
4] Define another variable to track whether CSR-loading failed and use it to avoid enabling
DC5 if it's true.
5] Define CSR-load-status accessor functions for use later.
v4:
1] Disable DC5 before enabling PG2 instead of after it.
2] DC5 was being mistaken enabled even when CSR-loading timed-out. Fix that.
3] Enable DC5-related functionality using a macro.
4] Remove dc5_enabled tracking variable and its use as it's not needed now.
v5:
1] Mark CSR failed to load where necessary in finish_csr_load function.
2] Use mutex-protected accessor function to check if CSR loaded instead of directly
accessing the variable.
3] Prefix csr_load_status_get/set function names with intel_.
v6: rebase to latest.
v7: Rebase on top of nightly (Damien)
v8: Squashed the patch from Imre - added csr helper pointers to simplify the code. (Imre)
v9: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)
v10: Added a enum for different csr states, suggested by Imre. (Animesh)
v11: Based on review comments from Imre, Damien and Daniel following changes done
- enum name chnaged to csr_state (singular form).
- FW_UNINITIALIZED used as zeroth element in enum csr_state.
- Prototype changed for helper function(set/get csr status), using enum csr_state instead of bool.
v12: Based on review comment from Imre, introduced bool fw_loaded local to finish_csr_load() which helps
calling once to set the csr status. The same flag used to fail RPM if find any issue during
firmware loading.
Issue: VIZ-2819
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Suketu Shah <suketu.j.shah@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-04-17 22:16:16 +08:00
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2014-09-30 16:56:38 +08:00
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#define for_each_power_well(i, power_well, domain_mask, power_domains) \
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for (i = 0; \
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i < (power_domains)->power_well_count && \
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((power_well) = &(power_domains)->power_wells[i]); \
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i++) \
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if ((power_well)->domains & (domain_mask))
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#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
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for (i = (power_domains)->power_well_count - 1; \
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i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
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i--) \
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if ((power_well)->domains & (domain_mask))
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2015-04-16 16:52:10 +08:00
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bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
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int power_well_id);
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2015-07-31 05:20:26 +08:00
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static void intel_power_well_enable(struct drm_i915_private *dev_priv,
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struct i915_power_well *power_well)
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{
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DRM_DEBUG_KMS("enabling %s\n", power_well->name);
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power_well->ops->enable(dev_priv, power_well);
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power_well->hw_enabled = true;
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}
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2015-07-31 05:20:27 +08:00
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static void intel_power_well_disable(struct drm_i915_private *dev_priv,
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struct i915_power_well *power_well)
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{
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DRM_DEBUG_KMS("disabling %s\n", power_well->name);
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power_well->hw_enabled = false;
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power_well->ops->disable(dev_priv, power_well);
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}
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2014-09-30 16:56:42 +08:00
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/*
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2014-09-30 16:56:38 +08:00
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* We should only use the power well if we explicitly asked the hardware to
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* enable it, so check if it's enabled and also check if we've requested it to
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* be enabled.
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*/
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static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
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struct i915_power_well *power_well)
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{
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return I915_READ(HSW_PWR_WELL_DRIVER) ==
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(HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
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}
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2014-09-30 16:56:42 +08:00
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/**
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* __intel_display_power_is_enabled - unlocked check for a power domain
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* @dev_priv: i915 device instance
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* @domain: power domain to check
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*
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* This is the unlocked version of intel_display_power_is_enabled() and should
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* only be used from error capture and recovery code where deadlocks are
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* possible.
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*
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* Returns:
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* True when the power domain is enabled, false otherwise.
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*/
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2014-09-30 16:56:39 +08:00
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bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
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enum intel_display_power_domain domain)
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2014-09-30 16:56:38 +08:00
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{
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struct i915_power_domains *power_domains;
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struct i915_power_well *power_well;
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bool is_enabled;
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int i;
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if (dev_priv->pm.suspended)
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return false;
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power_domains = &dev_priv->power_domains;
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is_enabled = true;
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for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
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if (power_well->always_on)
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continue;
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if (!power_well->hw_enabled) {
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is_enabled = false;
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break;
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}
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}
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return is_enabled;
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}
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2014-09-30 16:56:42 +08:00
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/**
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2014-11-25 21:45:41 +08:00
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* intel_display_power_is_enabled - check for a power domain
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2014-09-30 16:56:42 +08:00
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* @dev_priv: i915 device instance
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* @domain: power domain to check
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*
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* This function can be used to check the hw power domain state. It is mostly
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* used in hardware state readout functions. Everywhere else code should rely
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* upon explicit power domain reference counting to ensure that the hardware
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* block is powered up before accessing it.
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*
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* Callers must hold the relevant modesetting locks to ensure that concurrent
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* threads can't disable the power well while the caller tries to read a few
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* registers.
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*
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* Returns:
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* True when the power domain is enabled, false otherwise.
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*/
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2014-09-30 16:56:39 +08:00
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bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
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enum intel_display_power_domain domain)
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2014-09-30 16:56:38 +08:00
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{
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struct i915_power_domains *power_domains;
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bool ret;
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power_domains = &dev_priv->power_domains;
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mutex_lock(&power_domains->lock);
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2014-09-30 16:56:39 +08:00
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ret = __intel_display_power_is_enabled(dev_priv, domain);
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2014-09-30 16:56:38 +08:00
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mutex_unlock(&power_domains->lock);
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return ret;
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}
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2014-09-30 16:56:42 +08:00
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/**
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* intel_display_set_init_power - set the initial power domain state
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* @dev_priv: i915 device instance
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* @enable: whether to enable or disable the initial power domain state
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*
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* For simplicity our driver load/unload and system suspend/resume code assumes
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* that all power domains are always enabled. This functions controls the state
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* of this little hack. While the initial power domain state is enabled runtime
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* pm is effectively disabled.
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*/
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2014-09-30 16:56:40 +08:00
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void intel_display_set_init_power(struct drm_i915_private *dev_priv,
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bool enable)
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{
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if (dev_priv->power_domains.init_power_on == enable)
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return;
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if (enable)
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intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
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else
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intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
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dev_priv->power_domains.init_power_on = enable;
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}
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2014-09-30 16:56:38 +08:00
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/*
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* Starting with Haswell, we have a "Power Down Well" that can be turned off
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* when not needed anymore. We have 4 registers that can request the power well
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* to be enabled, and it will only be disabled if none of the registers is
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* requesting it to be enabled.
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*/
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static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
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{
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struct drm_device *dev = dev_priv->dev;
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/*
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* After we re-enable the power well, if we touch VGA register 0x3d5
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* we'll get unclaimed register interrupts. This stops after we write
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* anything to the VGA MSR register. The vgacon module uses this
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* register all the time, so if we unbind our driver and, as a
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* consequence, bind vgacon, we'll get stuck in an infinite loop at
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* console_unlock(). So make here we touch the VGA MSR register, making
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* sure vgacon can keep working normally without triggering interrupts
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* and error messages.
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*/
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vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
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outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
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vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
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2015-03-07 02:50:52 +08:00
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if (IS_BROADWELL(dev))
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2015-03-07 02:50:48 +08:00
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gen8_irq_power_well_post_enable(dev_priv,
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1 << PIPE_C | 1 << PIPE_B);
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2014-09-30 16:56:38 +08:00
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}
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2015-03-07 02:50:51 +08:00
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static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
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struct i915_power_well *power_well)
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{
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struct drm_device *dev = dev_priv->dev;
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/*
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* After we re-enable the power well, if we touch VGA register 0x3d5
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* we'll get unclaimed register interrupts. This stops after we write
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* anything to the VGA MSR register. The vgacon module uses this
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* register all the time, so if we unbind our driver and, as a
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* consequence, bind vgacon, we'll get stuck in an infinite loop at
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* console_unlock(). So make here we touch the VGA MSR register, making
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* sure vgacon can keep working normally without triggering interrupts
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* and error messages.
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*/
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if (power_well->data == SKL_DISP_PW_2) {
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vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
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outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
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vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
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gen8_irq_power_well_post_enable(dev_priv,
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1 << PIPE_C | 1 << PIPE_B);
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}
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}
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2014-09-30 16:56:38 +08:00
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static void hsw_set_power_well(struct drm_i915_private *dev_priv,
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struct i915_power_well *power_well, bool enable)
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{
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bool is_enabled, enable_requested;
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uint32_t tmp;
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tmp = I915_READ(HSW_PWR_WELL_DRIVER);
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is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
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enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
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if (enable) {
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if (!enable_requested)
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I915_WRITE(HSW_PWR_WELL_DRIVER,
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HSW_PWR_WELL_ENABLE_REQUEST);
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if (!is_enabled) {
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DRM_DEBUG_KMS("Enabling power well\n");
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if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
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HSW_PWR_WELL_STATE_ENABLED), 20))
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DRM_ERROR("Timeout enabling power well\n");
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2014-10-08 03:11:11 +08:00
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hsw_power_well_post_enable(dev_priv);
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2014-09-30 16:56:38 +08:00
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}
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} else {
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if (enable_requested) {
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I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
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POSTING_READ(HSW_PWR_WELL_DRIVER);
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DRM_DEBUG_KMS("Requesting to disable the power well\n");
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}
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}
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}
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2015-02-04 21:57:44 +08:00
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#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
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|
BIT(POWER_DOMAIN_TRANSCODER_A) | \
|
|
|
|
BIT(POWER_DOMAIN_PIPE_B) | \
|
|
|
|
BIT(POWER_DOMAIN_TRANSCODER_B) | \
|
|
|
|
BIT(POWER_DOMAIN_PIPE_C) | \
|
|
|
|
BIT(POWER_DOMAIN_TRANSCODER_C) | \
|
|
|
|
BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
|
|
|
|
BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
|
2015-08-13 18:00:12 +08:00
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \
|
2015-02-04 21:57:44 +08:00
|
|
|
BIT(POWER_DOMAIN_AUX_B) | \
|
|
|
|
BIT(POWER_DOMAIN_AUX_C) | \
|
|
|
|
BIT(POWER_DOMAIN_AUX_D) | \
|
|
|
|
BIT(POWER_DOMAIN_AUDIO) | \
|
|
|
|
BIT(POWER_DOMAIN_VGA) | \
|
|
|
|
BIT(POWER_DOMAIN_INIT))
|
|
|
|
#define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
|
2015-08-13 18:00:12 +08:00
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \
|
2015-02-04 21:57:44 +08:00
|
|
|
BIT(POWER_DOMAIN_INIT))
|
|
|
|
#define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_INIT))
|
|
|
|
#define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_INIT))
|
|
|
|
#define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_INIT))
|
|
|
|
#define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
|
2015-11-05 01:24:15 +08:00
|
|
|
(POWER_DOMAIN_MASK & ~( \
|
2015-11-09 23:48:20 +08:00
|
|
|
SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
|
2015-02-04 21:57:44 +08:00
|
|
|
BIT(POWER_DOMAIN_INIT))
|
|
|
|
|
2014-07-11 17:21:13 +08:00
|
|
|
#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
|
|
|
|
BIT(POWER_DOMAIN_TRANSCODER_A) | \
|
|
|
|
BIT(POWER_DOMAIN_PIPE_B) | \
|
|
|
|
BIT(POWER_DOMAIN_TRANSCODER_B) | \
|
|
|
|
BIT(POWER_DOMAIN_PIPE_C) | \
|
|
|
|
BIT(POWER_DOMAIN_TRANSCODER_C) | \
|
|
|
|
BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
|
|
|
|
BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_AUX_B) | \
|
|
|
|
BIT(POWER_DOMAIN_AUX_C) | \
|
|
|
|
BIT(POWER_DOMAIN_AUDIO) | \
|
|
|
|
BIT(POWER_DOMAIN_VGA) | \
|
2015-11-09 23:48:19 +08:00
|
|
|
BIT(POWER_DOMAIN_GMBUS) | \
|
2014-07-11 17:21:13 +08:00
|
|
|
BIT(POWER_DOMAIN_INIT))
|
|
|
|
#define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \
|
|
|
|
BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
|
|
|
|
BIT(POWER_DOMAIN_PIPE_A) | \
|
|
|
|
BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
|
|
|
|
BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_AUX_A) | \
|
|
|
|
BIT(POWER_DOMAIN_PLLS) | \
|
|
|
|
BIT(POWER_DOMAIN_INIT))
|
|
|
|
#define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
|
|
|
|
(POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
|
|
|
|
BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
|
|
|
|
BIT(POWER_DOMAIN_INIT))
|
|
|
|
|
2014-11-24 16:07:44 +08:00
|
|
|
static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = dev_priv->dev;
|
|
|
|
|
|
|
|
WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");
|
|
|
|
WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
|
|
|
|
"DC9 already programmed to be enabled.\n");
|
|
|
|
WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
|
|
|
|
"DC5 still not disabled to enable DC9.\n");
|
|
|
|
WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
|
|
|
|
WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
|
|
|
|
|
|
|
|
/*
|
|
|
|
* TODO: check for the following to verify the conditions to enter DC9
|
|
|
|
* state are satisfied:
|
|
|
|
* 1] Check relevant display engine registers to verify if mode set
|
|
|
|
* disable sequence was followed.
|
|
|
|
* 2] Check if display uninitialize sequence is initialized.
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
|
|
|
|
static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
|
|
|
|
WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
|
|
|
|
"DC9 already programmed to be disabled.\n");
|
|
|
|
WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
|
|
|
|
"DC5 still not disabled.\n");
|
|
|
|
|
|
|
|
/*
|
|
|
|
* TODO: check for the following to verify DC9 state was indeed
|
|
|
|
* entered before programming to disable it:
|
|
|
|
* 1] Check relevant display engine registers to verify if mode
|
|
|
|
* set disable sequence was followed.
|
|
|
|
* 2] Check if display uninitialize sequence is initialized.
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
|
2015-11-09 23:48:17 +08:00
|
|
|
static void gen9_set_dc_state_debugmask_memory_up(
|
|
|
|
struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
uint32_t val;
|
|
|
|
|
|
|
|
/* The below bit doesn't need to be cleared ever afterwards */
|
|
|
|
val = I915_READ(DC_STATE_DEBUG);
|
|
|
|
if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
|
|
|
|
val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
|
|
|
|
I915_WRITE(DC_STATE_DEBUG, val);
|
|
|
|
POSTING_READ(DC_STATE_DEBUG);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-11-05 01:24:16 +08:00
|
|
|
static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
|
2014-11-24 16:07:44 +08:00
|
|
|
{
|
|
|
|
uint32_t val;
|
2015-11-05 01:24:16 +08:00
|
|
|
uint32_t mask;
|
2014-11-24 16:07:44 +08:00
|
|
|
|
2015-11-05 01:24:16 +08:00
|
|
|
mask = DC_STATE_EN_UPTO_DC5;
|
|
|
|
if (IS_BROXTON(dev_priv))
|
|
|
|
mask |= DC_STATE_EN_DC9;
|
|
|
|
else
|
|
|
|
mask |= DC_STATE_EN_UPTO_DC6;
|
2014-11-24 16:07:44 +08:00
|
|
|
|
2015-11-05 01:24:16 +08:00
|
|
|
WARN_ON_ONCE(state & ~mask);
|
2014-11-24 16:07:44 +08:00
|
|
|
|
2015-11-09 23:48:17 +08:00
|
|
|
if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK)
|
|
|
|
gen9_set_dc_state_debugmask_memory_up(dev_priv);
|
|
|
|
|
2014-11-24 16:07:44 +08:00
|
|
|
val = I915_READ(DC_STATE_EN);
|
2015-11-05 01:24:16 +08:00
|
|
|
DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
|
|
|
|
val & mask, state);
|
|
|
|
val &= ~mask;
|
|
|
|
val |= state;
|
2014-11-24 16:07:44 +08:00
|
|
|
I915_WRITE(DC_STATE_EN, val);
|
|
|
|
POSTING_READ(DC_STATE_EN);
|
|
|
|
}
|
|
|
|
|
2015-11-05 01:24:16 +08:00
|
|
|
void bxt_enable_dc9(struct drm_i915_private *dev_priv)
|
2014-11-24 16:07:44 +08:00
|
|
|
{
|
2015-11-05 01:24:16 +08:00
|
|
|
assert_can_enable_dc9(dev_priv);
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Enabling DC9\n");
|
2014-11-24 16:07:44 +08:00
|
|
|
|
2015-11-05 01:24:16 +08:00
|
|
|
gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
|
|
|
|
}
|
|
|
|
|
|
|
|
void bxt_disable_dc9(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
2014-11-24 16:07:44 +08:00
|
|
|
assert_can_disable_dc9(dev_priv);
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Disabling DC9\n");
|
|
|
|
|
2015-11-05 01:24:16 +08:00
|
|
|
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
|
2014-11-24 16:07:44 +08:00
|
|
|
}
|
|
|
|
|
2015-10-29 05:58:57 +08:00
|
|
|
static void assert_csr_loaded(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
|
|
|
|
"CSR program storage start is NULL\n");
|
|
|
|
WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
|
|
|
|
WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
|
|
|
|
}
|
|
|
|
|
2015-04-16 16:52:10 +08:00
|
|
|
static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
|
drm/i915/skl: Add DC5 Trigger Sequence
Add triggers as per expectations mentioned in gen9_enable_dc5
and gen9_disable_dc5 patch.
Also call POSTING_READ for every write to a register to ensure that
its written immediately.
v1: Remove POSTING_READ calls as they've already been added in previous patches.
v2: Rebase to move all runtime pm specific changes to intel_runtime_pm.c file.
Modified as per review comments from Imre:
1] Change variable name 'dc5_allowed' to 'dc5_enabled' to correspond to relevant
functions.
2] Move the check dc5_enabled in skl_set_power_well() to disable DC5 into
gen9_disable_DC5 which is a more appropriate place.
3] Convert checks for 'pm.dc5_enabled' and 'pm.suspended' in skl_set_power_well()
to warnings. However, removing them for now as they'll be included in a future patch
asserting DC-state entry/exit criteria.
4] Enable DC5, only when CSR firmware is verified to be loaded. Create new structure
to track 'enabled' and 'deferred' status of DC5.
5] Ensure runtime PM reference is obtained, if CSR is not loaded, to avoid entering
runtime-suspend and release it when it's loaded.
6] Protect necessary CSR-related code with locks.
7] Move CSR-loading call to runtime PM initialization, as power domains needed to be
accessed during deferred DC5-enabling, are not initialized earlier.
v3: Rebase to latest.
Modified as per review comments from Imre:
1] Use blocking wait for CSR-loading to finish to enable DC5 for simplicity, instead of
deferring enabling DC5 until CSR is loaded.
2] Obtain runtime PM reference during CSR-loading initialization itself as deferred DC5-
enabling is removed and release it at the end of CSR-loading functionality.
3] Revert calling CSR-loading functionality to the beginning of i915 driver-load
functionality to avoid any delay in loading.
4] Define another variable to track whether CSR-loading failed and use it to avoid enabling
DC5 if it's true.
5] Define CSR-load-status accessor functions for use later.
v4:
1] Disable DC5 before enabling PG2 instead of after it.
2] DC5 was being mistaken enabled even when CSR-loading timed-out. Fix that.
3] Enable DC5-related functionality using a macro.
4] Remove dc5_enabled tracking variable and its use as it's not needed now.
v5:
1] Mark CSR failed to load where necessary in finish_csr_load function.
2] Use mutex-protected accessor function to check if CSR loaded instead of directly
accessing the variable.
3] Prefix csr_load_status_get/set function names with intel_.
v6: rebase to latest.
v7: Rebase on top of nightly (Damien)
v8: Squashed the patch from Imre - added csr helper pointers to simplify the code. (Imre)
v9: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)
v10: Added a enum for different csr states, suggested by Imre. (Animesh)
v11: Based on review comments from Imre, Damien and Daniel following changes done
- enum name chnaged to csr_state (singular form).
- FW_UNINITIALIZED used as zeroth element in enum csr_state.
- Prototype changed for helper function(set/get csr status), using enum csr_state instead of bool.
v12: Based on review comment from Imre, introduced bool fw_loaded local to finish_csr_load() which helps
calling once to set the csr status. The same flag used to fail RPM if find any issue during
firmware loading.
Issue: VIZ-2819
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Suketu Shah <suketu.j.shah@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-04-17 22:16:16 +08:00
|
|
|
{
|
2015-04-16 16:52:09 +08:00
|
|
|
struct drm_device *dev = dev_priv->dev;
|
2015-04-16 16:52:10 +08:00
|
|
|
bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
|
|
|
|
SKL_DISP_PW_2);
|
|
|
|
|
2015-09-10 23:20:28 +08:00
|
|
|
WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n");
|
|
|
|
WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
|
|
|
|
WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
|
2015-04-16 16:52:10 +08:00
|
|
|
|
2015-09-10 23:20:28 +08:00
|
|
|
WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
|
|
|
|
"DC5 already programmed to be enabled.\n");
|
|
|
|
WARN_ONCE(dev_priv->pm.suspended,
|
|
|
|
"DC5 cannot be enabled, if platform is runtime-suspended.\n");
|
2015-04-16 16:52:10 +08:00
|
|
|
|
|
|
|
assert_csr_loaded(dev_priv);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
|
|
|
|
SKL_DISP_PW_2);
|
2015-04-16 16:52:13 +08:00
|
|
|
/*
|
|
|
|
* During initialization, the firmware may not be loaded yet.
|
|
|
|
* We still want to make sure that the DC enabling flag is cleared.
|
|
|
|
*/
|
|
|
|
if (dev_priv->power_domains.initializing)
|
|
|
|
return;
|
2015-04-16 16:52:10 +08:00
|
|
|
|
2015-09-10 23:20:28 +08:00
|
|
|
WARN_ONCE(!pg2_enabled, "PG2 not enabled to disable DC5.\n");
|
|
|
|
WARN_ONCE(dev_priv->pm.suspended,
|
2015-04-16 16:52:10 +08:00
|
|
|
"Disabling of DC5 while platform is runtime-suspended should never happen.\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
assert_can_enable_dc5(dev_priv);
|
2015-04-16 16:52:09 +08:00
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Enabling DC5\n");
|
|
|
|
|
2015-11-05 01:24:16 +08:00
|
|
|
gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
|
drm/i915/skl: Add DC5 Trigger Sequence
Add triggers as per expectations mentioned in gen9_enable_dc5
and gen9_disable_dc5 patch.
Also call POSTING_READ for every write to a register to ensure that
its written immediately.
v1: Remove POSTING_READ calls as they've already been added in previous patches.
v2: Rebase to move all runtime pm specific changes to intel_runtime_pm.c file.
Modified as per review comments from Imre:
1] Change variable name 'dc5_allowed' to 'dc5_enabled' to correspond to relevant
functions.
2] Move the check dc5_enabled in skl_set_power_well() to disable DC5 into
gen9_disable_DC5 which is a more appropriate place.
3] Convert checks for 'pm.dc5_enabled' and 'pm.suspended' in skl_set_power_well()
to warnings. However, removing them for now as they'll be included in a future patch
asserting DC-state entry/exit criteria.
4] Enable DC5, only when CSR firmware is verified to be loaded. Create new structure
to track 'enabled' and 'deferred' status of DC5.
5] Ensure runtime PM reference is obtained, if CSR is not loaded, to avoid entering
runtime-suspend and release it when it's loaded.
6] Protect necessary CSR-related code with locks.
7] Move CSR-loading call to runtime PM initialization, as power domains needed to be
accessed during deferred DC5-enabling, are not initialized earlier.
v3: Rebase to latest.
Modified as per review comments from Imre:
1] Use blocking wait for CSR-loading to finish to enable DC5 for simplicity, instead of
deferring enabling DC5 until CSR is loaded.
2] Obtain runtime PM reference during CSR-loading initialization itself as deferred DC5-
enabling is removed and release it at the end of CSR-loading functionality.
3] Revert calling CSR-loading functionality to the beginning of i915 driver-load
functionality to avoid any delay in loading.
4] Define another variable to track whether CSR-loading failed and use it to avoid enabling
DC5 if it's true.
5] Define CSR-load-status accessor functions for use later.
v4:
1] Disable DC5 before enabling PG2 instead of after it.
2] DC5 was being mistaken enabled even when CSR-loading timed-out. Fix that.
3] Enable DC5-related functionality using a macro.
4] Remove dc5_enabled tracking variable and its use as it's not needed now.
v5:
1] Mark CSR failed to load where necessary in finish_csr_load function.
2] Use mutex-protected accessor function to check if CSR loaded instead of directly
accessing the variable.
3] Prefix csr_load_status_get/set function names with intel_.
v6: rebase to latest.
v7: Rebase on top of nightly (Damien)
v8: Squashed the patch from Imre - added csr helper pointers to simplify the code. (Imre)
v9: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)
v10: Added a enum for different csr states, suggested by Imre. (Animesh)
v11: Based on review comments from Imre, Damien and Daniel following changes done
- enum name chnaged to csr_state (singular form).
- FW_UNINITIALIZED used as zeroth element in enum csr_state.
- Prototype changed for helper function(set/get csr status), using enum csr_state instead of bool.
v12: Based on review comment from Imre, introduced bool fw_loaded local to finish_csr_load() which helps
calling once to set the csr status. The same flag used to fail RPM if find any issue during
firmware loading.
Issue: VIZ-2819
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Suketu Shah <suketu.j.shah@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-04-17 22:16:16 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
2015-04-16 16:52:10 +08:00
|
|
|
assert_can_disable_dc5(dev_priv);
|
2015-04-16 16:52:09 +08:00
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Disabling DC5\n");
|
|
|
|
|
2015-11-05 01:24:16 +08:00
|
|
|
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
|
drm/i915/skl: Add DC5 Trigger Sequence
Add triggers as per expectations mentioned in gen9_enable_dc5
and gen9_disable_dc5 patch.
Also call POSTING_READ for every write to a register to ensure that
its written immediately.
v1: Remove POSTING_READ calls as they've already been added in previous patches.
v2: Rebase to move all runtime pm specific changes to intel_runtime_pm.c file.
Modified as per review comments from Imre:
1] Change variable name 'dc5_allowed' to 'dc5_enabled' to correspond to relevant
functions.
2] Move the check dc5_enabled in skl_set_power_well() to disable DC5 into
gen9_disable_DC5 which is a more appropriate place.
3] Convert checks for 'pm.dc5_enabled' and 'pm.suspended' in skl_set_power_well()
to warnings. However, removing them for now as they'll be included in a future patch
asserting DC-state entry/exit criteria.
4] Enable DC5, only when CSR firmware is verified to be loaded. Create new structure
to track 'enabled' and 'deferred' status of DC5.
5] Ensure runtime PM reference is obtained, if CSR is not loaded, to avoid entering
runtime-suspend and release it when it's loaded.
6] Protect necessary CSR-related code with locks.
7] Move CSR-loading call to runtime PM initialization, as power domains needed to be
accessed during deferred DC5-enabling, are not initialized earlier.
v3: Rebase to latest.
Modified as per review comments from Imre:
1] Use blocking wait for CSR-loading to finish to enable DC5 for simplicity, instead of
deferring enabling DC5 until CSR is loaded.
2] Obtain runtime PM reference during CSR-loading initialization itself as deferred DC5-
enabling is removed and release it at the end of CSR-loading functionality.
3] Revert calling CSR-loading functionality to the beginning of i915 driver-load
functionality to avoid any delay in loading.
4] Define another variable to track whether CSR-loading failed and use it to avoid enabling
DC5 if it's true.
5] Define CSR-load-status accessor functions for use later.
v4:
1] Disable DC5 before enabling PG2 instead of after it.
2] DC5 was being mistaken enabled even when CSR-loading timed-out. Fix that.
3] Enable DC5-related functionality using a macro.
4] Remove dc5_enabled tracking variable and its use as it's not needed now.
v5:
1] Mark CSR failed to load where necessary in finish_csr_load function.
2] Use mutex-protected accessor function to check if CSR loaded instead of directly
accessing the variable.
3] Prefix csr_load_status_get/set function names with intel_.
v6: rebase to latest.
v7: Rebase on top of nightly (Damien)
v8: Squashed the patch from Imre - added csr helper pointers to simplify the code. (Imre)
v9: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)
v10: Added a enum for different csr states, suggested by Imre. (Animesh)
v11: Based on review comments from Imre, Damien and Daniel following changes done
- enum name chnaged to csr_state (singular form).
- FW_UNINITIALIZED used as zeroth element in enum csr_state.
- Prototype changed for helper function(set/get csr status), using enum csr_state instead of bool.
v12: Based on review comment from Imre, introduced bool fw_loaded local to finish_csr_load() which helps
calling once to set the csr status. The same flag used to fail RPM if find any issue during
firmware loading.
Issue: VIZ-2819
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Suketu Shah <suketu.j.shah@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-04-17 22:16:16 +08:00
|
|
|
}
|
|
|
|
|
2015-04-16 16:52:13 +08:00
|
|
|
static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
|
2015-04-16 16:52:11 +08:00
|
|
|
{
|
2015-04-16 16:52:12 +08:00
|
|
|
struct drm_device *dev = dev_priv->dev;
|
2015-04-16 16:52:13 +08:00
|
|
|
|
2015-09-10 23:20:28 +08:00
|
|
|
WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n");
|
|
|
|
WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
|
|
|
|
WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
|
|
|
|
"Backlight is not disabled.\n");
|
|
|
|
WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
|
|
|
|
"DC6 already programmed to be enabled.\n");
|
2015-04-16 16:52:13 +08:00
|
|
|
|
|
|
|
assert_csr_loaded(dev_priv);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* During initialization, the firmware may not be loaded yet.
|
|
|
|
* We still want to make sure that the DC enabling flag is cleared.
|
|
|
|
*/
|
|
|
|
if (dev_priv->power_domains.initializing)
|
|
|
|
return;
|
|
|
|
|
2015-09-10 23:20:28 +08:00
|
|
|
WARN_ONCE(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
|
|
|
|
"DC6 already programmed to be disabled.\n");
|
2015-04-16 16:52:13 +08:00
|
|
|
}
|
|
|
|
|
2015-09-29 13:31:59 +08:00
|
|
|
void skl_enable_dc6(struct drm_i915_private *dev_priv)
|
2015-04-16 16:52:13 +08:00
|
|
|
{
|
|
|
|
assert_can_enable_dc6(dev_priv);
|
2015-04-16 16:52:12 +08:00
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Enabling DC6\n");
|
|
|
|
|
2015-11-05 01:24:16 +08:00
|
|
|
gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
|
|
|
|
|
2015-04-16 16:52:11 +08:00
|
|
|
}
|
|
|
|
|
2015-09-29 13:31:59 +08:00
|
|
|
void skl_disable_dc6(struct drm_i915_private *dev_priv)
|
2015-04-16 16:52:11 +08:00
|
|
|
{
|
2015-04-16 16:52:13 +08:00
|
|
|
assert_can_disable_dc6(dev_priv);
|
2015-04-16 16:52:12 +08:00
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Disabling DC6\n");
|
|
|
|
|
2015-11-05 01:24:16 +08:00
|
|
|
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
|
2015-04-16 16:52:11 +08:00
|
|
|
}
|
|
|
|
|
2015-02-04 21:57:44 +08:00
|
|
|
static void skl_set_power_well(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well, bool enable)
|
|
|
|
{
|
drm/i915/skl: Add DC5 Trigger Sequence
Add triggers as per expectations mentioned in gen9_enable_dc5
and gen9_disable_dc5 patch.
Also call POSTING_READ for every write to a register to ensure that
its written immediately.
v1: Remove POSTING_READ calls as they've already been added in previous patches.
v2: Rebase to move all runtime pm specific changes to intel_runtime_pm.c file.
Modified as per review comments from Imre:
1] Change variable name 'dc5_allowed' to 'dc5_enabled' to correspond to relevant
functions.
2] Move the check dc5_enabled in skl_set_power_well() to disable DC5 into
gen9_disable_DC5 which is a more appropriate place.
3] Convert checks for 'pm.dc5_enabled' and 'pm.suspended' in skl_set_power_well()
to warnings. However, removing them for now as they'll be included in a future patch
asserting DC-state entry/exit criteria.
4] Enable DC5, only when CSR firmware is verified to be loaded. Create new structure
to track 'enabled' and 'deferred' status of DC5.
5] Ensure runtime PM reference is obtained, if CSR is not loaded, to avoid entering
runtime-suspend and release it when it's loaded.
6] Protect necessary CSR-related code with locks.
7] Move CSR-loading call to runtime PM initialization, as power domains needed to be
accessed during deferred DC5-enabling, are not initialized earlier.
v3: Rebase to latest.
Modified as per review comments from Imre:
1] Use blocking wait for CSR-loading to finish to enable DC5 for simplicity, instead of
deferring enabling DC5 until CSR is loaded.
2] Obtain runtime PM reference during CSR-loading initialization itself as deferred DC5-
enabling is removed and release it at the end of CSR-loading functionality.
3] Revert calling CSR-loading functionality to the beginning of i915 driver-load
functionality to avoid any delay in loading.
4] Define another variable to track whether CSR-loading failed and use it to avoid enabling
DC5 if it's true.
5] Define CSR-load-status accessor functions for use later.
v4:
1] Disable DC5 before enabling PG2 instead of after it.
2] DC5 was being mistaken enabled even when CSR-loading timed-out. Fix that.
3] Enable DC5-related functionality using a macro.
4] Remove dc5_enabled tracking variable and its use as it's not needed now.
v5:
1] Mark CSR failed to load where necessary in finish_csr_load function.
2] Use mutex-protected accessor function to check if CSR loaded instead of directly
accessing the variable.
3] Prefix csr_load_status_get/set function names with intel_.
v6: rebase to latest.
v7: Rebase on top of nightly (Damien)
v8: Squashed the patch from Imre - added csr helper pointers to simplify the code. (Imre)
v9: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)
v10: Added a enum for different csr states, suggested by Imre. (Animesh)
v11: Based on review comments from Imre, Damien and Daniel following changes done
- enum name chnaged to csr_state (singular form).
- FW_UNINITIALIZED used as zeroth element in enum csr_state.
- Prototype changed for helper function(set/get csr status), using enum csr_state instead of bool.
v12: Based on review comment from Imre, introduced bool fw_loaded local to finish_csr_load() which helps
calling once to set the csr status. The same flag used to fail RPM if find any issue during
firmware loading.
Issue: VIZ-2819
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Suketu Shah <suketu.j.shah@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-04-17 22:16:16 +08:00
|
|
|
struct drm_device *dev = dev_priv->dev;
|
2015-02-04 21:57:44 +08:00
|
|
|
uint32_t tmp, fuse_status;
|
|
|
|
uint32_t req_mask, state_mask;
|
2015-03-07 02:50:49 +08:00
|
|
|
bool is_enabled, enable_requested, check_fuse_status = false;
|
2015-02-04 21:57:44 +08:00
|
|
|
|
|
|
|
tmp = I915_READ(HSW_PWR_WELL_DRIVER);
|
|
|
|
fuse_status = I915_READ(SKL_FUSE_STATUS);
|
|
|
|
|
|
|
|
switch (power_well->data) {
|
|
|
|
case SKL_DISP_PW_1:
|
|
|
|
if (wait_for((I915_READ(SKL_FUSE_STATUS) &
|
|
|
|
SKL_FUSE_PG0_DIST_STATUS), 1)) {
|
|
|
|
DRM_ERROR("PG0 not enabled\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case SKL_DISP_PW_2:
|
|
|
|
if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
|
|
|
|
DRM_ERROR("PG1 in disabled state\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case SKL_DISP_PW_DDI_A_E:
|
|
|
|
case SKL_DISP_PW_DDI_B:
|
|
|
|
case SKL_DISP_PW_DDI_C:
|
|
|
|
case SKL_DISP_PW_DDI_D:
|
|
|
|
case SKL_DISP_PW_MISC_IO:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
WARN(1, "Unknown power well %lu\n", power_well->data);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
req_mask = SKL_POWER_WELL_REQ(power_well->data);
|
2015-03-07 02:50:49 +08:00
|
|
|
enable_requested = tmp & req_mask;
|
2015-02-04 21:57:44 +08:00
|
|
|
state_mask = SKL_POWER_WELL_STATE(power_well->data);
|
2015-03-07 02:50:49 +08:00
|
|
|
is_enabled = tmp & state_mask;
|
2015-02-04 21:57:44 +08:00
|
|
|
|
|
|
|
if (enable) {
|
2015-03-07 02:50:49 +08:00
|
|
|
if (!enable_requested) {
|
drm/i915/skl: Add DC5 Trigger Sequence
Add triggers as per expectations mentioned in gen9_enable_dc5
and gen9_disable_dc5 patch.
Also call POSTING_READ for every write to a register to ensure that
its written immediately.
v1: Remove POSTING_READ calls as they've already been added in previous patches.
v2: Rebase to move all runtime pm specific changes to intel_runtime_pm.c file.
Modified as per review comments from Imre:
1] Change variable name 'dc5_allowed' to 'dc5_enabled' to correspond to relevant
functions.
2] Move the check dc5_enabled in skl_set_power_well() to disable DC5 into
gen9_disable_DC5 which is a more appropriate place.
3] Convert checks for 'pm.dc5_enabled' and 'pm.suspended' in skl_set_power_well()
to warnings. However, removing them for now as they'll be included in a future patch
asserting DC-state entry/exit criteria.
4] Enable DC5, only when CSR firmware is verified to be loaded. Create new structure
to track 'enabled' and 'deferred' status of DC5.
5] Ensure runtime PM reference is obtained, if CSR is not loaded, to avoid entering
runtime-suspend and release it when it's loaded.
6] Protect necessary CSR-related code with locks.
7] Move CSR-loading call to runtime PM initialization, as power domains needed to be
accessed during deferred DC5-enabling, are not initialized earlier.
v3: Rebase to latest.
Modified as per review comments from Imre:
1] Use blocking wait for CSR-loading to finish to enable DC5 for simplicity, instead of
deferring enabling DC5 until CSR is loaded.
2] Obtain runtime PM reference during CSR-loading initialization itself as deferred DC5-
enabling is removed and release it at the end of CSR-loading functionality.
3] Revert calling CSR-loading functionality to the beginning of i915 driver-load
functionality to avoid any delay in loading.
4] Define another variable to track whether CSR-loading failed and use it to avoid enabling
DC5 if it's true.
5] Define CSR-load-status accessor functions for use later.
v4:
1] Disable DC5 before enabling PG2 instead of after it.
2] DC5 was being mistaken enabled even when CSR-loading timed-out. Fix that.
3] Enable DC5-related functionality using a macro.
4] Remove dc5_enabled tracking variable and its use as it's not needed now.
v5:
1] Mark CSR failed to load where necessary in finish_csr_load function.
2] Use mutex-protected accessor function to check if CSR loaded instead of directly
accessing the variable.
3] Prefix csr_load_status_get/set function names with intel_.
v6: rebase to latest.
v7: Rebase on top of nightly (Damien)
v8: Squashed the patch from Imre - added csr helper pointers to simplify the code. (Imre)
v9: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)
v10: Added a enum for different csr states, suggested by Imre. (Animesh)
v11: Based on review comments from Imre, Damien and Daniel following changes done
- enum name chnaged to csr_state (singular form).
- FW_UNINITIALIZED used as zeroth element in enum csr_state.
- Prototype changed for helper function(set/get csr status), using enum csr_state instead of bool.
v12: Based on review comment from Imre, introduced bool fw_loaded local to finish_csr_load() which helps
calling once to set the csr status. The same flag used to fail RPM if find any issue during
firmware loading.
Issue: VIZ-2819
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Suketu Shah <suketu.j.shah@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-04-17 22:16:16 +08:00
|
|
|
WARN((tmp & state_mask) &&
|
|
|
|
!I915_READ(HSW_PWR_WELL_BIOS),
|
|
|
|
"Invalid for power well status to be enabled, unless done by the BIOS, \
|
|
|
|
when request is to disable!\n");
|
2015-09-29 13:31:59 +08:00
|
|
|
if (power_well->data == SKL_DISP_PW_2) {
|
|
|
|
if (GEN9_ENABLE_DC5(dev))
|
|
|
|
gen9_disable_dc5(dev_priv);
|
2015-04-16 16:52:11 +08:00
|
|
|
if (SKL_ENABLE_DC6(dev)) {
|
|
|
|
/*
|
|
|
|
* DDI buffer programming unnecessary during driver-load/resume
|
|
|
|
* as it's already done during modeset initialization then.
|
|
|
|
* It's also invalid here as encoder list is still uninitialized.
|
|
|
|
*/
|
|
|
|
if (!dev_priv->power_domains.initializing)
|
|
|
|
intel_prepare_ddi(dev);
|
|
|
|
}
|
|
|
|
}
|
2015-02-04 21:57:44 +08:00
|
|
|
I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
|
|
|
|
}
|
|
|
|
|
2015-03-07 02:50:49 +08:00
|
|
|
if (!is_enabled) {
|
2015-03-07 02:50:50 +08:00
|
|
|
DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
|
2015-02-04 21:57:44 +08:00
|
|
|
if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
|
|
|
|
state_mask), 1))
|
|
|
|
DRM_ERROR("%s enable timeout\n",
|
|
|
|
power_well->name);
|
|
|
|
check_fuse_status = true;
|
|
|
|
}
|
|
|
|
} else {
|
2015-03-07 02:50:49 +08:00
|
|
|
if (enable_requested) {
|
2015-11-05 01:24:15 +08:00
|
|
|
I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
|
|
|
|
POSTING_READ(HSW_PWR_WELL_DRIVER);
|
|
|
|
DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
|
drm/i915/skl: Add DC5 Trigger Sequence
Add triggers as per expectations mentioned in gen9_enable_dc5
and gen9_disable_dc5 patch.
Also call POSTING_READ for every write to a register to ensure that
its written immediately.
v1: Remove POSTING_READ calls as they've already been added in previous patches.
v2: Rebase to move all runtime pm specific changes to intel_runtime_pm.c file.
Modified as per review comments from Imre:
1] Change variable name 'dc5_allowed' to 'dc5_enabled' to correspond to relevant
functions.
2] Move the check dc5_enabled in skl_set_power_well() to disable DC5 into
gen9_disable_DC5 which is a more appropriate place.
3] Convert checks for 'pm.dc5_enabled' and 'pm.suspended' in skl_set_power_well()
to warnings. However, removing them for now as they'll be included in a future patch
asserting DC-state entry/exit criteria.
4] Enable DC5, only when CSR firmware is verified to be loaded. Create new structure
to track 'enabled' and 'deferred' status of DC5.
5] Ensure runtime PM reference is obtained, if CSR is not loaded, to avoid entering
runtime-suspend and release it when it's loaded.
6] Protect necessary CSR-related code with locks.
7] Move CSR-loading call to runtime PM initialization, as power domains needed to be
accessed during deferred DC5-enabling, are not initialized earlier.
v3: Rebase to latest.
Modified as per review comments from Imre:
1] Use blocking wait for CSR-loading to finish to enable DC5 for simplicity, instead of
deferring enabling DC5 until CSR is loaded.
2] Obtain runtime PM reference during CSR-loading initialization itself as deferred DC5-
enabling is removed and release it at the end of CSR-loading functionality.
3] Revert calling CSR-loading functionality to the beginning of i915 driver-load
functionality to avoid any delay in loading.
4] Define another variable to track whether CSR-loading failed and use it to avoid enabling
DC5 if it's true.
5] Define CSR-load-status accessor functions for use later.
v4:
1] Disable DC5 before enabling PG2 instead of after it.
2] DC5 was being mistaken enabled even when CSR-loading timed-out. Fix that.
3] Enable DC5-related functionality using a macro.
4] Remove dc5_enabled tracking variable and its use as it's not needed now.
v5:
1] Mark CSR failed to load where necessary in finish_csr_load function.
2] Use mutex-protected accessor function to check if CSR loaded instead of directly
accessing the variable.
3] Prefix csr_load_status_get/set function names with intel_.
v6: rebase to latest.
v7: Rebase on top of nightly (Damien)
v8: Squashed the patch from Imre - added csr helper pointers to simplify the code. (Imre)
v9: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)
v10: Added a enum for different csr states, suggested by Imre. (Animesh)
v11: Based on review comments from Imre, Damien and Daniel following changes done
- enum name chnaged to csr_state (singular form).
- FW_UNINITIALIZED used as zeroth element in enum csr_state.
- Prototype changed for helper function(set/get csr status), using enum csr_state instead of bool.
v12: Based on review comment from Imre, introduced bool fw_loaded local to finish_csr_load() which helps
calling once to set the csr status. The same flag used to fail RPM if find any issue during
firmware loading.
Issue: VIZ-2819
Signed-off-by: A.Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Suketu Shah <suketu.j.shah@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-04-17 22:16:16 +08:00
|
|
|
|
2015-09-29 13:31:59 +08:00
|
|
|
if (GEN9_ENABLE_DC5(dev) &&
|
2015-11-12 23:10:37 +08:00
|
|
|
power_well->data == SKL_DISP_PW_2)
|
2015-09-29 13:31:59 +08:00
|
|
|
gen9_enable_dc5(dev_priv);
|
2015-02-04 21:57:44 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (check_fuse_status) {
|
|
|
|
if (power_well->data == SKL_DISP_PW_1) {
|
|
|
|
if (wait_for((I915_READ(SKL_FUSE_STATUS) &
|
|
|
|
SKL_FUSE_PG1_DIST_STATUS), 1))
|
|
|
|
DRM_ERROR("PG1 distributing status timeout\n");
|
|
|
|
} else if (power_well->data == SKL_DISP_PW_2) {
|
|
|
|
if (wait_for((I915_READ(SKL_FUSE_STATUS) &
|
|
|
|
SKL_FUSE_PG2_DIST_STATUS), 1))
|
|
|
|
DRM_ERROR("PG2 distributing status timeout\n");
|
|
|
|
}
|
|
|
|
}
|
2015-03-07 02:50:51 +08:00
|
|
|
|
|
|
|
if (enable && !is_enabled)
|
|
|
|
skl_power_well_post_enable(dev_priv, power_well);
|
2015-02-04 21:57:44 +08:00
|
|
|
}
|
|
|
|
|
2014-09-30 16:56:38 +08:00
|
|
|
static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well)
|
|
|
|
{
|
|
|
|
hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We're taking over the BIOS, so clear any requests made by it since
|
|
|
|
* the driver is in charge now.
|
|
|
|
*/
|
|
|
|
if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
|
|
|
|
I915_WRITE(HSW_PWR_WELL_BIOS, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well)
|
|
|
|
{
|
|
|
|
hsw_set_power_well(dev_priv, power_well, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well)
|
|
|
|
{
|
|
|
|
hsw_set_power_well(dev_priv, power_well, false);
|
|
|
|
}
|
|
|
|
|
2015-02-04 21:57:44 +08:00
|
|
|
static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well)
|
|
|
|
{
|
|
|
|
uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
|
|
|
|
SKL_POWER_WELL_STATE(power_well->data);
|
|
|
|
|
|
|
|
return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well)
|
|
|
|
{
|
|
|
|
skl_set_power_well(dev_priv, power_well, power_well->count > 0);
|
|
|
|
|
|
|
|
/* Clear any request made by BIOS as driver is taking over */
|
|
|
|
I915_WRITE(HSW_PWR_WELL_BIOS, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void skl_power_well_enable(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well)
|
|
|
|
{
|
|
|
|
skl_set_power_well(dev_priv, power_well, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void skl_power_well_disable(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well)
|
|
|
|
{
|
|
|
|
skl_set_power_well(dev_priv, power_well, false);
|
|
|
|
}
|
|
|
|
|
2014-09-30 16:56:38 +08:00
|
|
|
static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well)
|
|
|
|
{
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void vlv_set_power_well(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well, bool enable)
|
|
|
|
{
|
|
|
|
enum punit_power_well power_well_id = power_well->data;
|
|
|
|
u32 mask;
|
|
|
|
u32 state;
|
|
|
|
u32 ctrl;
|
|
|
|
|
|
|
|
mask = PUNIT_PWRGT_MASK(power_well_id);
|
|
|
|
state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
|
|
|
|
PUNIT_PWRGT_PWR_GATE(power_well_id);
|
|
|
|
|
|
|
|
mutex_lock(&dev_priv->rps.hw_lock);
|
|
|
|
|
|
|
|
#define COND \
|
|
|
|
((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
|
|
|
|
|
|
|
|
if (COND)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
|
|
|
|
ctrl &= ~mask;
|
|
|
|
ctrl |= state;
|
|
|
|
vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
|
|
|
|
|
|
|
|
if (wait_for(COND, 100))
|
2015-05-10 00:00:23 +08:00
|
|
|
DRM_ERROR("timeout setting power well state %08x (%08x)\n",
|
2014-09-30 16:56:38 +08:00
|
|
|
state,
|
|
|
|
vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
|
|
|
|
|
|
|
|
#undef COND
|
|
|
|
|
|
|
|
out:
|
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well)
|
|
|
|
{
|
|
|
|
vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well)
|
|
|
|
{
|
|
|
|
vlv_set_power_well(dev_priv, power_well, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well)
|
|
|
|
{
|
|
|
|
vlv_set_power_well(dev_priv, power_well, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well)
|
|
|
|
{
|
|
|
|
int power_well_id = power_well->data;
|
|
|
|
bool enabled = false;
|
|
|
|
u32 mask;
|
|
|
|
u32 state;
|
|
|
|
u32 ctrl;
|
|
|
|
|
|
|
|
mask = PUNIT_PWRGT_MASK(power_well_id);
|
|
|
|
ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
|
|
|
|
|
|
|
|
mutex_lock(&dev_priv->rps.hw_lock);
|
|
|
|
|
|
|
|
state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
|
|
|
|
/*
|
|
|
|
* We only ever set the power-on and power-gate states, anything
|
|
|
|
* else is unexpected.
|
|
|
|
*/
|
|
|
|
WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
|
|
|
|
state != PUNIT_PWRGT_PWR_GATE(power_well_id));
|
|
|
|
if (state == ctrl)
|
|
|
|
enabled = true;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* A transient state at this point would mean some unexpected party
|
|
|
|
* is poking at the power controls too.
|
|
|
|
*/
|
|
|
|
ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
|
|
|
|
WARN_ON(ctrl != state);
|
|
|
|
|
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
|
|
|
|
|
|
|
return enabled;
|
|
|
|
}
|
|
|
|
|
2015-06-29 20:25:51 +08:00
|
|
|
static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
|
2014-09-30 16:56:38 +08:00
|
|
|
{
|
2015-06-29 20:25:53 +08:00
|
|
|
enum pipe pipe;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable the CRI clock source so we can get at the
|
|
|
|
* display and the reference clock for VGA
|
|
|
|
* hotplug / manual detection. Supposedly DSI also
|
|
|
|
* needs the ref clock up and running.
|
|
|
|
*
|
|
|
|
* CHV DPLL B/C have some issues if VGA mode is enabled.
|
|
|
|
*/
|
|
|
|
for_each_pipe(dev_priv->dev, pipe) {
|
|
|
|
u32 val = I915_READ(DPLL(pipe));
|
|
|
|
|
|
|
|
val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
|
|
|
|
if (pipe != PIPE_A)
|
|
|
|
val |= DPLL_INTEGRATED_CRI_CLK_VLV;
|
|
|
|
|
|
|
|
I915_WRITE(DPLL(pipe), val);
|
|
|
|
}
|
2014-09-30 16:56:38 +08:00
|
|
|
|
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
|
|
|
valleyview_enable_display_irqs(dev_priv);
|
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* During driver initialization/resume we can avoid restoring the
|
|
|
|
* part of the HW/SW state that will be inited anyway explicitly.
|
|
|
|
*/
|
|
|
|
if (dev_priv->power_domains.initializing)
|
|
|
|
return;
|
|
|
|
|
2014-09-30 16:56:44 +08:00
|
|
|
intel_hpd_init(dev_priv);
|
2014-09-30 16:56:38 +08:00
|
|
|
|
|
|
|
i915_redisable_vga_power_on(dev_priv->dev);
|
|
|
|
}
|
|
|
|
|
2015-06-29 20:25:51 +08:00
|
|
|
static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
spin_lock_irq(&dev_priv->irq_lock);
|
|
|
|
valleyview_disable_display_irqs(dev_priv);
|
|
|
|
spin_unlock_irq(&dev_priv->irq_lock);
|
|
|
|
|
|
|
|
vlv_power_sequencer_reset(dev_priv);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well)
|
|
|
|
{
|
|
|
|
WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
|
|
|
|
|
|
|
|
vlv_set_power_well(dev_priv, power_well, true);
|
|
|
|
|
|
|
|
vlv_display_power_well_init(dev_priv);
|
|
|
|
}
|
|
|
|
|
2014-09-30 16:56:38 +08:00
|
|
|
static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well)
|
|
|
|
{
|
|
|
|
WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
|
|
|
|
|
2015-06-29 20:25:51 +08:00
|
|
|
vlv_display_power_well_deinit(dev_priv);
|
2014-09-30 16:56:38 +08:00
|
|
|
|
|
|
|
vlv_set_power_well(dev_priv, power_well, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well)
|
|
|
|
{
|
|
|
|
WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
|
|
|
|
|
2015-06-29 20:25:53 +08:00
|
|
|
/* since ref/cri clock was enabled */
|
2014-09-30 16:56:38 +08:00
|
|
|
udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
|
|
|
|
|
|
|
|
vlv_set_power_well(dev_priv, power_well, true);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
|
|
|
|
* 6. De-assert cmn_reset/side_reset. Same as VLV X0.
|
|
|
|
* a. GUnit 0x2110 bit[0] set to 1 (def 0)
|
|
|
|
* b. The other bits such as sfr settings / modesel may all
|
|
|
|
* be set to 0.
|
|
|
|
*
|
|
|
|
* This should only be done on init and resume from S3 with
|
|
|
|
* both PLLs disabled, or we risk losing DPIO and PLL
|
|
|
|
* synchronization.
|
|
|
|
*/
|
|
|
|
I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well)
|
|
|
|
{
|
|
|
|
enum pipe pipe;
|
|
|
|
|
|
|
|
WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
|
|
|
|
|
|
|
|
for_each_pipe(dev_priv, pipe)
|
|
|
|
assert_pll_disabled(dev_priv, pipe);
|
|
|
|
|
|
|
|
/* Assert common reset */
|
|
|
|
I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
|
|
|
|
|
|
|
|
vlv_set_power_well(dev_priv, power_well, false);
|
|
|
|
}
|
|
|
|
|
2015-07-09 04:46:01 +08:00
|
|
|
#define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
|
|
|
|
|
|
|
|
static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
|
|
|
|
int power_well_id)
|
|
|
|
{
|
|
|
|
struct i915_power_domains *power_domains = &dev_priv->power_domains;
|
|
|
|
int i;
|
|
|
|
|
2015-11-05 01:24:11 +08:00
|
|
|
for (i = 0; i < power_domains->power_well_count; i++) {
|
|
|
|
struct i915_power_well *power_well;
|
|
|
|
|
|
|
|
power_well = &power_domains->power_wells[i];
|
2015-07-09 04:46:01 +08:00
|
|
|
if (power_well->data == power_well_id)
|
|
|
|
return power_well;
|
|
|
|
}
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
#define BITS_SET(val, bits) (((val) & (bits)) == (bits))
|
|
|
|
|
|
|
|
static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct i915_power_well *cmn_bc =
|
|
|
|
lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
|
|
|
|
struct i915_power_well *cmn_d =
|
|
|
|
lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
|
|
|
|
u32 phy_control = dev_priv->chv_phy_control;
|
|
|
|
u32 phy_status = 0;
|
2015-09-08 23:05:45 +08:00
|
|
|
u32 phy_status_mask = 0xffffffff;
|
2015-07-09 04:46:01 +08:00
|
|
|
u32 tmp;
|
|
|
|
|
2015-09-08 23:05:45 +08:00
|
|
|
/*
|
|
|
|
* The BIOS can leave the PHY is some weird state
|
|
|
|
* where it doesn't fully power down some parts.
|
|
|
|
* Disable the asserts until the PHY has been fully
|
|
|
|
* reset (ie. the power well has been disabled at
|
|
|
|
* least once).
|
|
|
|
*/
|
|
|
|
if (!dev_priv->chv_phy_assert[DPIO_PHY0])
|
|
|
|
phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
|
|
|
|
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
|
|
|
|
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
|
|
|
|
PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
|
|
|
|
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
|
|
|
|
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
|
|
|
|
|
|
|
|
if (!dev_priv->chv_phy_assert[DPIO_PHY1])
|
|
|
|
phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
|
|
|
|
PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
|
|
|
|
PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
|
|
|
|
|
2015-07-09 04:46:01 +08:00
|
|
|
if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
|
|
|
|
phy_status |= PHY_POWERGOOD(DPIO_PHY0);
|
|
|
|
|
|
|
|
/* this assumes override is only used to enable lanes */
|
|
|
|
if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
|
|
|
|
phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
|
|
|
|
|
|
|
|
if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
|
|
|
|
phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
|
|
|
|
|
|
|
|
/* CL1 is on whenever anything is on in either channel */
|
|
|
|
if (BITS_SET(phy_control,
|
|
|
|
PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
|
|
|
|
PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
|
|
|
|
phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The DPLLB check accounts for the pipe B + port A usage
|
|
|
|
* with CL2 powered up but all the lanes in the second channel
|
|
|
|
* powered down.
|
|
|
|
*/
|
|
|
|
if (BITS_SET(phy_control,
|
|
|
|
PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
|
|
|
|
(I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
|
|
|
|
phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
|
|
|
|
|
|
|
|
if (BITS_SET(phy_control,
|
|
|
|
PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
|
|
|
|
phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
|
|
|
|
if (BITS_SET(phy_control,
|
|
|
|
PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
|
|
|
|
phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
|
|
|
|
|
|
|
|
if (BITS_SET(phy_control,
|
|
|
|
PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
|
|
|
|
phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
|
|
|
|
if (BITS_SET(phy_control,
|
|
|
|
PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
|
|
|
|
phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
|
|
|
|
phy_status |= PHY_POWERGOOD(DPIO_PHY1);
|
|
|
|
|
|
|
|
/* this assumes override is only used to enable lanes */
|
|
|
|
if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
|
|
|
|
phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
|
|
|
|
|
|
|
|
if (BITS_SET(phy_control,
|
|
|
|
PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
|
|
|
|
phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
|
|
|
|
|
|
|
|
if (BITS_SET(phy_control,
|
|
|
|
PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
|
|
|
|
phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
|
|
|
|
if (BITS_SET(phy_control,
|
|
|
|
PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
|
|
|
|
phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
|
|
|
|
}
|
|
|
|
|
2015-09-08 23:05:45 +08:00
|
|
|
phy_status &= phy_status_mask;
|
|
|
|
|
2015-07-09 04:46:01 +08:00
|
|
|
/*
|
|
|
|
* The PHY may be busy with some initial calibration and whatnot,
|
|
|
|
* so the power state can take a while to actually change.
|
|
|
|
*/
|
2015-09-08 23:05:45 +08:00
|
|
|
if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))
|
2015-07-09 04:46:01 +08:00
|
|
|
WARN(phy_status != tmp,
|
|
|
|
"Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
|
|
|
|
tmp, phy_status, dev_priv->chv_phy_control);
|
|
|
|
}
|
|
|
|
|
|
|
|
#undef BITS_SET
|
|
|
|
|
2014-09-30 16:56:38 +08:00
|
|
|
static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well)
|
|
|
|
{
|
|
|
|
enum dpio_phy phy;
|
2015-07-09 04:45:54 +08:00
|
|
|
enum pipe pipe;
|
|
|
|
uint32_t tmp;
|
2014-09-30 16:56:38 +08:00
|
|
|
|
|
|
|
WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
|
|
|
|
power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
|
|
|
|
|
2015-07-09 04:45:54 +08:00
|
|
|
if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
|
|
|
|
pipe = PIPE_A;
|
2014-09-30 16:56:38 +08:00
|
|
|
phy = DPIO_PHY0;
|
2015-07-09 04:45:54 +08:00
|
|
|
} else {
|
|
|
|
pipe = PIPE_C;
|
2014-09-30 16:56:38 +08:00
|
|
|
phy = DPIO_PHY1;
|
2015-07-09 04:45:54 +08:00
|
|
|
}
|
2015-06-29 20:25:53 +08:00
|
|
|
|
|
|
|
/* since ref/cri clock was enabled */
|
2014-09-30 16:56:38 +08:00
|
|
|
udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
|
|
|
|
vlv_set_power_well(dev_priv, power_well, true);
|
|
|
|
|
|
|
|
/* Poll for phypwrgood signal */
|
|
|
|
if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
|
|
|
|
DRM_ERROR("Display PHY %d is not power up\n", phy);
|
|
|
|
|
2015-07-09 04:45:54 +08:00
|
|
|
mutex_lock(&dev_priv->sb_lock);
|
|
|
|
|
|
|
|
/* Enable dynamic power down */
|
|
|
|
tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
|
2015-07-09 04:45:57 +08:00
|
|
|
tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
|
|
|
|
DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
|
2015-07-09 04:45:54 +08:00
|
|
|
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
|
|
|
|
|
|
|
|
if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
|
|
|
|
tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
|
|
|
|
tmp |= DPIO_DYNPWRDOWNEN_CH1;
|
|
|
|
vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
|
2015-07-09 04:45:58 +08:00
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* Force the non-existing CL2 off. BXT does this
|
|
|
|
* too, so maybe it saves some power even though
|
|
|
|
* CL2 doesn't exist?
|
|
|
|
*/
|
|
|
|
tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
|
|
|
|
tmp |= DPIO_CL2_LDOFUSE_PWRENB;
|
|
|
|
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
|
2015-07-09 04:45:54 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
mutex_unlock(&dev_priv->sb_lock);
|
|
|
|
|
2015-04-10 23:21:28 +08:00
|
|
|
dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
|
|
|
|
I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
|
2015-07-09 04:45:54 +08:00
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
|
|
|
|
phy, dev_priv->chv_phy_control);
|
2015-07-09 04:46:01 +08:00
|
|
|
|
|
|
|
assert_chv_phy_status(dev_priv);
|
2014-09-30 16:56:38 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well)
|
|
|
|
{
|
|
|
|
enum dpio_phy phy;
|
|
|
|
|
|
|
|
WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
|
|
|
|
power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
|
|
|
|
|
|
|
|
if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
|
|
|
|
phy = DPIO_PHY0;
|
|
|
|
assert_pll_disabled(dev_priv, PIPE_A);
|
|
|
|
assert_pll_disabled(dev_priv, PIPE_B);
|
|
|
|
} else {
|
|
|
|
phy = DPIO_PHY1;
|
|
|
|
assert_pll_disabled(dev_priv, PIPE_C);
|
|
|
|
}
|
|
|
|
|
2015-04-10 23:21:28 +08:00
|
|
|
dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
|
|
|
|
I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
|
2014-09-30 16:56:38 +08:00
|
|
|
|
|
|
|
vlv_set_power_well(dev_priv, power_well, false);
|
2015-07-09 04:45:54 +08:00
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
|
|
|
|
phy, dev_priv->chv_phy_control);
|
2015-07-09 04:46:01 +08:00
|
|
|
|
2015-09-08 23:05:45 +08:00
|
|
|
/* PHY is fully reset now, so we can enable the PHY state asserts */
|
|
|
|
dev_priv->chv_phy_assert[phy] = true;
|
|
|
|
|
2015-07-09 04:46:01 +08:00
|
|
|
assert_chv_phy_status(dev_priv);
|
2015-07-09 04:45:54 +08:00
|
|
|
}
|
|
|
|
|
2015-07-09 04:46:00 +08:00
|
|
|
static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
|
|
|
|
enum dpio_channel ch, bool override, unsigned int mask)
|
|
|
|
{
|
|
|
|
enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
|
|
|
|
u32 reg, val, expected, actual;
|
|
|
|
|
2015-09-08 23:05:45 +08:00
|
|
|
/*
|
|
|
|
* The BIOS can leave the PHY is some weird state
|
|
|
|
* where it doesn't fully power down some parts.
|
|
|
|
* Disable the asserts until the PHY has been fully
|
|
|
|
* reset (ie. the power well has been disabled at
|
|
|
|
* least once).
|
|
|
|
*/
|
|
|
|
if (!dev_priv->chv_phy_assert[phy])
|
|
|
|
return;
|
|
|
|
|
2015-07-09 04:46:00 +08:00
|
|
|
if (ch == DPIO_CH0)
|
|
|
|
reg = _CHV_CMN_DW0_CH0;
|
|
|
|
else
|
|
|
|
reg = _CHV_CMN_DW6_CH1;
|
|
|
|
|
|
|
|
mutex_lock(&dev_priv->sb_lock);
|
|
|
|
val = vlv_dpio_read(dev_priv, pipe, reg);
|
|
|
|
mutex_unlock(&dev_priv->sb_lock);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This assumes !override is only used when the port is disabled.
|
|
|
|
* All lanes should power down even without the override when
|
|
|
|
* the port is disabled.
|
|
|
|
*/
|
|
|
|
if (!override || mask == 0xf) {
|
|
|
|
expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
|
|
|
|
/*
|
|
|
|
* If CH1 common lane is not active anymore
|
|
|
|
* (eg. for pipe B DPLL) the entire channel will
|
|
|
|
* shut down, which causes the common lane registers
|
|
|
|
* to read as 0. That means we can't actually check
|
|
|
|
* the lane power down status bits, but as the entire
|
|
|
|
* register reads as 0 it's a good indication that the
|
|
|
|
* channel is indeed entirely powered down.
|
|
|
|
*/
|
|
|
|
if (ch == DPIO_CH1 && val == 0)
|
|
|
|
expected = 0;
|
|
|
|
} else if (mask != 0x0) {
|
|
|
|
expected = DPIO_ANYDL_POWERDOWN;
|
|
|
|
} else {
|
|
|
|
expected = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ch == DPIO_CH0)
|
|
|
|
actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
|
|
|
|
else
|
|
|
|
actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
|
|
|
|
actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
|
|
|
|
|
|
|
|
WARN(actual != expected,
|
|
|
|
"Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
|
|
|
|
!!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
|
|
|
|
!!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
|
|
|
|
reg, val);
|
|
|
|
}
|
|
|
|
|
drm/i915: Trick CL2 into life on CHV when using pipe B with port B
Normmally the common lane in a PHY channel gets powered up when some
of the data lanes get powered up. But when we're driving port B with
pipe B we don't want to enabled any of the data lanes, and just want
the DPLL in the common lane to be active.
To make that happens we have to temporarily enable some data lanes
after which we can access the DPLL registers in the common lane. Once
the pipe is up and running we can drop the power override on the data
lanes allowing them to shut down. From this point forward the common
lane will in fact stay powered on until the data lanes in the other
channel get powered down.
Ville's extended explanation from the review thread:
On Wed, Aug 19, 2015 at 07:47:41AM +0530, Deepak wrote:
> One Q, why only for port B? Port C is also in same common lane right?
Port B is in the first PHY channel which also houses CL1. CL1 always
powers up whenever any lanes in either PHY channel are powered up.
CL2 only powers up if lanes in the second channel (ie. the one with
port C) powers up.
So in this scenario (pipe B->port B) we want the DPLL from CL2, but
ideally we only want to power up the lanes for port B. Powering up
port B lanes will only power up CL1, but as we need CL2 instead we
need to, temporarily, power up some lanes in port C as well.
Crossing the streams the other way (pipe A->port C) is not a problem
since CL1 powers up whenever anything else powers up. So powering up
some port C lanes is enough on its own to make the CL1 DPLL
operational, even though CL1 and the lanes live in separate channels.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
[danvet: Amend commit message with extended explanation.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-09 04:45:55 +08:00
|
|
|
bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
|
|
|
|
enum dpio_channel ch, bool override)
|
|
|
|
{
|
|
|
|
struct i915_power_domains *power_domains = &dev_priv->power_domains;
|
|
|
|
bool was_override;
|
|
|
|
|
|
|
|
mutex_lock(&power_domains->lock);
|
|
|
|
|
|
|
|
was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
|
|
|
|
|
|
|
|
if (override == was_override)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
if (override)
|
|
|
|
dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
|
|
|
|
else
|
|
|
|
dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
|
|
|
|
|
|
|
|
I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
|
|
|
|
phy, ch, dev_priv->chv_phy_control);
|
|
|
|
|
2015-07-09 04:46:01 +08:00
|
|
|
assert_chv_phy_status(dev_priv);
|
|
|
|
|
drm/i915: Trick CL2 into life on CHV when using pipe B with port B
Normmally the common lane in a PHY channel gets powered up when some
of the data lanes get powered up. But when we're driving port B with
pipe B we don't want to enabled any of the data lanes, and just want
the DPLL in the common lane to be active.
To make that happens we have to temporarily enable some data lanes
after which we can access the DPLL registers in the common lane. Once
the pipe is up and running we can drop the power override on the data
lanes allowing them to shut down. From this point forward the common
lane will in fact stay powered on until the data lanes in the other
channel get powered down.
Ville's extended explanation from the review thread:
On Wed, Aug 19, 2015 at 07:47:41AM +0530, Deepak wrote:
> One Q, why only for port B? Port C is also in same common lane right?
Port B is in the first PHY channel which also houses CL1. CL1 always
powers up whenever any lanes in either PHY channel are powered up.
CL2 only powers up if lanes in the second channel (ie. the one with
port C) powers up.
So in this scenario (pipe B->port B) we want the DPLL from CL2, but
ideally we only want to power up the lanes for port B. Powering up
port B lanes will only power up CL1, but as we need CL2 instead we
need to, temporarily, power up some lanes in port C as well.
Crossing the streams the other way (pipe A->port C) is not a problem
since CL1 powers up whenever anything else powers up. So powering up
some port C lanes is enough on its own to make the CL1 DPLL
operational, even though CL1 and the lanes live in separate channels.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Deepak S <deepak.s@linux.intel.com>
[danvet: Amend commit message with extended explanation.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-07-09 04:45:55 +08:00
|
|
|
out:
|
|
|
|
mutex_unlock(&power_domains->lock);
|
|
|
|
|
|
|
|
return was_override;
|
|
|
|
}
|
|
|
|
|
2015-07-09 04:45:54 +08:00
|
|
|
void chv_phy_powergate_lanes(struct intel_encoder *encoder,
|
|
|
|
bool override, unsigned int mask)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
|
|
|
|
struct i915_power_domains *power_domains = &dev_priv->power_domains;
|
|
|
|
enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
|
|
|
|
enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
|
|
|
|
|
|
|
|
mutex_lock(&power_domains->lock);
|
|
|
|
|
|
|
|
dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
|
|
|
|
dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
|
|
|
|
|
|
|
|
if (override)
|
|
|
|
dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
|
|
|
|
else
|
|
|
|
dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
|
|
|
|
|
|
|
|
I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
|
|
|
|
phy, ch, mask, dev_priv->chv_phy_control);
|
|
|
|
|
2015-07-09 04:46:01 +08:00
|
|
|
assert_chv_phy_status(dev_priv);
|
|
|
|
|
2015-07-09 04:46:00 +08:00
|
|
|
assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
|
|
|
|
|
2015-07-09 04:45:54 +08:00
|
|
|
mutex_unlock(&power_domains->lock);
|
2014-09-30 16:56:38 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well)
|
|
|
|
{
|
|
|
|
enum pipe pipe = power_well->data;
|
|
|
|
bool enabled;
|
|
|
|
u32 state, ctrl;
|
|
|
|
|
|
|
|
mutex_lock(&dev_priv->rps.hw_lock);
|
|
|
|
|
|
|
|
state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
|
|
|
|
/*
|
|
|
|
* We only ever set the power-on and power-gate states, anything
|
|
|
|
* else is unexpected.
|
|
|
|
*/
|
|
|
|
WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
|
|
|
|
enabled = state == DP_SSS_PWR_ON(pipe);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* A transient state at this point would mean some unexpected party
|
|
|
|
* is poking at the power controls too.
|
|
|
|
*/
|
|
|
|
ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
|
|
|
|
WARN_ON(ctrl << 16 != state);
|
|
|
|
|
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
|
|
|
|
|
|
|
return enabled;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well,
|
|
|
|
bool enable)
|
|
|
|
{
|
|
|
|
enum pipe pipe = power_well->data;
|
|
|
|
u32 state;
|
|
|
|
u32 ctrl;
|
|
|
|
|
|
|
|
state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
|
|
|
|
|
|
|
|
mutex_lock(&dev_priv->rps.hw_lock);
|
|
|
|
|
|
|
|
#define COND \
|
|
|
|
((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
|
|
|
|
|
|
|
|
if (COND)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
|
|
|
|
ctrl &= ~DP_SSC_MASK(pipe);
|
|
|
|
ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
|
|
|
|
vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
|
|
|
|
|
|
|
|
if (wait_for(COND, 100))
|
2015-05-10 00:00:23 +08:00
|
|
|
DRM_ERROR("timeout setting power well state %08x (%08x)\n",
|
2014-09-30 16:56:38 +08:00
|
|
|
state,
|
|
|
|
vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
|
|
|
|
|
|
|
|
#undef COND
|
|
|
|
|
|
|
|
out:
|
|
|
|
mutex_unlock(&dev_priv->rps.hw_lock);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well)
|
|
|
|
{
|
2015-06-29 20:25:50 +08:00
|
|
|
WARN_ON_ONCE(power_well->data != PIPE_A);
|
|
|
|
|
2014-09-30 16:56:38 +08:00
|
|
|
chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well)
|
|
|
|
{
|
2015-06-29 20:25:50 +08:00
|
|
|
WARN_ON_ONCE(power_well->data != PIPE_A);
|
2014-09-30 16:56:38 +08:00
|
|
|
|
|
|
|
chv_set_pipe_power_well(dev_priv, power_well, true);
|
2014-10-31 01:43:03 +08:00
|
|
|
|
2015-06-29 20:25:51 +08:00
|
|
|
vlv_display_power_well_init(dev_priv);
|
2014-09-30 16:56:38 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
|
|
|
|
struct i915_power_well *power_well)
|
|
|
|
{
|
2015-06-29 20:25:50 +08:00
|
|
|
WARN_ON_ONCE(power_well->data != PIPE_A);
|
|
|
|
|
2015-06-29 20:25:51 +08:00
|
|
|
vlv_display_power_well_deinit(dev_priv);
|
2014-10-31 01:43:03 +08:00
|
|
|
|
2014-09-30 16:56:38 +08:00
|
|
|
chv_set_pipe_power_well(dev_priv, power_well, false);
|
|
|
|
}
|
|
|
|
|
2014-09-30 16:56:42 +08:00
|
|
|
/**
|
|
|
|
* intel_display_power_get - grab a power domain reference
|
|
|
|
* @dev_priv: i915 device instance
|
|
|
|
* @domain: power domain to reference
|
|
|
|
*
|
|
|
|
* This function grabs a power domain reference for @domain and ensures that the
|
|
|
|
* power domain and all its parents are powered up. Therefore users should only
|
|
|
|
* grab a reference to the innermost power domain they need.
|
|
|
|
*
|
|
|
|
* Any power domain reference obtained by this function must have a symmetric
|
|
|
|
* call to intel_display_power_put() to release the reference again.
|
|
|
|
*/
|
2014-09-30 16:56:38 +08:00
|
|
|
void intel_display_power_get(struct drm_i915_private *dev_priv,
|
|
|
|
enum intel_display_power_domain domain)
|
|
|
|
{
|
|
|
|
struct i915_power_domains *power_domains;
|
|
|
|
struct i915_power_well *power_well;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
intel_runtime_pm_get(dev_priv);
|
|
|
|
|
|
|
|
power_domains = &dev_priv->power_domains;
|
|
|
|
|
|
|
|
mutex_lock(&power_domains->lock);
|
|
|
|
|
|
|
|
for_each_power_well(i, power_well, BIT(domain), power_domains) {
|
2015-07-31 05:20:26 +08:00
|
|
|
if (!power_well->count++)
|
|
|
|
intel_power_well_enable(dev_priv, power_well);
|
2014-09-30 16:56:38 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
power_domains->domain_use_count[domain]++;
|
|
|
|
|
|
|
|
mutex_unlock(&power_domains->lock);
|
|
|
|
}
|
|
|
|
|
2014-09-30 16:56:42 +08:00
|
|
|
/**
|
|
|
|
* intel_display_power_put - release a power domain reference
|
|
|
|
* @dev_priv: i915 device instance
|
|
|
|
* @domain: power domain to reference
|
|
|
|
*
|
|
|
|
* This function drops the power domain reference obtained by
|
|
|
|
* intel_display_power_get() and might power down the corresponding hardware
|
|
|
|
* block right away if this is the last reference.
|
|
|
|
*/
|
2014-09-30 16:56:38 +08:00
|
|
|
void intel_display_power_put(struct drm_i915_private *dev_priv,
|
|
|
|
enum intel_display_power_domain domain)
|
|
|
|
{
|
|
|
|
struct i915_power_domains *power_domains;
|
|
|
|
struct i915_power_well *power_well;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
power_domains = &dev_priv->power_domains;
|
|
|
|
|
|
|
|
mutex_lock(&power_domains->lock);
|
|
|
|
|
|
|
|
WARN_ON(!power_domains->domain_use_count[domain]);
|
|
|
|
power_domains->domain_use_count[domain]--;
|
|
|
|
|
|
|
|
for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
|
|
|
|
WARN_ON(!power_well->count);
|
|
|
|
|
2015-11-17 23:44:23 +08:00
|
|
|
if (!--power_well->count)
|
2015-07-31 05:20:27 +08:00
|
|
|
intel_power_well_disable(dev_priv, power_well);
|
2014-09-30 16:56:38 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
mutex_unlock(&power_domains->lock);
|
|
|
|
|
|
|
|
intel_runtime_pm_put(dev_priv);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define HSW_ALWAYS_ON_POWER_DOMAINS ( \
|
|
|
|
BIT(POWER_DOMAIN_PIPE_A) | \
|
|
|
|
BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_CRT) | \
|
|
|
|
BIT(POWER_DOMAIN_PLLS) | \
|
2015-01-16 23:57:51 +08:00
|
|
|
BIT(POWER_DOMAIN_AUX_A) | \
|
|
|
|
BIT(POWER_DOMAIN_AUX_B) | \
|
|
|
|
BIT(POWER_DOMAIN_AUX_C) | \
|
|
|
|
BIT(POWER_DOMAIN_AUX_D) | \
|
2015-11-09 23:48:19 +08:00
|
|
|
BIT(POWER_DOMAIN_GMBUS) | \
|
2014-09-30 16:56:38 +08:00
|
|
|
BIT(POWER_DOMAIN_INIT))
|
|
|
|
#define HSW_DISPLAY_POWER_DOMAINS ( \
|
|
|
|
(POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
|
|
|
|
BIT(POWER_DOMAIN_INIT))
|
|
|
|
|
|
|
|
#define BDW_ALWAYS_ON_POWER_DOMAINS ( \
|
|
|
|
HSW_ALWAYS_ON_POWER_DOMAINS | \
|
|
|
|
BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
|
|
|
|
#define BDW_DISPLAY_POWER_DOMAINS ( \
|
|
|
|
(POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
|
|
|
|
BIT(POWER_DOMAIN_INIT))
|
|
|
|
|
|
|
|
#define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
|
|
|
|
#define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
|
|
|
|
|
|
|
|
#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_CRT) | \
|
2015-01-16 23:57:51 +08:00
|
|
|
BIT(POWER_DOMAIN_AUX_B) | \
|
|
|
|
BIT(POWER_DOMAIN_AUX_C) | \
|
2014-09-30 16:56:38 +08:00
|
|
|
BIT(POWER_DOMAIN_INIT))
|
|
|
|
|
|
|
|
#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
|
2015-01-16 23:57:51 +08:00
|
|
|
BIT(POWER_DOMAIN_AUX_B) | \
|
2014-09-30 16:56:38 +08:00
|
|
|
BIT(POWER_DOMAIN_INIT))
|
|
|
|
|
|
|
|
#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
|
2015-01-16 23:57:51 +08:00
|
|
|
BIT(POWER_DOMAIN_AUX_B) | \
|
2014-09-30 16:56:38 +08:00
|
|
|
BIT(POWER_DOMAIN_INIT))
|
|
|
|
|
|
|
|
#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
|
2015-01-16 23:57:51 +08:00
|
|
|
BIT(POWER_DOMAIN_AUX_C) | \
|
2014-09-30 16:56:38 +08:00
|
|
|
BIT(POWER_DOMAIN_INIT))
|
|
|
|
|
|
|
|
#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
|
2015-01-16 23:57:51 +08:00
|
|
|
BIT(POWER_DOMAIN_AUX_C) | \
|
2014-09-30 16:56:38 +08:00
|
|
|
BIT(POWER_DOMAIN_INIT))
|
|
|
|
|
|
|
|
#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
|
2015-01-16 23:57:51 +08:00
|
|
|
BIT(POWER_DOMAIN_AUX_B) | \
|
|
|
|
BIT(POWER_DOMAIN_AUX_C) | \
|
2014-09-30 16:56:38 +08:00
|
|
|
BIT(POWER_DOMAIN_INIT))
|
|
|
|
|
|
|
|
#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
|
|
|
|
BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
|
2015-01-16 23:57:51 +08:00
|
|
|
BIT(POWER_DOMAIN_AUX_D) | \
|
2014-09-30 16:56:38 +08:00
|
|
|
BIT(POWER_DOMAIN_INIT))
|
|
|
|
|
|
|
|
static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
|
|
|
|
.sync_hw = i9xx_always_on_power_well_noop,
|
|
|
|
.enable = i9xx_always_on_power_well_noop,
|
|
|
|
.disable = i9xx_always_on_power_well_noop,
|
|
|
|
.is_enabled = i9xx_always_on_power_well_enabled,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct i915_power_well_ops chv_pipe_power_well_ops = {
|
|
|
|
.sync_hw = chv_pipe_power_well_sync_hw,
|
|
|
|
.enable = chv_pipe_power_well_enable,
|
|
|
|
.disable = chv_pipe_power_well_disable,
|
|
|
|
.is_enabled = chv_pipe_power_well_enabled,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
|
|
|
|
.sync_hw = vlv_power_well_sync_hw,
|
|
|
|
.enable = chv_dpio_cmn_power_well_enable,
|
|
|
|
.disable = chv_dpio_cmn_power_well_disable,
|
|
|
|
.is_enabled = vlv_power_well_enabled,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct i915_power_well i9xx_always_on_power_well[] = {
|
|
|
|
{
|
|
|
|
.name = "always-on",
|
|
|
|
.always_on = 1,
|
|
|
|
.domains = POWER_DOMAIN_MASK,
|
|
|
|
.ops = &i9xx_always_on_power_well_ops,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct i915_power_well_ops hsw_power_well_ops = {
|
|
|
|
.sync_hw = hsw_power_well_sync_hw,
|
|
|
|
.enable = hsw_power_well_enable,
|
|
|
|
.disable = hsw_power_well_disable,
|
|
|
|
.is_enabled = hsw_power_well_enabled,
|
|
|
|
};
|
|
|
|
|
2015-02-04 21:57:44 +08:00
|
|
|
static const struct i915_power_well_ops skl_power_well_ops = {
|
|
|
|
.sync_hw = skl_power_well_sync_hw,
|
|
|
|
.enable = skl_power_well_enable,
|
|
|
|
.disable = skl_power_well_disable,
|
|
|
|
.is_enabled = skl_power_well_enabled,
|
|
|
|
};
|
|
|
|
|
2014-09-30 16:56:38 +08:00
|
|
|
static struct i915_power_well hsw_power_wells[] = {
|
|
|
|
{
|
|
|
|
.name = "always-on",
|
|
|
|
.always_on = 1,
|
|
|
|
.domains = HSW_ALWAYS_ON_POWER_DOMAINS,
|
|
|
|
.ops = &i9xx_always_on_power_well_ops,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "display",
|
|
|
|
.domains = HSW_DISPLAY_POWER_DOMAINS,
|
|
|
|
.ops = &hsw_power_well_ops,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct i915_power_well bdw_power_wells[] = {
|
|
|
|
{
|
|
|
|
.name = "always-on",
|
|
|
|
.always_on = 1,
|
|
|
|
.domains = BDW_ALWAYS_ON_POWER_DOMAINS,
|
|
|
|
.ops = &i9xx_always_on_power_well_ops,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "display",
|
|
|
|
.domains = BDW_DISPLAY_POWER_DOMAINS,
|
|
|
|
.ops = &hsw_power_well_ops,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct i915_power_well_ops vlv_display_power_well_ops = {
|
|
|
|
.sync_hw = vlv_power_well_sync_hw,
|
|
|
|
.enable = vlv_display_power_well_enable,
|
|
|
|
.disable = vlv_display_power_well_disable,
|
|
|
|
.is_enabled = vlv_power_well_enabled,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
|
|
|
|
.sync_hw = vlv_power_well_sync_hw,
|
|
|
|
.enable = vlv_dpio_cmn_power_well_enable,
|
|
|
|
.disable = vlv_dpio_cmn_power_well_disable,
|
|
|
|
.is_enabled = vlv_power_well_enabled,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
|
|
|
|
.sync_hw = vlv_power_well_sync_hw,
|
|
|
|
.enable = vlv_power_well_enable,
|
|
|
|
.disable = vlv_power_well_disable,
|
|
|
|
.is_enabled = vlv_power_well_enabled,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct i915_power_well vlv_power_wells[] = {
|
|
|
|
{
|
|
|
|
.name = "always-on",
|
|
|
|
.always_on = 1,
|
|
|
|
.domains = VLV_ALWAYS_ON_POWER_DOMAINS,
|
|
|
|
.ops = &i9xx_always_on_power_well_ops,
|
2015-11-05 01:24:10 +08:00
|
|
|
.data = PUNIT_POWER_WELL_ALWAYS_ON,
|
2014-09-30 16:56:38 +08:00
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "display",
|
|
|
|
.domains = VLV_DISPLAY_POWER_DOMAINS,
|
|
|
|
.data = PUNIT_POWER_WELL_DISP2D,
|
|
|
|
.ops = &vlv_display_power_well_ops,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "dpio-tx-b-01",
|
|
|
|
.domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
|
|
|
|
VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
|
|
|
|
VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
|
|
|
|
VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
|
|
|
|
.ops = &vlv_dpio_power_well_ops,
|
|
|
|
.data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "dpio-tx-b-23",
|
|
|
|
.domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
|
|
|
|
VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
|
|
|
|
VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
|
|
|
|
VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
|
|
|
|
.ops = &vlv_dpio_power_well_ops,
|
|
|
|
.data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "dpio-tx-c-01",
|
|
|
|
.domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
|
|
|
|
VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
|
|
|
|
VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
|
|
|
|
VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
|
|
|
|
.ops = &vlv_dpio_power_well_ops,
|
|
|
|
.data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "dpio-tx-c-23",
|
|
|
|
.domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
|
|
|
|
VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
|
|
|
|
VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
|
|
|
|
VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
|
|
|
|
.ops = &vlv_dpio_power_well_ops,
|
|
|
|
.data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "dpio-common",
|
|
|
|
.domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
|
|
|
|
.data = PUNIT_POWER_WELL_DPIO_CMN_BC,
|
|
|
|
.ops = &vlv_dpio_cmn_power_well_ops,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct i915_power_well chv_power_wells[] = {
|
|
|
|
{
|
|
|
|
.name = "always-on",
|
|
|
|
.always_on = 1,
|
|
|
|
.domains = VLV_ALWAYS_ON_POWER_DOMAINS,
|
|
|
|
.ops = &i9xx_always_on_power_well_ops,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "display",
|
2014-10-27 22:07:32 +08:00
|
|
|
/*
|
2015-05-27 01:22:39 +08:00
|
|
|
* Pipe A power well is the new disp2d well. Pipe B and C
|
|
|
|
* power wells don't actually exist. Pipe A power well is
|
|
|
|
* required for any pipe to work.
|
2014-10-27 22:07:32 +08:00
|
|
|
*/
|
2015-05-27 01:22:39 +08:00
|
|
|
.domains = VLV_DISPLAY_POWER_DOMAINS,
|
2014-09-30 16:56:38 +08:00
|
|
|
.data = PIPE_A,
|
|
|
|
.ops = &chv_pipe_power_well_ops,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "dpio-common-bc",
|
2015-04-10 23:21:29 +08:00
|
|
|
.domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
|
2014-09-30 16:56:38 +08:00
|
|
|
.data = PUNIT_POWER_WELL_DPIO_CMN_BC,
|
|
|
|
.ops = &chv_dpio_cmn_power_well_ops,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "dpio-common-d",
|
2015-04-10 23:21:29 +08:00
|
|
|
.domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
|
2014-09-30 16:56:38 +08:00
|
|
|
.data = PUNIT_POWER_WELL_DPIO_CMN_D,
|
|
|
|
.ops = &chv_dpio_cmn_power_well_ops,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2015-04-16 16:52:10 +08:00
|
|
|
bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
|
|
|
|
int power_well_id)
|
|
|
|
{
|
|
|
|
struct i915_power_well *power_well;
|
|
|
|
bool ret;
|
|
|
|
|
|
|
|
power_well = lookup_power_well(dev_priv, power_well_id);
|
|
|
|
ret = power_well->ops->is_enabled(dev_priv, power_well);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-02-04 21:57:44 +08:00
|
|
|
static struct i915_power_well skl_power_wells[] = {
|
|
|
|
{
|
|
|
|
.name = "always-on",
|
|
|
|
.always_on = 1,
|
|
|
|
.domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
|
|
|
|
.ops = &i9xx_always_on_power_well_ops,
|
2015-11-05 01:24:10 +08:00
|
|
|
.data = SKL_DISP_PW_ALWAYS_ON,
|
2015-02-04 21:57:44 +08:00
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "power well 1",
|
2015-11-05 01:24:15 +08:00
|
|
|
/* Handled by the DMC firmware */
|
|
|
|
.domains = 0,
|
2015-02-04 21:57:44 +08:00
|
|
|
.ops = &skl_power_well_ops,
|
|
|
|
.data = SKL_DISP_PW_1,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "MISC IO power well",
|
2015-11-05 01:24:15 +08:00
|
|
|
/* Handled by the DMC firmware */
|
|
|
|
.domains = 0,
|
2015-02-04 21:57:44 +08:00
|
|
|
.ops = &skl_power_well_ops,
|
|
|
|
.data = SKL_DISP_PW_MISC_IO,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "power well 2",
|
|
|
|
.domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
|
|
|
|
.ops = &skl_power_well_ops,
|
|
|
|
.data = SKL_DISP_PW_2,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "DDI A/E power well",
|
|
|
|
.domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
|
|
|
|
.ops = &skl_power_well_ops,
|
|
|
|
.data = SKL_DISP_PW_DDI_A_E,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "DDI B power well",
|
|
|
|
.domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
|
|
|
|
.ops = &skl_power_well_ops,
|
|
|
|
.data = SKL_DISP_PW_DDI_B,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "DDI C power well",
|
|
|
|
.domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
|
|
|
|
.ops = &skl_power_well_ops,
|
|
|
|
.data = SKL_DISP_PW_DDI_C,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "DDI D power well",
|
|
|
|
.domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
|
|
|
|
.ops = &skl_power_well_ops,
|
|
|
|
.data = SKL_DISP_PW_DDI_D,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
drm/i915: Make turning on/off PW1 and Misc I/O part of the init/fini sequences
Before this patch, we used the intel_display_power_{get,put} functions
to make sure the PW1 and Misc I/O power wells were enabled all the
time while LCPLL was enabled. We called a get() at
intel_ddi_pll_init() when we discovered that LCPLL was enabled, then
we would call put/get at skl_{un,}init_cdclk().
The problem is that skl_uninit_cdclk() is indirectly called by
intel_runtime_suspend(). So it will only release its power well
_after_ we already decided to runtime suspend. But since we only
decide to runtime suspend after all power wells and refcounts are
released, that basically means we will never decide to runtime
suspend.
So what this patch does to fix that problem is move the PW1 + Misc I/O
power well handling out of the runtime PM mechanism: instead of
calling intel_display_power_{get_put} - functions that touch the
refcount -, we'll call the low level intel_power_well_{en,dis}able,
which don't change the refcount. This way, it is now possible for the
refcount to actually reach zero, and we'll now start runtime
suspending/resuming.
v2 (from Paulo):
- Write a commit message since the original patch left it empty.
- Rebase after the intel_power_well_{en,dis}able rename.
- Use lookup_power_well() instead of hardcoded indexes.
Testcase: igt/pm_rpm/rte (and every other rpm test)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92211
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92605
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446657859-9598-4-git-send-email-imre.deak@intel.com
2015-11-05 01:24:12 +08:00
|
|
|
void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct i915_power_well *well;
|
|
|
|
|
|
|
|
if (!IS_SKYLAKE(dev_priv))
|
|
|
|
return;
|
|
|
|
|
|
|
|
well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
|
|
|
|
intel_power_well_enable(dev_priv, well);
|
|
|
|
|
|
|
|
well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
|
|
|
|
intel_power_well_enable(dev_priv, well);
|
|
|
|
}
|
|
|
|
|
|
|
|
void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct i915_power_well *well;
|
|
|
|
|
|
|
|
if (!IS_SKYLAKE(dev_priv))
|
|
|
|
return;
|
|
|
|
|
|
|
|
well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
|
|
|
|
intel_power_well_disable(dev_priv, well);
|
|
|
|
|
|
|
|
well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
|
|
|
|
intel_power_well_disable(dev_priv, well);
|
|
|
|
}
|
|
|
|
|
2014-07-11 17:21:13 +08:00
|
|
|
static struct i915_power_well bxt_power_wells[] = {
|
|
|
|
{
|
|
|
|
.name = "always-on",
|
|
|
|
.always_on = 1,
|
|
|
|
.domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
|
|
|
|
.ops = &i9xx_always_on_power_well_ops,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "power well 1",
|
|
|
|
.domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS,
|
|
|
|
.ops = &skl_power_well_ops,
|
|
|
|
.data = SKL_DISP_PW_1,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.name = "power well 2",
|
|
|
|
.domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
|
|
|
|
.ops = &skl_power_well_ops,
|
|
|
|
.data = SKL_DISP_PW_2,
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2014-09-30 16:56:38 +08:00
|
|
|
#define set_power_wells(power_domains, __power_wells) ({ \
|
|
|
|
(power_domains)->power_wells = (__power_wells); \
|
|
|
|
(power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
|
|
|
|
})
|
|
|
|
|
2014-09-30 16:56:42 +08:00
|
|
|
/**
|
|
|
|
* intel_power_domains_init - initializes the power domain structures
|
|
|
|
* @dev_priv: i915 device instance
|
|
|
|
*
|
|
|
|
* Initializes the power domain structures for @dev_priv depending upon the
|
|
|
|
* supported platform.
|
|
|
|
*/
|
2014-09-30 16:56:38 +08:00
|
|
|
int intel_power_domains_init(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct i915_power_domains *power_domains = &dev_priv->power_domains;
|
|
|
|
|
2015-11-09 23:48:19 +08:00
|
|
|
BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
|
|
|
|
|
2014-09-30 16:56:38 +08:00
|
|
|
mutex_init(&power_domains->lock);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The enabling order will be from lower to higher indexed wells,
|
|
|
|
* the disabling order is reversed.
|
|
|
|
*/
|
|
|
|
if (IS_HASWELL(dev_priv->dev)) {
|
|
|
|
set_power_wells(power_domains, hsw_power_wells);
|
|
|
|
} else if (IS_BROADWELL(dev_priv->dev)) {
|
|
|
|
set_power_wells(power_domains, bdw_power_wells);
|
2015-10-28 19:16:45 +08:00
|
|
|
} else if (IS_SKYLAKE(dev_priv->dev) || IS_KABYLAKE(dev_priv->dev)) {
|
2015-02-04 21:57:44 +08:00
|
|
|
set_power_wells(power_domains, skl_power_wells);
|
2014-07-11 17:21:13 +08:00
|
|
|
} else if (IS_BROXTON(dev_priv->dev)) {
|
|
|
|
set_power_wells(power_domains, bxt_power_wells);
|
2014-09-30 16:56:38 +08:00
|
|
|
} else if (IS_CHERRYVIEW(dev_priv->dev)) {
|
|
|
|
set_power_wells(power_domains, chv_power_wells);
|
|
|
|
} else if (IS_VALLEYVIEW(dev_priv->dev)) {
|
|
|
|
set_power_wells(power_domains, vlv_power_wells);
|
|
|
|
} else {
|
|
|
|
set_power_wells(power_domains, i9xx_always_on_power_well);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-09-30 16:56:42 +08:00
|
|
|
/**
|
|
|
|
* intel_power_domains_fini - finalizes the power domain structures
|
|
|
|
* @dev_priv: i915 device instance
|
|
|
|
*
|
|
|
|
* Finalizes the power domain structures for @dev_priv depending upon the
|
|
|
|
* supported platform. This function also disables runtime pm and ensures that
|
|
|
|
* the device stays powered up so that the driver can be reloaded.
|
|
|
|
*/
|
2014-09-30 16:56:39 +08:00
|
|
|
void intel_power_domains_fini(struct drm_i915_private *dev_priv)
|
2014-09-30 16:56:38 +08:00
|
|
|
{
|
2014-09-30 16:56:39 +08:00
|
|
|
/* The i915.ko module is still not prepared to be loaded when
|
|
|
|
* the power well is not enabled, so just enable it in case
|
|
|
|
* we're going to unload/reload. */
|
|
|
|
intel_display_set_init_power(dev_priv, true);
|
2015-11-17 23:44:23 +08:00
|
|
|
|
|
|
|
/* Remove the refcount we took to keep power well support disabled. */
|
|
|
|
if (!i915.disable_power_well)
|
|
|
|
intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
|
2014-09-30 16:56:38 +08:00
|
|
|
}
|
|
|
|
|
2015-11-05 01:24:13 +08:00
|
|
|
static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
|
2014-09-30 16:56:38 +08:00
|
|
|
{
|
|
|
|
struct i915_power_domains *power_domains = &dev_priv->power_domains;
|
|
|
|
struct i915_power_well *power_well;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
mutex_lock(&power_domains->lock);
|
|
|
|
for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
|
|
|
|
power_well->ops->sync_hw(dev_priv, power_well);
|
|
|
|
power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
|
|
|
|
power_well);
|
|
|
|
}
|
|
|
|
mutex_unlock(&power_domains->lock);
|
|
|
|
}
|
|
|
|
|
2015-11-17 23:33:53 +08:00
|
|
|
static void skl_display_core_init(struct drm_i915_private *dev_priv,
|
|
|
|
bool resume)
|
|
|
|
{
|
|
|
|
struct i915_power_domains *power_domains = &dev_priv->power_domains;
|
|
|
|
uint32_t val;
|
|
|
|
|
2015-11-05 01:24:17 +08:00
|
|
|
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
|
|
|
|
|
2015-11-17 23:33:53 +08:00
|
|
|
/* enable PCH reset handshake */
|
|
|
|
val = I915_READ(HSW_NDE_RSTWRN_OPT);
|
|
|
|
I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
|
|
|
|
|
|
|
|
/* enable PG1 and Misc I/O */
|
|
|
|
mutex_lock(&power_domains->lock);
|
|
|
|
skl_pw1_misc_io_init(dev_priv);
|
|
|
|
mutex_unlock(&power_domains->lock);
|
|
|
|
|
|
|
|
if (!resume)
|
|
|
|
return;
|
|
|
|
|
|
|
|
skl_init_cdclk(dev_priv);
|
|
|
|
|
|
|
|
if (dev_priv->csr.dmc_payload)
|
|
|
|
intel_csr_load_program(dev_priv);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct i915_power_domains *power_domains = &dev_priv->power_domains;
|
|
|
|
|
2015-11-05 01:24:17 +08:00
|
|
|
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
|
|
|
|
|
2015-11-17 23:33:53 +08:00
|
|
|
skl_uninit_cdclk(dev_priv);
|
|
|
|
|
|
|
|
/* The spec doesn't call for removing the reset handshake flag */
|
|
|
|
/* disable PG1 and Misc I/O */
|
|
|
|
mutex_lock(&power_domains->lock);
|
|
|
|
skl_pw1_misc_io_fini(dev_priv);
|
|
|
|
mutex_unlock(&power_domains->lock);
|
|
|
|
}
|
|
|
|
|
2015-04-10 23:21:28 +08:00
|
|
|
static void chv_phy_control_init(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct i915_power_well *cmn_bc =
|
|
|
|
lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
|
|
|
|
struct i915_power_well *cmn_d =
|
|
|
|
lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* DISPLAY_PHY_CONTROL can get corrupted if read. As a
|
|
|
|
* workaround never ever read DISPLAY_PHY_CONTROL, and
|
|
|
|
* instead maintain a shadow copy ourselves. Use the actual
|
2015-07-09 04:45:54 +08:00
|
|
|
* power well state and lane status to reconstruct the
|
|
|
|
* expected initial value.
|
2015-04-10 23:21:28 +08:00
|
|
|
*/
|
|
|
|
dev_priv->chv_phy_control =
|
2015-05-27 01:22:38 +08:00
|
|
|
PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
|
|
|
|
PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
|
2015-07-09 04:45:54 +08:00
|
|
|
PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
|
|
|
|
PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
|
|
|
|
PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If all lanes are disabled we leave the override disabled
|
|
|
|
* with all power down bits cleared to match the state we
|
|
|
|
* would use after disabling the port. Otherwise enable the
|
|
|
|
* override and set the lane powerdown bits accding to the
|
|
|
|
* current lane status.
|
|
|
|
*/
|
|
|
|
if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
|
|
|
|
uint32_t status = I915_READ(DPLL(PIPE_A));
|
|
|
|
unsigned int mask;
|
|
|
|
|
|
|
|
mask = status & DPLL_PORTB_READY_MASK;
|
|
|
|
if (mask == 0xf)
|
|
|
|
mask = 0x0;
|
|
|
|
else
|
|
|
|
dev_priv->chv_phy_control |=
|
|
|
|
PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
|
|
|
|
|
|
|
|
dev_priv->chv_phy_control |=
|
|
|
|
PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
|
|
|
|
|
|
|
|
mask = (status & DPLL_PORTC_READY_MASK) >> 4;
|
|
|
|
if (mask == 0xf)
|
|
|
|
mask = 0x0;
|
|
|
|
else
|
|
|
|
dev_priv->chv_phy_control |=
|
|
|
|
PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
|
|
|
|
|
|
|
|
dev_priv->chv_phy_control |=
|
|
|
|
PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
|
|
|
|
|
2015-04-10 23:21:28 +08:00
|
|
|
dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
|
2015-09-08 23:05:45 +08:00
|
|
|
|
|
|
|
dev_priv->chv_phy_assert[DPIO_PHY0] = false;
|
|
|
|
} else {
|
|
|
|
dev_priv->chv_phy_assert[DPIO_PHY0] = true;
|
2015-07-09 04:45:54 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
|
|
|
|
uint32_t status = I915_READ(DPIO_PHY_STATUS);
|
|
|
|
unsigned int mask;
|
|
|
|
|
|
|
|
mask = status & DPLL_PORTD_READY_MASK;
|
|
|
|
|
|
|
|
if (mask == 0xf)
|
|
|
|
mask = 0x0;
|
|
|
|
else
|
|
|
|
dev_priv->chv_phy_control |=
|
|
|
|
PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
|
|
|
|
|
|
|
|
dev_priv->chv_phy_control |=
|
|
|
|
PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
|
|
|
|
|
2015-04-10 23:21:28 +08:00
|
|
|
dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
|
2015-09-08 23:05:45 +08:00
|
|
|
|
|
|
|
dev_priv->chv_phy_assert[DPIO_PHY1] = false;
|
|
|
|
} else {
|
|
|
|
dev_priv->chv_phy_assert[DPIO_PHY1] = true;
|
2015-07-09 04:45:54 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
|
|
|
|
dev_priv->chv_phy_control);
|
2015-04-10 23:21:28 +08:00
|
|
|
}
|
|
|
|
|
2014-09-30 16:56:38 +08:00
|
|
|
static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct i915_power_well *cmn =
|
|
|
|
lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
|
|
|
|
struct i915_power_well *disp2d =
|
|
|
|
lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
|
|
|
|
|
|
|
|
/* If the display might be already active skip this */
|
2014-10-17 01:52:33 +08:00
|
|
|
if (cmn->ops->is_enabled(dev_priv, cmn) &&
|
|
|
|
disp2d->ops->is_enabled(dev_priv, disp2d) &&
|
2014-09-30 16:56:38 +08:00
|
|
|
I915_READ(DPIO_CTL) & DPIO_CMNRST)
|
|
|
|
return;
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("toggling display PHY side reset\n");
|
|
|
|
|
|
|
|
/* cmnlane needs DPLL registers */
|
|
|
|
disp2d->ops->enable(dev_priv, disp2d);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
|
|
|
|
* Need to assert and de-assert PHY SB reset by gating the
|
|
|
|
* common lane power, then un-gating it.
|
|
|
|
* Simply ungating isn't enough to reset the PHY enough to get
|
|
|
|
* ports and lanes running.
|
|
|
|
*/
|
|
|
|
cmn->ops->disable(dev_priv, cmn);
|
|
|
|
}
|
|
|
|
|
2014-09-30 16:56:42 +08:00
|
|
|
/**
|
|
|
|
* intel_power_domains_init_hw - initialize hardware power domain state
|
|
|
|
* @dev_priv: i915 device instance
|
|
|
|
*
|
|
|
|
* This function initializes the hardware power domain state and enables all
|
|
|
|
* power domains using intel_display_set_init_power().
|
|
|
|
*/
|
2015-11-17 23:33:53 +08:00
|
|
|
void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
|
2014-09-30 16:56:38 +08:00
|
|
|
{
|
|
|
|
struct drm_device *dev = dev_priv->dev;
|
|
|
|
struct i915_power_domains *power_domains = &dev_priv->power_domains;
|
|
|
|
|
|
|
|
power_domains->initializing = true;
|
|
|
|
|
2015-11-17 23:33:53 +08:00
|
|
|
if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
|
|
|
|
skl_display_core_init(dev_priv, resume);
|
|
|
|
} else if (IS_CHERRYVIEW(dev)) {
|
2015-07-09 04:45:51 +08:00
|
|
|
mutex_lock(&power_domains->lock);
|
2015-04-10 23:21:28 +08:00
|
|
|
chv_phy_control_init(dev_priv);
|
2015-07-09 04:45:51 +08:00
|
|
|
mutex_unlock(&power_domains->lock);
|
2015-04-10 23:21:28 +08:00
|
|
|
} else if (IS_VALLEYVIEW(dev)) {
|
2014-09-30 16:56:38 +08:00
|
|
|
mutex_lock(&power_domains->lock);
|
|
|
|
vlv_cmnlane_wa(dev_priv);
|
|
|
|
mutex_unlock(&power_domains->lock);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* For now, we need the power well to be always enabled. */
|
|
|
|
intel_display_set_init_power(dev_priv, true);
|
2015-11-17 23:44:23 +08:00
|
|
|
/* Disable power support if the user asked so. */
|
|
|
|
if (!i915.disable_power_well)
|
|
|
|
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
|
2015-11-05 01:24:13 +08:00
|
|
|
intel_power_domains_sync_hw(dev_priv);
|
2014-09-30 16:56:38 +08:00
|
|
|
power_domains->initializing = false;
|
|
|
|
}
|
|
|
|
|
2015-11-17 23:33:53 +08:00
|
|
|
/**
|
|
|
|
* intel_power_domains_suspend - suspend power domain state
|
|
|
|
* @dev_priv: i915 device instance
|
|
|
|
*
|
|
|
|
* This function prepares the hardware power domain state before entering
|
|
|
|
* system suspend. It must be paired with intel_power_domains_init_hw().
|
|
|
|
*/
|
|
|
|
void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
|
|
|
|
skl_display_core_uninit(dev_priv);
|
2015-11-17 23:44:23 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Even if power well support was disabled we still want to disable
|
|
|
|
* power wells while we are system suspended.
|
|
|
|
*/
|
|
|
|
if (!i915.disable_power_well)
|
|
|
|
intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
|
2015-11-17 23:33:53 +08:00
|
|
|
}
|
|
|
|
|
2014-09-30 16:56:42 +08:00
|
|
|
/**
|
|
|
|
* intel_runtime_pm_get - grab a runtime pm reference
|
|
|
|
* @dev_priv: i915 device instance
|
|
|
|
*
|
|
|
|
* This function grabs a device-level runtime pm reference (mostly used for GEM
|
|
|
|
* code to ensure the GTT or GT is on) and ensures that it is powered up.
|
|
|
|
*
|
|
|
|
* Any runtime pm reference obtained by this function must have a symmetric
|
|
|
|
* call to intel_runtime_pm_put() to release the reference again.
|
|
|
|
*/
|
2014-09-30 16:56:38 +08:00
|
|
|
void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = dev_priv->dev;
|
|
|
|
struct device *device = &dev->pdev->dev;
|
|
|
|
|
|
|
|
if (!HAS_RUNTIME_PM(dev))
|
|
|
|
return;
|
|
|
|
|
|
|
|
pm_runtime_get_sync(device);
|
|
|
|
WARN(dev_priv->pm.suspended, "Device still suspended.\n");
|
|
|
|
}
|
|
|
|
|
2014-09-30 16:56:42 +08:00
|
|
|
/**
|
|
|
|
* intel_runtime_pm_get_noresume - grab a runtime pm reference
|
|
|
|
* @dev_priv: i915 device instance
|
|
|
|
*
|
|
|
|
* This function grabs a device-level runtime pm reference (mostly used for GEM
|
|
|
|
* code to ensure the GTT or GT is on).
|
|
|
|
*
|
|
|
|
* It will _not_ power up the device but instead only check that it's powered
|
|
|
|
* on. Therefore it is only valid to call this functions from contexts where
|
|
|
|
* the device is known to be powered up and where trying to power it up would
|
|
|
|
* result in hilarity and deadlocks. That pretty much means only the system
|
|
|
|
* suspend/resume code where this is used to grab runtime pm references for
|
|
|
|
* delayed setup down in work items.
|
|
|
|
*
|
|
|
|
* Any runtime pm reference obtained by this function must have a symmetric
|
|
|
|
* call to intel_runtime_pm_put() to release the reference again.
|
|
|
|
*/
|
2014-09-30 16:56:38 +08:00
|
|
|
void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = dev_priv->dev;
|
|
|
|
struct device *device = &dev->pdev->dev;
|
|
|
|
|
|
|
|
if (!HAS_RUNTIME_PM(dev))
|
|
|
|
return;
|
|
|
|
|
|
|
|
WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
|
|
|
|
pm_runtime_get_noresume(device);
|
|
|
|
}
|
|
|
|
|
2014-09-30 16:56:42 +08:00
|
|
|
/**
|
|
|
|
* intel_runtime_pm_put - release a runtime pm reference
|
|
|
|
* @dev_priv: i915 device instance
|
|
|
|
*
|
|
|
|
* This function drops the device-level runtime pm reference obtained by
|
|
|
|
* intel_runtime_pm_get() and might power down the corresponding
|
|
|
|
* hardware block right away if this is the last reference.
|
|
|
|
*/
|
2014-09-30 16:56:38 +08:00
|
|
|
void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = dev_priv->dev;
|
|
|
|
struct device *device = &dev->pdev->dev;
|
|
|
|
|
|
|
|
if (!HAS_RUNTIME_PM(dev))
|
|
|
|
return;
|
|
|
|
|
|
|
|
pm_runtime_mark_last_busy(device);
|
|
|
|
pm_runtime_put_autosuspend(device);
|
|
|
|
}
|
|
|
|
|
2014-09-30 16:56:42 +08:00
|
|
|
/**
|
|
|
|
* intel_runtime_pm_enable - enable runtime pm
|
|
|
|
* @dev_priv: i915 device instance
|
|
|
|
*
|
|
|
|
* This function enables runtime pm at the end of the driver load sequence.
|
|
|
|
*
|
|
|
|
* Note that this function does currently not enable runtime pm for the
|
|
|
|
* subordinate display power domains. That is only done on the first modeset
|
|
|
|
* using intel_display_set_init_power().
|
|
|
|
*/
|
2014-09-30 16:56:39 +08:00
|
|
|
void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
|
2014-09-30 16:56:38 +08:00
|
|
|
{
|
|
|
|
struct drm_device *dev = dev_priv->dev;
|
|
|
|
struct device *device = &dev->pdev->dev;
|
|
|
|
|
|
|
|
if (!HAS_RUNTIME_PM(dev))
|
|
|
|
return;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* RPM depends on RC6 to save restore the GT HW context, so make RC6 a
|
|
|
|
* requirement.
|
|
|
|
*/
|
|
|
|
if (!intel_enable_rc6(dev)) {
|
|
|
|
DRM_INFO("RC6 disabled, disabling runtime PM support\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
|
|
|
|
pm_runtime_mark_last_busy(device);
|
|
|
|
pm_runtime_use_autosuspend(device);
|
|
|
|
|
|
|
|
pm_runtime_put_autosuspend(device);
|
|
|
|
}
|
|
|
|
|