133 lines
2.8 KiB
C
133 lines
2.8 KiB
C
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/*
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* OMAP4XXX L3 Interconnect error handling driver header
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*
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* Copyright (C) 2011 Texas Corporation
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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* sricharan <r.sricharan@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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* USA
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
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#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
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/*
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* L3 register offsets
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*/
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#define L3_MODULES 3
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#define CLEAR_STDERR_LOG (1 << 31)
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#define CUSTOM_ERROR 0x2
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#define STANDARD_ERROR 0x0
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#define INBAND_ERROR 0x0
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#define EMIF_KERRLOG_OFFSET 0x10
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#define L3_SLAVE_ADDRESS_OFFSET 0x14
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#define LOGICAL_ADDR_ERRORLOG 0x4
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#define L3_APPLICATION_ERROR 0x0
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#define L3_DEBUG_ERROR 0x1
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u32 l3_flagmux[L3_MODULES] = {
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0x50C,
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0x100C,
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0X020C
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};
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/*
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* L3 Target standard Error register offsets
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*/
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u32 l3_targ_stderrlog_main_clk1[] = {
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0x148, /* DMM1 */
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0x248, /* DMM2 */
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0x348, /* ABE */
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0x448, /* L4CFG */
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0x648 /* CLK2 PWR DISC */
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};
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u32 l3_targ_stderrlog_main_clk2[] = {
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0x548, /* CORTEX M3 */
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0x348, /* DSS */
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0x148, /* GPMC */
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0x448, /* ISS */
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0x748, /* IVAHD */
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0xD48, /* missing in TRM corresponds to AES1*/
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0x948, /* L4 PER0*/
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0x248, /* OCMRAM */
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0x148, /* missing in TRM corresponds to GPMC sERROR*/
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0x648, /* SGX */
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0x848, /* SL2 */
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0x1648, /* C2C */
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0x1148, /* missing in TRM corresponds PWR DISC CLK1*/
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0xF48, /* missing in TRM corrsponds to SHA1*/
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0xE48, /* missing in TRM corresponds to AES2*/
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0xC48, /* L4 PER3 */
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0xA48, /* L4 PER1*/
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0xB48 /* L4 PER2*/
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};
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u32 l3_targ_stderrlog_main_clk3[] = {
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0x0148 /* EMUSS */
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};
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char *l3_targ_stderrlog_main_name[L3_MODULES][18] = {
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{
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"DMM1",
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"DMM2",
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"ABE",
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"L4CFG",
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"CLK2 PWR DISC",
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},
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{
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"CORTEX M3" ,
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"DSS ",
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"GPMC ",
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"ISS ",
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"IVAHD ",
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"AES1",
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"L4 PER0",
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"OCMRAM ",
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"GPMC sERROR",
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"SGX ",
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"SL2 ",
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"C2C ",
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"PWR DISC CLK1",
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"SHA1",
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"AES2",
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"L4 PER3",
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"L4 PER1",
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"L4 PER2",
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},
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{
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"EMUSS",
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},
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};
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u32 *l3_targ[L3_MODULES] = {
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l3_targ_stderrlog_main_clk1,
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l3_targ_stderrlog_main_clk2,
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l3_targ_stderrlog_main_clk3,
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};
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struct omap4_l3 {
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struct device *dev;
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struct clk *ick;
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/* memory base */
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void __iomem *l3_base[4];
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int debug_irq;
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int app_irq;
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};
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#endif
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