2009-04-08 07:16:42 +08:00
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/*
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* Copyright © 2008 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Keith Packard <keithp@keithp.com>
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*
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*/
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#include <linux/i2c.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 16:04:11 +08:00
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#include <linux/slab.h>
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2011-08-31 06:16:33 +08:00
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#include <linux/export.h>
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2012-10-03 01:01:07 +08:00
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#include <drm/drmP.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_edid.h>
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2009-04-08 07:16:42 +08:00
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#include "intel_drv.h"
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2012-10-03 01:01:07 +08:00
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#include <drm/i915_drm.h>
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2009-04-08 07:16:42 +08:00
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#include "i915_drv.h"
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#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
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2013-09-04 01:30:37 +08:00
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struct dp_link_dpll {
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int link_bw;
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struct dpll dpll;
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};
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static const struct dp_link_dpll gen4_dpll[] = {
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{ DP_LINK_BW_1_62,
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{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
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{ DP_LINK_BW_2_7,
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{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
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};
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static const struct dp_link_dpll pch_dpll[] = {
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{ DP_LINK_BW_1_62,
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{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
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{ DP_LINK_BW_2_7,
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{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
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};
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2013-09-04 01:30:38 +08:00
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static const struct dp_link_dpll vlv_dpll[] = {
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{ DP_LINK_BW_1_62,
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2013-09-25 15:47:51 +08:00
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{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
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2013-09-04 01:30:38 +08:00
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{ DP_LINK_BW_2_7,
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{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
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};
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2014-04-09 18:28:18 +08:00
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/*
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* CHV supports eDP 1.4 that have more link rates.
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* Below only provides the fixed rate but exclude variable rate.
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*/
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static const struct dp_link_dpll chv_dpll[] = {
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/*
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* CHV requires to program fractional division for m2.
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* m2 is stored in fixed point format using formula below
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* (m2_int << 22) | m2_fraction
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*/
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{ DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
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{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
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{ DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
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{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
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{ DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
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{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
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};
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2010-10-08 07:01:06 +08:00
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/**
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* is_edp - is the given port attached to an eDP panel (either CPU or PCH)
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* @intel_dp: DP struct
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*
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* If a CPU or PCH DP output is attached to an eDP panel, this function
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* will return true, and false otherwise.
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*/
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static bool is_edp(struct intel_dp *intel_dp)
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{
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2012-10-27 05:05:46 +08:00
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
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2010-10-08 07:01:06 +08:00
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}
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2013-05-08 18:14:06 +08:00
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static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
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2010-10-08 07:01:06 +08:00
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{
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2013-05-08 18:14:06 +08:00
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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return intel_dig_port->base.base.dev;
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2010-10-08 07:01:06 +08:00
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}
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2010-09-09 23:20:55 +08:00
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static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
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{
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2012-10-27 05:05:44 +08:00
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return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
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2010-09-09 23:20:55 +08:00
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}
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2010-08-04 20:50:23 +08:00
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static void intel_dp_link_down(struct intel_dp *intel_dp);
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2014-03-14 22:51:13 +08:00
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static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
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2014-01-17 21:39:48 +08:00
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static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
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2009-04-08 07:16:42 +08:00
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static int
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2010-08-04 20:50:23 +08:00
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intel_dp_max_link_bw(struct intel_dp *intel_dp)
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2009-04-08 07:16:42 +08:00
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{
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2011-07-08 02:10:58 +08:00
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int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
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2014-01-21 01:19:39 +08:00
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struct drm_device *dev = intel_dp->attached_connector->base.dev;
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2009-04-08 07:16:42 +08:00
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switch (max_link_bw) {
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case DP_LINK_BW_1_62:
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case DP_LINK_BW_2_7:
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break;
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2013-07-09 22:05:26 +08:00
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case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
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2014-04-29 22:00:22 +08:00
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if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
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INTEL_INFO(dev)->gen >= 8) &&
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2014-01-21 01:19:39 +08:00
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intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
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max_link_bw = DP_LINK_BW_5_4;
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else
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max_link_bw = DP_LINK_BW_2_7;
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2013-07-09 22:05:26 +08:00
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break;
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2009-04-08 07:16:42 +08:00
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default:
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2013-07-09 22:05:26 +08:00
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WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
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max_link_bw);
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2009-04-08 07:16:42 +08:00
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max_link_bw = DP_LINK_BW_1_62;
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break;
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}
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return max_link_bw;
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}
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2014-05-06 19:56:50 +08:00
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static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
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{
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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struct drm_device *dev = intel_dig_port->base.base.dev;
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u8 source_max, sink_max;
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source_max = 4;
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if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
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(intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
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source_max = 2;
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sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
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return min(source_max, sink_max);
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}
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2011-10-15 00:43:49 +08:00
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/*
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* The units on the numbers in the next two are... bizarre. Examples will
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* make it clearer; this one parallels an example in the eDP spec.
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*
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* intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
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*
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* 270000 * 1 * 8 / 10 == 216000
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*
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* The actual data capacity of that configuration is 2.16Gbit/s, so the
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* units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
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* or equivalently, kilopixels per second - so for 1680x1050R it'd be
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* 119000. At 18bpp that's 2142000 kilobits per second.
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*
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* Thus the strange-looking division by 10 in intel_dp_link_required, to
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* get the result in decakilobits instead of kilobits.
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*/
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2009-04-08 07:16:42 +08:00
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static int
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2012-01-26 00:16:25 +08:00
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intel_dp_link_required(int pixel_clock, int bpp)
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2009-04-08 07:16:42 +08:00
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{
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2011-10-15 00:43:49 +08:00
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return (pixel_clock * bpp + 9) / 10;
|
2009-04-08 07:16:42 +08:00
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}
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2010-06-30 09:46:17 +08:00
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static int
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intel_dp_max_data_rate(int max_link_clock, int max_lanes)
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{
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return (max_link_clock * max_lanes * 8) / 10;
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}
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2013-11-28 23:29:18 +08:00
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static enum drm_mode_status
|
2009-04-08 07:16:42 +08:00
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intel_dp_mode_valid(struct drm_connector *connector,
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struct drm_display_mode *mode)
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{
|
2010-09-09 23:20:55 +08:00
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struct intel_dp *intel_dp = intel_attached_dp(connector);
|
2012-10-19 19:51:50 +08:00
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struct intel_connector *intel_connector = to_intel_connector(connector);
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|
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struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
|
2013-03-27 07:44:59 +08:00
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int target_clock = mode->clock;
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int max_rate, mode_rate, max_lanes, max_link_clock;
|
2009-04-08 07:16:42 +08:00
|
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|
2012-10-19 19:51:50 +08:00
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if (is_edp(intel_dp) && fixed_mode) {
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|
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if (mode->hdisplay > fixed_mode->hdisplay)
|
2010-07-19 16:43:14 +08:00
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return MODE_PANEL;
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|
2012-10-19 19:51:50 +08:00
|
|
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if (mode->vdisplay > fixed_mode->vdisplay)
|
2010-07-19 16:43:14 +08:00
|
|
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return MODE_PANEL;
|
2013-04-03 05:42:31 +08:00
|
|
|
|
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|
|
target_clock = fixed_mode->clock;
|
2010-07-19 16:43:14 +08:00
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|
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}
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|
2013-03-27 07:44:59 +08:00
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|
|
max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
|
2014-05-06 19:56:50 +08:00
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max_lanes = intel_dp_max_lane_count(intel_dp);
|
2013-03-27 07:44:59 +08:00
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|
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max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
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|
|
|
mode_rate = intel_dp_link_required(target_clock, 18);
|
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|
|
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|
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if (mode_rate > max_rate)
|
2012-04-10 16:42:36 +08:00
|
|
|
return MODE_CLOCK_HIGH;
|
2009-04-08 07:16:42 +08:00
|
|
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|
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if (mode->clock < 10000)
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|
|
return MODE_CLOCK_LOW;
|
|
|
|
|
2012-05-23 17:30:55 +08:00
|
|
|
if (mode->flags & DRM_MODE_FLAG_DBLCLK)
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|
|
return MODE_H_ILLEGAL;
|
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
return MODE_OK;
|
|
|
|
}
|
|
|
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|
|
static uint32_t
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|
|
pack_aux(uint8_t *src, int src_bytes)
|
|
|
|
{
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|
|
|
int i;
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|
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uint32_t v = 0;
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|
|
if (src_bytes > 4)
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|
|
src_bytes = 4;
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|
|
for (i = 0; i < src_bytes; i++)
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|
|
|
v |= ((uint32_t) src[i]) << ((3-i) * 8);
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|
|
return v;
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|
|
}
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|
|
static void
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|
|
unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
|
|
|
|
{
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|
|
|
int i;
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|
|
if (dst_bytes > 4)
|
|
|
|
dst_bytes = 4;
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|
|
|
for (i = 0; i < dst_bytes; i++)
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|
|
|
dst[i] = src >> ((3-i) * 8);
|
|
|
|
}
|
|
|
|
|
2009-06-12 13:31:31 +08:00
|
|
|
/* hrawclock is 1/4 the FSB frequency */
|
|
|
|
static int
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|
|
intel_hrawclk(struct drm_device *dev)
|
|
|
|
{
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|
|
struct drm_i915_private *dev_priv = dev->dev_private;
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|
|
uint32_t clkcfg;
|
|
|
|
|
2012-09-27 21:43:01 +08:00
|
|
|
/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
|
|
|
|
if (IS_VALLEYVIEW(dev))
|
|
|
|
return 200;
|
|
|
|
|
2009-06-12 13:31:31 +08:00
|
|
|
clkcfg = I915_READ(CLKCFG);
|
|
|
|
switch (clkcfg & CLKCFG_FSB_MASK) {
|
|
|
|
case CLKCFG_FSB_400:
|
|
|
|
return 100;
|
|
|
|
case CLKCFG_FSB_533:
|
|
|
|
return 133;
|
|
|
|
case CLKCFG_FSB_667:
|
|
|
|
return 166;
|
|
|
|
case CLKCFG_FSB_800:
|
|
|
|
return 200;
|
|
|
|
case CLKCFG_FSB_1067:
|
|
|
|
return 266;
|
|
|
|
case CLKCFG_FSB_1333:
|
|
|
|
return 333;
|
|
|
|
/* these two are just a guess; one of them might be right */
|
|
|
|
case CLKCFG_FSB_1600:
|
|
|
|
case CLKCFG_FSB_1600_ALT:
|
|
|
|
return 400;
|
|
|
|
default:
|
|
|
|
return 133;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-09-06 12:40:05 +08:00
|
|
|
static void
|
|
|
|
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
|
|
|
|
struct intel_dp *intel_dp,
|
|
|
|
struct edp_power_seq *out);
|
|
|
|
static void
|
|
|
|
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
|
|
|
|
struct intel_dp *intel_dp,
|
|
|
|
struct edp_power_seq *out);
|
|
|
|
|
|
|
|
static enum pipe
|
|
|
|
vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
|
|
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
enum port port = intel_dig_port->port;
|
|
|
|
enum pipe pipe;
|
|
|
|
|
|
|
|
/* modeset should have pipe */
|
|
|
|
if (crtc)
|
|
|
|
return to_intel_crtc(crtc)->pipe;
|
|
|
|
|
|
|
|
/* init time, try to find a pipe with this port selected */
|
|
|
|
for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
|
|
|
|
u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
|
|
|
|
PANEL_PORT_SELECT_MASK;
|
|
|
|
if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
|
|
|
|
return pipe;
|
|
|
|
if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
|
|
|
|
return pipe;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* shrug */
|
|
|
|
return PIPE_A;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
|
|
|
|
|
|
|
if (HAS_PCH_SPLIT(dev))
|
|
|
|
return PCH_PP_CONTROL;
|
|
|
|
else
|
|
|
|
return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 _pp_stat_reg(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
|
|
|
|
|
|
|
if (HAS_PCH_SPLIT(dev))
|
|
|
|
return PCH_PP_STATUS;
|
|
|
|
else
|
|
|
|
return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
|
|
|
|
}
|
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
static bool edp_have_panel_power(struct intel_dp *intel_dp)
|
2011-09-30 06:53:27 +08:00
|
|
|
{
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2011-09-30 06:53:27 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
2013-09-06 12:40:05 +08:00
|
|
|
return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
|
2011-09-30 06:53:27 +08:00
|
|
|
}
|
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
|
2011-09-30 06:53:27 +08:00
|
|
|
{
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2011-09-30 06:53:27 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2014-04-15 01:24:33 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct intel_encoder *intel_encoder = &intel_dig_port->base;
|
|
|
|
enum intel_display_power_domain power_domain;
|
2011-09-30 06:53:27 +08:00
|
|
|
|
2014-04-15 01:24:33 +08:00
|
|
|
power_domain = intel_display_port_power_domain(intel_encoder);
|
|
|
|
return intel_display_power_enabled(dev_priv, power_domain) &&
|
2014-04-02 01:55:09 +08:00
|
|
|
(I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
|
2011-09-30 06:53:27 +08:00
|
|
|
}
|
|
|
|
|
2011-09-20 04:54:47 +08:00
|
|
|
static void
|
|
|
|
intel_dp_check_edp(struct intel_dp *intel_dp)
|
|
|
|
{
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2011-09-20 04:54:47 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2011-09-30 06:53:27 +08:00
|
|
|
|
2011-09-20 04:54:47 +08:00
|
|
|
if (!is_edp(intel_dp))
|
|
|
|
return;
|
2013-03-29 00:55:41 +08:00
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
|
2011-09-20 04:54:47 +08:00
|
|
|
WARN(1, "eDP powered off while attempting aux channel communication.\n");
|
|
|
|
DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
|
2013-09-06 12:40:05 +08:00
|
|
|
I915_READ(_pp_stat_reg(intel_dp)),
|
|
|
|
I915_READ(_pp_ctrl_reg(intel_dp)));
|
2011-09-20 04:54:47 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
static uint32_t
|
|
|
|
intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
|
|
|
|
{
|
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-02-19 06:00:25 +08:00
|
|
|
uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
uint32_t status;
|
|
|
|
bool done;
|
|
|
|
|
2012-12-02 04:03:59 +08:00
|
|
|
#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
if (has_aux_irq)
|
2013-02-19 06:00:24 +08:00
|
|
|
done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
|
2013-05-22 01:03:20 +08:00
|
|
|
msecs_to_jiffies_timeout(10));
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
else
|
|
|
|
done = wait_for_atomic(C, 10) == 0;
|
|
|
|
if (!done)
|
|
|
|
DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
|
|
|
|
has_aux_irq);
|
|
|
|
#undef C
|
|
|
|
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
2014-01-21 21:35:39 +08:00
|
|
|
static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2012-10-27 05:05:50 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
|
2014-01-21 21:35:39 +08:00
|
|
|
/*
|
|
|
|
* The clock divider is based off the hrawclk, and would like to run at
|
|
|
|
* 2MHz. So, take the hrawclk value and divide by 2 and use that
|
2009-04-08 07:16:42 +08:00
|
|
|
*/
|
2014-01-21 21:35:39 +08:00
|
|
|
return index ? 0 : intel_hrawclk(dev) / 2;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
|
|
|
|
{
|
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
|
|
|
|
|
|
|
if (index)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (intel_dig_port->port == PORT_A) {
|
|
|
|
if (IS_GEN6(dev) || IS_GEN7(dev))
|
2013-07-12 05:44:57 +08:00
|
|
|
return 200; /* SNB & IVB eDP input clock at 400Mhz */
|
2010-04-08 09:43:27 +08:00
|
|
|
else
|
2013-07-12 05:44:57 +08:00
|
|
|
return 225; /* eDP input clock at 450Mhz */
|
2014-01-21 21:35:39 +08:00
|
|
|
} else {
|
|
|
|
return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
|
|
|
|
{
|
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
if (intel_dig_port->port == PORT_A) {
|
|
|
|
if (index)
|
|
|
|
return 0;
|
|
|
|
return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
|
2013-04-09 13:11:00 +08:00
|
|
|
} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
|
|
|
|
/* Workaround for non-ULT HSW */
|
2013-07-21 23:00:03 +08:00
|
|
|
switch (index) {
|
|
|
|
case 0: return 63;
|
|
|
|
case 1: return 72;
|
|
|
|
default: return 0;
|
|
|
|
}
|
2014-01-21 21:35:39 +08:00
|
|
|
} else {
|
2013-07-21 23:00:03 +08:00
|
|
|
return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
|
2013-04-09 13:11:00 +08:00
|
|
|
}
|
2013-07-12 05:44:57 +08:00
|
|
|
}
|
|
|
|
|
2014-01-21 21:35:39 +08:00
|
|
|
static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
|
|
|
|
{
|
|
|
|
return index ? 0 : 100;
|
|
|
|
}
|
|
|
|
|
2014-01-20 23:52:30 +08:00
|
|
|
static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
|
|
|
|
bool has_aux_irq,
|
|
|
|
int send_bytes,
|
|
|
|
uint32_t aux_clock_divider)
|
|
|
|
{
|
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
|
|
|
uint32_t precharge, timeout;
|
|
|
|
|
|
|
|
if (IS_GEN6(dev))
|
|
|
|
precharge = 3;
|
|
|
|
else
|
|
|
|
precharge = 5;
|
|
|
|
|
|
|
|
if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
|
|
|
|
timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
|
|
|
|
else
|
|
|
|
timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
|
|
|
|
|
|
|
|
return DP_AUX_CH_CTL_SEND_BUSY |
|
2014-01-20 23:52:31 +08:00
|
|
|
DP_AUX_CH_CTL_DONE |
|
2014-01-20 23:52:30 +08:00
|
|
|
(has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
|
2014-01-20 23:52:31 +08:00
|
|
|
DP_AUX_CH_CTL_TIME_OUT_ERROR |
|
2014-01-20 23:52:30 +08:00
|
|
|
timeout |
|
2014-01-20 23:52:31 +08:00
|
|
|
DP_AUX_CH_CTL_RECEIVE_ERROR |
|
2014-01-20 23:52:30 +08:00
|
|
|
(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
|
|
|
|
(precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
|
2014-01-20 23:52:31 +08:00
|
|
|
(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
|
2014-01-20 23:52:30 +08:00
|
|
|
}
|
|
|
|
|
2013-07-12 05:44:57 +08:00
|
|
|
static int
|
|
|
|
intel_dp_aux_ch(struct intel_dp *intel_dp,
|
|
|
|
uint8_t *send, int send_bytes,
|
|
|
|
uint8_t *recv, int recv_size)
|
|
|
|
{
|
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
|
|
|
|
uint32_t ch_data = ch_ctl + 4;
|
2013-07-21 23:00:03 +08:00
|
|
|
uint32_t aux_clock_divider;
|
2013-07-12 05:44:57 +08:00
|
|
|
int i, ret, recv_bytes;
|
|
|
|
uint32_t status;
|
2014-01-20 23:52:30 +08:00
|
|
|
int try, clock = 0;
|
2014-02-07 23:33:20 +08:00
|
|
|
bool has_aux_irq = HAS_AUX_IRQ(dev);
|
2014-03-14 22:51:14 +08:00
|
|
|
bool vdd;
|
|
|
|
|
|
|
|
vdd = _edp_panel_vdd_on(intel_dp);
|
2013-07-12 05:44:57 +08:00
|
|
|
|
|
|
|
/* dp aux is extremely sensitive to irq latency, hence request the
|
|
|
|
* lowest possible wakeup latency and so prevent the cpu from going into
|
|
|
|
* deep sleep states.
|
|
|
|
*/
|
|
|
|
pm_qos_update_request(&dev_priv->pm_qos, 0);
|
|
|
|
|
|
|
|
intel_dp_check_edp(intel_dp);
|
2009-07-24 01:00:31 +08:00
|
|
|
|
2013-08-20 00:18:09 +08:00
|
|
|
intel_aux_display_runtime_get(dev_priv);
|
|
|
|
|
2011-08-02 06:02:20 +08:00
|
|
|
/* Try to wait for any previous AUX channel activity */
|
|
|
|
for (try = 0; try < 3; try++) {
|
2012-12-02 04:03:59 +08:00
|
|
|
status = I915_READ_NOTRACE(ch_ctl);
|
2011-08-02 06:02:20 +08:00
|
|
|
if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
|
|
|
|
break;
|
|
|
|
msleep(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (try == 3) {
|
|
|
|
WARN(1, "dp_aux_ch not started status 0x%08x\n",
|
|
|
|
I915_READ(ch_ctl));
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
ret = -EBUSY;
|
|
|
|
goto out;
|
2010-08-19 01:12:56 +08:00
|
|
|
}
|
|
|
|
|
2013-09-17 22:14:10 +08:00
|
|
|
/* Only 5 data registers! */
|
|
|
|
if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
|
|
|
|
ret = -E2BIG;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2014-01-21 21:35:39 +08:00
|
|
|
while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
|
2014-01-21 21:37:15 +08:00
|
|
|
u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
|
|
|
|
has_aux_irq,
|
|
|
|
send_bytes,
|
|
|
|
aux_clock_divider);
|
2014-01-20 23:52:30 +08:00
|
|
|
|
2013-07-21 23:00:03 +08:00
|
|
|
/* Must try at least 3 times according to DP spec */
|
|
|
|
for (try = 0; try < 5; try++) {
|
|
|
|
/* Load the send data into the aux channel data registers */
|
|
|
|
for (i = 0; i < send_bytes; i += 4)
|
|
|
|
I915_WRITE(ch_data + i,
|
|
|
|
pack_aux(send + i, send_bytes - i));
|
|
|
|
|
|
|
|
/* Send the command and wait for it to complete */
|
2014-01-20 23:52:30 +08:00
|
|
|
I915_WRITE(ch_ctl, send_ctl);
|
2013-07-21 23:00:03 +08:00
|
|
|
|
|
|
|
status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
|
|
|
|
|
|
|
|
/* Clear done status and any errors */
|
|
|
|
I915_WRITE(ch_ctl,
|
|
|
|
status |
|
|
|
|
DP_AUX_CH_CTL_DONE |
|
|
|
|
DP_AUX_CH_CTL_TIME_OUT_ERROR |
|
|
|
|
DP_AUX_CH_CTL_RECEIVE_ERROR);
|
|
|
|
|
|
|
|
if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
|
|
|
|
DP_AUX_CH_CTL_RECEIVE_ERROR))
|
|
|
|
continue;
|
|
|
|
if (status & DP_AUX_CH_CTL_DONE)
|
|
|
|
break;
|
|
|
|
}
|
2010-08-19 01:12:56 +08:00
|
|
|
if (status & DP_AUX_CH_CTL_DONE)
|
2009-04-08 07:16:42 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((status & DP_AUX_CH_CTL_DONE) == 0) {
|
2009-06-29 06:42:17 +08:00
|
|
|
DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
ret = -EBUSY;
|
|
|
|
goto out;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Check for timeout or receive error.
|
|
|
|
* Timeouts occur when the sink is not connected
|
|
|
|
*/
|
2009-06-12 13:30:32 +08:00
|
|
|
if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
|
2009-06-29 06:42:17 +08:00
|
|
|
DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
ret = -EIO;
|
|
|
|
goto out;
|
2009-06-12 13:30:32 +08:00
|
|
|
}
|
2009-06-29 06:42:17 +08:00
|
|
|
|
|
|
|
/* Timeouts occur when the device isn't connected, so they're
|
|
|
|
* "normal" -- don't fill the kernel log with these */
|
2009-06-12 13:30:32 +08:00
|
|
|
if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
|
2009-10-09 11:39:41 +08:00
|
|
|
DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
ret = -ETIMEDOUT;
|
|
|
|
goto out;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Unload any bytes sent back from the other side */
|
|
|
|
recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
|
|
|
|
DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
|
|
|
|
if (recv_bytes > recv_size)
|
|
|
|
recv_bytes = recv_size;
|
2011-08-17 03:34:10 +08:00
|
|
|
|
2010-08-19 01:12:56 +08:00
|
|
|
for (i = 0; i < recv_bytes; i += 4)
|
|
|
|
unpack_aux(I915_READ(ch_data + i),
|
|
|
|
recv + i, recv_bytes - i);
|
2009-04-08 07:16:42 +08:00
|
|
|
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
ret = recv_bytes;
|
|
|
|
out:
|
|
|
|
pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
|
2013-08-20 00:18:09 +08:00
|
|
|
intel_aux_display_runtime_put(dev_priv);
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
|
2014-03-14 22:51:14 +08:00
|
|
|
if (vdd)
|
|
|
|
edp_panel_vdd_off(intel_dp, false);
|
|
|
|
|
drm/i915: irq-drive the dp aux communication
At least on the platforms that have a dp aux irq and also have it
enabled - vlvhsw should have one, too. But I don't have a machine to
test this on. Judging from docs there's no dp aux interrupt for gm45.
Also, I only have an ivb cpu edp machine, so the dp aux A code for
snb/ilk is untested.
For dpcd probing when nothing is connected it slashes about 5ms of cpu
time (cpu time is now negligible), which agrees with 3 * 5 400 usec
timeouts.
A previous version of this patch increases the time required to go
through the dp_detect cycle (which includes reading the edid) from
around 33 ms to around 40 ms. Experiments indicated that this is
purely due to the irq latency - the hw doesn't allow us to queue up
dp aux transactions and hence irq latency directly affects throughput.
gmbus is much better, there we have a 8 byte buffer, and we get the
irq once another 4 bytes can be queued up.
But by using the pm_qos interface to request the lowest possible cpu
wake-up latency this slowdown completely disappeared.
Since all our output detection logic is single-threaded with the
mode_config mutex right now anyway, I've decide not ot play fancy and
to just reuse the gmbus wait queue. But this would definitely prep the
way to run dp detection on different ports in parallel
v2: Add a timeout for dp aux transfers when using interrupts - the hw
_does_ prevent this with the hw-based 400 usec timeout, but if the
irq somehow doesn't arrive we're screwed. Lesson learned while
developing this ;-)
v3: While at it also convert the busy-loop to wait_for_atomic, so that
we don't run the risk of an infinite loop any more.
v4: Ensure we have the smallest possible irq latency by using the
pm_qos interface.
v5: Add a comment to the code to explain why we frob pm_qos. Suggested
by Chris Wilson.
v6: Disable dp irq for vlv, that's easier than trying to get at docs
and hw.
v7: Squash in a fix for Haswell that Paulo Zanoni tracked down - the
dp aux registers aren't at a fixed offset any more, but can be on the
PCH while the DP port is on the cpu die.
Reviewed-by: Imre Deak <imre.deak@intel.com> (v6)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-12-01 20:53:48 +08:00
|
|
|
return ret;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
2014-04-07 17:37:25 +08:00
|
|
|
#define BARE_ADDRESS_SIZE 3
|
|
|
|
#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
|
2014-03-14 22:51:15 +08:00
|
|
|
static ssize_t
|
|
|
|
intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2014-03-14 22:51:15 +08:00
|
|
|
struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
|
|
|
|
uint8_t txbuf[20], rxbuf[20];
|
|
|
|
size_t txsize, rxsize;
|
2009-04-08 07:16:42 +08:00
|
|
|
int ret;
|
|
|
|
|
2014-03-14 22:51:15 +08:00
|
|
|
txbuf[0] = msg->request << 4;
|
|
|
|
txbuf[1] = msg->address >> 8;
|
|
|
|
txbuf[2] = msg->address & 0xff;
|
|
|
|
txbuf[3] = msg->size - 1;
|
2013-09-17 22:14:10 +08:00
|
|
|
|
2014-03-14 22:51:15 +08:00
|
|
|
switch (msg->request & ~DP_AUX_I2C_MOT) {
|
|
|
|
case DP_AUX_NATIVE_WRITE:
|
|
|
|
case DP_AUX_I2C_WRITE:
|
2014-04-07 17:37:25 +08:00
|
|
|
txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
|
2014-03-14 22:51:15 +08:00
|
|
|
rxsize = 1;
|
2014-02-11 17:52:05 +08:00
|
|
|
|
2014-03-14 22:51:15 +08:00
|
|
|
if (WARN_ON(txsize > 20))
|
|
|
|
return -E2BIG;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2014-03-14 22:51:15 +08:00
|
|
|
memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2014-03-14 22:51:15 +08:00
|
|
|
ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
|
|
|
|
if (ret > 0) {
|
|
|
|
msg->reply = rxbuf[0] >> 4;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2014-03-14 22:51:15 +08:00
|
|
|
/* Return payload size. */
|
|
|
|
ret = msg->size;
|
|
|
|
}
|
|
|
|
break;
|
2013-09-17 22:14:10 +08:00
|
|
|
|
2014-03-14 22:51:15 +08:00
|
|
|
case DP_AUX_NATIVE_READ:
|
|
|
|
case DP_AUX_I2C_READ:
|
2014-04-07 17:37:25 +08:00
|
|
|
txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
|
2014-03-14 22:51:15 +08:00
|
|
|
rxsize = msg->size + 1;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2014-03-14 22:51:15 +08:00
|
|
|
if (WARN_ON(rxsize > 20))
|
|
|
|
return -E2BIG;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2014-03-14 22:51:15 +08:00
|
|
|
ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
|
|
|
|
if (ret > 0) {
|
|
|
|
msg->reply = rxbuf[0] >> 4;
|
|
|
|
/*
|
|
|
|
* Assume happy day, and copy the data. The caller is
|
|
|
|
* expected to check msg->reply before touching it.
|
|
|
|
*
|
|
|
|
* Return payload size.
|
|
|
|
*/
|
|
|
|
ret--;
|
|
|
|
memcpy(msg->buffer, rxbuf + 1, ret);
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
2014-03-14 22:51:15 +08:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
ret = -EINVAL;
|
|
|
|
break;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
2014-02-11 17:52:05 +08:00
|
|
|
|
2014-03-14 22:51:15 +08:00
|
|
|
return ret;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
2014-03-14 22:51:15 +08:00
|
|
|
static void
|
|
|
|
intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2014-03-14 22:51:16 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
enum port port = intel_dig_port->port;
|
2014-03-14 22:51:17 +08:00
|
|
|
const char *name = NULL;
|
2009-12-04 08:55:24 +08:00
|
|
|
int ret;
|
|
|
|
|
2014-03-14 22:51:16 +08:00
|
|
|
switch (port) {
|
|
|
|
case PORT_A:
|
|
|
|
intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
|
2014-03-14 22:51:17 +08:00
|
|
|
name = "DPDDC-A";
|
2009-12-04 08:55:24 +08:00
|
|
|
break;
|
2014-03-14 22:51:16 +08:00
|
|
|
case PORT_B:
|
|
|
|
intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
|
2014-03-14 22:51:17 +08:00
|
|
|
name = "DPDDC-B";
|
2009-12-04 08:55:24 +08:00
|
|
|
break;
|
2014-03-14 22:51:16 +08:00
|
|
|
case PORT_C:
|
|
|
|
intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
|
2014-03-14 22:51:17 +08:00
|
|
|
name = "DPDDC-C";
|
2009-12-04 08:55:24 +08:00
|
|
|
break;
|
2014-03-14 22:51:16 +08:00
|
|
|
case PORT_D:
|
|
|
|
intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
|
2014-03-14 22:51:17 +08:00
|
|
|
name = "DPDDC-D";
|
2014-03-14 22:51:16 +08:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
BUG();
|
2009-12-04 08:55:24 +08:00
|
|
|
}
|
|
|
|
|
2014-03-14 22:51:16 +08:00
|
|
|
if (!HAS_DDI(dev))
|
|
|
|
intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
|
2010-12-09 00:10:21 +08:00
|
|
|
|
2014-03-14 22:51:17 +08:00
|
|
|
intel_dp->aux.name = name;
|
2014-03-14 22:51:15 +08:00
|
|
|
intel_dp->aux.dev = dev->dev;
|
|
|
|
intel_dp->aux.transfer = intel_dp_aux_transfer;
|
2010-12-09 00:10:21 +08:00
|
|
|
|
2014-03-14 22:51:17 +08:00
|
|
|
DRM_DEBUG_KMS("registering %s bus for %s\n", name,
|
|
|
|
connector->base.kdev->kobj.name);
|
2010-12-09 00:10:21 +08:00
|
|
|
|
2014-06-04 14:02:28 +08:00
|
|
|
ret = drm_dp_aux_register(&intel_dp->aux);
|
2014-03-14 22:51:17 +08:00
|
|
|
if (ret < 0) {
|
2014-06-04 14:02:28 +08:00
|
|
|
DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
|
2014-03-14 22:51:17 +08:00
|
|
|
name, ret);
|
|
|
|
return;
|
2009-12-04 08:55:24 +08:00
|
|
|
}
|
2013-10-31 05:50:26 +08:00
|
|
|
|
2014-03-14 22:51:17 +08:00
|
|
|
ret = sysfs_create_link(&connector->base.kdev->kobj,
|
|
|
|
&intel_dp->aux.ddc.dev.kobj,
|
|
|
|
intel_dp->aux.ddc.dev.kobj.name);
|
|
|
|
if (ret < 0) {
|
|
|
|
DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
|
2014-06-04 14:02:28 +08:00
|
|
|
drm_dp_aux_unregister(&intel_dp->aux);
|
2009-12-04 08:55:24 +08:00
|
|
|
}
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
2014-02-11 23:12:49 +08:00
|
|
|
static void
|
|
|
|
intel_dp_connector_unregister(struct intel_connector *intel_connector)
|
|
|
|
{
|
|
|
|
struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
|
|
|
|
|
|
|
|
sysfs_remove_link(&intel_connector->base.kdev->kobj,
|
2014-03-14 22:51:17 +08:00
|
|
|
intel_dp->aux.ddc.dev.kobj.name);
|
2014-02-11 23:12:49 +08:00
|
|
|
intel_connector_unregister(intel_connector);
|
|
|
|
}
|
|
|
|
|
2013-04-19 17:14:33 +08:00
|
|
|
static void
|
|
|
|
intel_dp_set_clock(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_config *pipe_config, int link_bw)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = encoder->base.dev;
|
2013-09-04 01:30:37 +08:00
|
|
|
const struct dp_link_dpll *divisor = NULL;
|
|
|
|
int i, count = 0;
|
2013-04-19 17:14:33 +08:00
|
|
|
|
|
|
|
if (IS_G4X(dev)) {
|
2013-09-04 01:30:37 +08:00
|
|
|
divisor = gen4_dpll;
|
|
|
|
count = ARRAY_SIZE(gen4_dpll);
|
2013-04-19 17:14:33 +08:00
|
|
|
} else if (IS_HASWELL(dev)) {
|
|
|
|
/* Haswell has special-purpose DP DDI clocks. */
|
|
|
|
} else if (HAS_PCH_SPLIT(dev)) {
|
2013-09-04 01:30:37 +08:00
|
|
|
divisor = pch_dpll;
|
|
|
|
count = ARRAY_SIZE(pch_dpll);
|
2014-04-09 18:28:18 +08:00
|
|
|
} else if (IS_CHERRYVIEW(dev)) {
|
|
|
|
divisor = chv_dpll;
|
|
|
|
count = ARRAY_SIZE(chv_dpll);
|
2013-04-19 17:14:33 +08:00
|
|
|
} else if (IS_VALLEYVIEW(dev)) {
|
2013-09-04 01:30:38 +08:00
|
|
|
divisor = vlv_dpll;
|
|
|
|
count = ARRAY_SIZE(vlv_dpll);
|
2013-04-19 17:14:33 +08:00
|
|
|
}
|
2013-09-04 01:30:37 +08:00
|
|
|
|
|
|
|
if (divisor && count) {
|
|
|
|
for (i = 0; i < count; i++) {
|
|
|
|
if (link_bw == divisor[i].link_bw) {
|
|
|
|
pipe_config->dpll = divisor[i].dpll;
|
|
|
|
pipe_config->clock_set = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2013-04-19 17:14:33 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-04-05 14:43:28 +08:00
|
|
|
static void
|
|
|
|
intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
enum transcoder transcoder = crtc->config.cpu_transcoder;
|
|
|
|
|
|
|
|
I915_WRITE(PIPE_DATA_M2(transcoder),
|
|
|
|
TU_SIZE(m_n->tu) | m_n->gmch_m);
|
|
|
|
I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
|
|
|
|
I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
|
|
|
|
I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
|
|
|
|
}
|
|
|
|
|
2012-10-27 05:05:52 +08:00
|
|
|
bool
|
2013-03-27 07:44:55 +08:00
|
|
|
intel_dp_compute_config(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_config *pipe_config)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2013-03-27 07:44:55 +08:00
|
|
|
struct drm_device *dev = encoder->base.dev;
|
2013-03-27 07:44:59 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-03-27 07:44:55 +08:00
|
|
|
struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
|
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
2013-05-16 19:40:36 +08:00
|
|
|
enum port port = dp_to_dig_port(intel_dp)->port;
|
2013-04-26 03:55:01 +08:00
|
|
|
struct intel_crtc *intel_crtc = encoder->new_crtc;
|
2012-10-19 19:51:50 +08:00
|
|
|
struct intel_connector *intel_connector = intel_dp->attached_connector;
|
2009-04-08 07:16:42 +08:00
|
|
|
int lane_count, clock;
|
2014-05-06 19:56:52 +08:00
|
|
|
int min_lane_count = 1;
|
2014-05-06 19:56:50 +08:00
|
|
|
int max_lane_count = intel_dp_max_lane_count(intel_dp);
|
2014-01-21 01:19:39 +08:00
|
|
|
/* Conveniently, the link BW constants become indices with a shift...*/
|
2014-05-06 19:56:52 +08:00
|
|
|
int min_clock = 0;
|
2014-01-21 01:19:39 +08:00
|
|
|
int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
|
2012-04-21 02:23:49 +08:00
|
|
|
int bpp, mode_rate;
|
2014-01-21 01:19:39 +08:00
|
|
|
static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
|
2013-06-01 23:16:21 +08:00
|
|
|
int link_avail, link_clock;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2013-05-16 19:40:36 +08:00
|
|
|
if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
|
2013-03-27 07:44:55 +08:00
|
|
|
pipe_config->has_pch_encoder = true;
|
|
|
|
|
2013-04-03 05:42:31 +08:00
|
|
|
pipe_config->has_dp_encoder = true;
|
2014-04-25 05:54:52 +08:00
|
|
|
pipe_config->has_audio = intel_dp->has_audio;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2012-10-19 19:51:50 +08:00
|
|
|
if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
|
|
|
|
intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
|
|
|
|
adjusted_mode);
|
2013-04-26 03:55:01 +08:00
|
|
|
if (!HAS_PCH_SPLIT(dev))
|
|
|
|
intel_gmch_panel_fitting(intel_crtc, pipe_config,
|
|
|
|
intel_connector->panel.fitting_mode);
|
|
|
|
else
|
2013-04-26 03:55:02 +08:00
|
|
|
intel_pch_panel_fitting(intel_crtc, pipe_config,
|
|
|
|
intel_connector->panel.fitting_mode);
|
2010-07-19 16:43:13 +08:00
|
|
|
}
|
|
|
|
|
2012-06-05 00:39:21 +08:00
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
|
2012-05-23 17:30:55 +08:00
|
|
|
return false;
|
|
|
|
|
2012-04-21 02:23:49 +08:00
|
|
|
DRM_DEBUG_KMS("DP link computation with max lane count %i "
|
|
|
|
"max bw %02x pixel clock %iKHz\n",
|
2013-09-25 23:45:37 +08:00
|
|
|
max_lane_count, bws[max_clock],
|
|
|
|
adjusted_mode->crtc_clock);
|
2012-04-21 02:23:49 +08:00
|
|
|
|
2013-03-27 07:44:59 +08:00
|
|
|
/* Walk through all bpp values. Luckily they're all nicely spaced with 2
|
|
|
|
* bpc in between. */
|
2013-06-02 01:45:56 +08:00
|
|
|
bpp = pipe_config->pipe_bpp;
|
2014-05-06 19:56:52 +08:00
|
|
|
if (is_edp(intel_dp)) {
|
|
|
|
if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
|
|
|
|
DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
|
|
|
|
dev_priv->vbt.edp_bpp);
|
|
|
|
bpp = dev_priv->vbt.edp_bpp;
|
|
|
|
}
|
|
|
|
|
2014-05-14 18:02:19 +08:00
|
|
|
if (IS_BROADWELL(dev)) {
|
|
|
|
/* Yes, it's an ugly hack. */
|
|
|
|
min_lane_count = max_lane_count;
|
|
|
|
DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
|
|
|
|
min_lane_count);
|
|
|
|
} else if (dev_priv->vbt.edp_lanes) {
|
2014-05-06 19:56:52 +08:00
|
|
|
min_lane_count = min(dev_priv->vbt.edp_lanes,
|
|
|
|
max_lane_count);
|
|
|
|
DRM_DEBUG_KMS("using min %u lanes per VBT\n",
|
|
|
|
min_lane_count);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dev_priv->vbt.edp_rate) {
|
|
|
|
min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
|
|
|
|
DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
|
|
|
|
bws[min_clock]);
|
|
|
|
}
|
2013-07-18 22:44:13 +08:00
|
|
|
}
|
2013-05-04 16:09:18 +08:00
|
|
|
|
2013-03-27 07:44:59 +08:00
|
|
|
for (; bpp >= 6*3; bpp -= 2*3) {
|
2013-09-25 23:45:37 +08:00
|
|
|
mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
|
|
|
|
bpp);
|
2013-03-27 07:44:59 +08:00
|
|
|
|
2014-05-06 19:56:52 +08:00
|
|
|
for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
|
|
|
|
for (clock = min_clock; clock <= max_clock; clock++) {
|
2013-03-27 07:44:59 +08:00
|
|
|
link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
|
|
|
|
link_avail = intel_dp_max_data_rate(link_clock,
|
|
|
|
lane_count);
|
|
|
|
|
|
|
|
if (mode_rate <= link_avail) {
|
|
|
|
goto found;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2012-04-10 16:42:36 +08:00
|
|
|
|
2013-03-27 07:44:59 +08:00
|
|
|
return false;
|
2013-01-17 22:31:28 +08:00
|
|
|
|
2013-03-27 07:44:59 +08:00
|
|
|
found:
|
2013-01-17 22:31:29 +08:00
|
|
|
if (intel_dp->color_range_auto) {
|
|
|
|
/*
|
|
|
|
* See:
|
|
|
|
* CEA-861-E - 5.1 Default Encoding Parameters
|
|
|
|
* VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
|
|
|
|
*/
|
2012-12-20 22:41:44 +08:00
|
|
|
if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
|
2013-01-17 22:31:29 +08:00
|
|
|
intel_dp->color_range = DP_COLOR_RANGE_16_235;
|
|
|
|
else
|
|
|
|
intel_dp->color_range = 0;
|
|
|
|
}
|
|
|
|
|
2013-01-17 22:31:28 +08:00
|
|
|
if (intel_dp->color_range)
|
2013-03-27 07:44:56 +08:00
|
|
|
pipe_config->limited_color_range = true;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2013-03-27 07:44:59 +08:00
|
|
|
intel_dp->link_bw = bws[clock];
|
|
|
|
intel_dp->lane_count = lane_count;
|
2013-05-04 16:09:18 +08:00
|
|
|
pipe_config->pipe_bpp = bpp;
|
2013-06-01 23:16:21 +08:00
|
|
|
pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2013-03-27 07:44:59 +08:00
|
|
|
DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
|
|
|
|
intel_dp->link_bw, intel_dp->lane_count,
|
2013-06-01 23:16:21 +08:00
|
|
|
pipe_config->port_clock, bpp);
|
2013-03-27 07:44:59 +08:00
|
|
|
DRM_DEBUG_KMS("DP link bw required %i available %i\n",
|
|
|
|
mode_rate, link_avail);
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2013-04-03 05:42:31 +08:00
|
|
|
intel_link_compute_m_n(bpp, lane_count,
|
2013-09-25 23:45:37 +08:00
|
|
|
adjusted_mode->crtc_clock,
|
|
|
|
pipe_config->port_clock,
|
2013-04-03 05:42:31 +08:00
|
|
|
&pipe_config->dp_m_n);
|
2013-03-18 18:25:36 +08:00
|
|
|
|
2014-04-05 14:43:28 +08:00
|
|
|
if (intel_connector->panel.downclock_mode != NULL &&
|
|
|
|
intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
|
|
|
|
intel_link_compute_m_n(bpp, lane_count,
|
|
|
|
intel_connector->panel.downclock_mode->clock,
|
|
|
|
pipe_config->port_clock,
|
|
|
|
&pipe_config->dp_m2_n2);
|
|
|
|
}
|
|
|
|
|
2013-04-19 17:14:33 +08:00
|
|
|
intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
|
|
|
|
|
2013-04-03 05:42:31 +08:00
|
|
|
return true;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
2013-06-01 23:16:20 +08:00
|
|
|
static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
|
2012-11-29 22:59:31 +08:00
|
|
|
{
|
2013-06-01 23:16:20 +08:00
|
|
|
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
|
|
|
|
struct drm_device *dev = crtc->base.dev;
|
2012-11-29 22:59:31 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 dpa_ctl;
|
|
|
|
|
2013-06-01 23:16:21 +08:00
|
|
|
DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
|
2012-11-29 22:59:31 +08:00
|
|
|
dpa_ctl = I915_READ(DP_A);
|
|
|
|
dpa_ctl &= ~DP_PLL_FREQ_MASK;
|
|
|
|
|
2013-06-01 23:16:21 +08:00
|
|
|
if (crtc->config.port_clock == 162000) {
|
2012-11-29 22:59:32 +08:00
|
|
|
/* For a long time we've carried around a ILK-DevA w/a for the
|
|
|
|
* 160MHz clock. If we're really unlucky, it's still required.
|
|
|
|
*/
|
|
|
|
DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
|
2012-11-29 22:59:31 +08:00
|
|
|
dpa_ctl |= DP_PLL_FREQ_160MHZ;
|
2013-06-01 23:16:20 +08:00
|
|
|
intel_dp->DP |= DP_PLL_FREQ_160MHZ;
|
2012-11-29 22:59:31 +08:00
|
|
|
} else {
|
|
|
|
dpa_ctl |= DP_PLL_FREQ_270MHZ;
|
2013-06-01 23:16:20 +08:00
|
|
|
intel_dp->DP |= DP_PLL_FREQ_270MHZ;
|
2012-11-29 22:59:31 +08:00
|
|
|
}
|
2012-11-29 22:59:32 +08:00
|
|
|
|
2012-11-29 22:59:31 +08:00
|
|
|
I915_WRITE(DP_A, dpa_ctl);
|
|
|
|
|
|
|
|
POSTING_READ(DP_A);
|
|
|
|
udelay(500);
|
|
|
|
}
|
|
|
|
|
2014-04-25 05:54:54 +08:00
|
|
|
static void intel_dp_prepare(struct intel_encoder *encoder)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2013-07-22 03:37:05 +08:00
|
|
|
struct drm_device *dev = encoder->base.dev;
|
2011-11-02 10:54:11 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-07-22 03:37:05 +08:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
2013-05-16 19:40:36 +08:00
|
|
|
enum port port = dp_to_dig_port(intel_dp)->port;
|
2013-07-22 03:37:05 +08:00
|
|
|
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
|
|
|
|
struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2011-11-02 10:54:11 +08:00
|
|
|
/*
|
2011-11-17 08:26:07 +08:00
|
|
|
* There are four kinds of DP registers:
|
2011-11-02 10:54:11 +08:00
|
|
|
*
|
|
|
|
* IBX PCH
|
2011-11-17 08:26:07 +08:00
|
|
|
* SNB CPU
|
|
|
|
* IVB CPU
|
2011-11-02 10:54:11 +08:00
|
|
|
* CPT PCH
|
|
|
|
*
|
|
|
|
* IBX PCH and CPU are the same for almost everything,
|
|
|
|
* except that the CPU DP PLL is configured in this
|
|
|
|
* register
|
|
|
|
*
|
|
|
|
* CPT PCH is quite different, having many bits moved
|
|
|
|
* to the TRANS_DP_CTL register instead. That
|
|
|
|
* configuration happens (oddly) in ironlake_pch_enable
|
|
|
|
*/
|
2010-04-06 05:57:59 +08:00
|
|
|
|
2011-11-02 10:54:11 +08:00
|
|
|
/* Preserve the BIOS-computed detected bit. This is
|
|
|
|
* supposed to be read-only.
|
|
|
|
*/
|
|
|
|
intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2011-11-02 10:54:11 +08:00
|
|
|
/* Handle DP bits in common between all three register formats */
|
|
|
|
intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
|
2013-04-30 20:01:40 +08:00
|
|
|
intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2014-04-25 05:54:52 +08:00
|
|
|
if (crtc->config.has_audio) {
|
drm/i915: pass ELD to HDMI/DP audio driver
Add ELD support for Intel Eaglelake, IbexPeak/Ironlake,
SandyBridge/CougarPoint and IvyBridge/PantherPoint chips.
ELD (EDID-Like Data) describes to the HDMI/DP audio driver the audio
capabilities of the plugged monitor. It's built and passed to audio
driver in 2 steps:
(1) at get_modes time, parse EDID and save ELD to drm_connector.eld[]
(2) at mode_set time, write drm_connector.eld[] to the Transcoder's hw
ELD buffer and set the ELD_valid bit to inform HDMI/DP audio driver
This patch is tested OK on G45/HDMI, IbexPeak/HDMI and IvyBridge/HDMI+DP.
Test scheme: plug in the HDMI/DP monitor, and run
cat /proc/asound/card0/eld*
to check if the monitor name, HDMI/DP type, etc. show up correctly.
Minor imperfection: the GEN5_AUD_CNTL_ST/DIP_Port_Select field always
reads 0 (reserved). Without knowing the port number, I worked it around
by setting the ELD_valid bit for ALL the three ports. It's tested to not
be a problem, because the audio driver will find invalid ELD data and
hence rightfully abort, even when it sees the ELD_valid indicator.
Thanks to Zhenyu and Pierre-Louis for a lot of valuable help and testing.
CC: Zhao Yakui <yakui.zhao@intel.com>
CC: Wang Zhenyu <zhenyu.z.wang@intel.com>
CC: Jeremy Bush <contractfrombelow@gmail.com>
CC: Christopher White <c.white@pulseforce.com>
CC: Pierre-Louis Bossart <pierre-louis.bossart@intel.com>
CC: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Wu Fengguang <fengguang.wu@intel.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-09-05 14:25:34 +08:00
|
|
|
DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
|
2013-06-01 23:16:20 +08:00
|
|
|
pipe_name(crtc->pipe));
|
2010-08-04 20:50:23 +08:00
|
|
|
intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
|
2013-07-22 03:37:05 +08:00
|
|
|
intel_write_eld(&encoder->base, adjusted_mode);
|
drm/i915: pass ELD to HDMI/DP audio driver
Add ELD support for Intel Eaglelake, IbexPeak/Ironlake,
SandyBridge/CougarPoint and IvyBridge/PantherPoint chips.
ELD (EDID-Like Data) describes to the HDMI/DP audio driver the audio
capabilities of the plugged monitor. It's built and passed to audio
driver in 2 steps:
(1) at get_modes time, parse EDID and save ELD to drm_connector.eld[]
(2) at mode_set time, write drm_connector.eld[] to the Transcoder's hw
ELD buffer and set the ELD_valid bit to inform HDMI/DP audio driver
This patch is tested OK on G45/HDMI, IbexPeak/HDMI and IvyBridge/HDMI+DP.
Test scheme: plug in the HDMI/DP monitor, and run
cat /proc/asound/card0/eld*
to check if the monitor name, HDMI/DP type, etc. show up correctly.
Minor imperfection: the GEN5_AUD_CNTL_ST/DIP_Port_Select field always
reads 0 (reserved). Without knowing the port number, I worked it around
by setting the ELD_valid bit for ALL the three ports. It's tested to not
be a problem, because the audio driver will find invalid ELD data and
hence rightfully abort, even when it sees the ELD_valid indicator.
Thanks to Zhenyu and Pierre-Louis for a lot of valuable help and testing.
CC: Zhao Yakui <yakui.zhao@intel.com>
CC: Wang Zhenyu <zhenyu.z.wang@intel.com>
CC: Jeremy Bush <contractfrombelow@gmail.com>
CC: Christopher White <c.white@pulseforce.com>
CC: Pierre-Louis Bossart <pierre-louis.bossart@intel.com>
CC: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Wu Fengguang <fengguang.wu@intel.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-09-05 14:25:34 +08:00
|
|
|
}
|
2012-10-16 02:51:33 +08:00
|
|
|
|
2011-11-02 10:54:11 +08:00
|
|
|
/* Split out the IBX/CPU vs CPT settings */
|
2009-07-24 01:00:32 +08:00
|
|
|
|
2013-05-16 19:40:36 +08:00
|
|
|
if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
|
2011-11-17 08:26:07 +08:00
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
|
|
|
|
intel_dp->DP |= DP_SYNC_HS_HIGH;
|
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
|
|
|
|
intel_dp->DP |= DP_SYNC_VS_HIGH;
|
|
|
|
intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
|
|
|
|
|
2013-10-04 20:08:10 +08:00
|
|
|
if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
|
2011-11-17 08:26:07 +08:00
|
|
|
intel_dp->DP |= DP_ENHANCED_FRAMING;
|
|
|
|
|
2013-06-01 23:16:20 +08:00
|
|
|
intel_dp->DP |= crtc->pipe << 29;
|
2013-05-16 19:40:36 +08:00
|
|
|
} else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
|
2013-03-29 00:55:40 +08:00
|
|
|
if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
|
2013-01-17 22:31:28 +08:00
|
|
|
intel_dp->DP |= intel_dp->color_range;
|
2011-11-02 10:54:11 +08:00
|
|
|
|
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
|
|
|
|
intel_dp->DP |= DP_SYNC_HS_HIGH;
|
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
|
|
|
|
intel_dp->DP |= DP_SYNC_VS_HIGH;
|
|
|
|
intel_dp->DP |= DP_LINK_TRAIN_OFF;
|
|
|
|
|
2013-10-04 20:08:10 +08:00
|
|
|
if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
|
2011-11-02 10:54:11 +08:00
|
|
|
intel_dp->DP |= DP_ENHANCED_FRAMING;
|
|
|
|
|
2014-04-09 18:28:21 +08:00
|
|
|
if (!IS_CHERRYVIEW(dev)) {
|
|
|
|
if (crtc->pipe == 1)
|
|
|
|
intel_dp->DP |= DP_PIPEB_SELECT;
|
|
|
|
} else {
|
|
|
|
intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
|
|
|
|
}
|
2011-11-02 10:54:11 +08:00
|
|
|
} else {
|
|
|
|
intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
|
2009-07-24 01:00:32 +08:00
|
|
|
}
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
2013-12-20 00:29:42 +08:00
|
|
|
#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
|
|
|
|
#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
|
2011-11-02 10:57:50 +08:00
|
|
|
|
drm/i915: don't wait for power cycle when waiting for power off
Function ironlake_wait_panel_off should just wait for the power off
delay, while function ironlake_wait_panel_power_cycle should wait for
the panel cycle (that's required after we turn the panel off, before
we enable it again).
The problem is that, currently, ironlake_wait_panel_off is waiting not
just for the panel to be off, but also for the power cycle delay and
the backlight off delay. This function relies on the PP_STATUS bits
3:0, which are not documented and not supposed to be used. A quick
analysis of the values we get while waiting quickly shows that power
off is reached while bits 3:0 are still 0x1, and the time it takes to
become 0x0 is the power cycle delay.
On my system with backlight off delay of 200ms, power down delay of
50ms and power cycle delay of 500ms, this is what I get:
- Start waiting with value 0x80000008, timestamp 6.429364.
- Jumps to 0xa0000003, timestamp 6.431360 (time waited: 0.001996)
- Jumps to 0xa0000002, timestamp 6.631277 (time waited: 0.201913)
- Jumps to 0x08000001, timestamp 6.681258 (time waited: 0.251894)
- Jumps to 0x00000000, timestamp 7.192012 (time waited: 0.762648)
As you can see, ironlake_wait_panel_off is sleeping 760ms instead of
the expected 50ms: the first 200ms matches the backlight off delay
(which we should already have waited for!), then the 50ms for the real
panel off delay, then the 500ms for the panel power cycle.
This patch makes is look just at bits 31 and 29:28, which will ignore
the panel power cycle.
And just to be clear: this saves 500ms on my system every time we
disable the panel. But we can still save 200ms more (the backlight off
delay) on the next patches.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuougseek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-12-20 00:29:43 +08:00
|
|
|
#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
|
|
|
|
#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
|
2011-11-02 10:57:50 +08:00
|
|
|
|
2013-12-20 00:29:42 +08:00
|
|
|
#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
|
|
|
|
#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
|
2011-11-02 10:57:50 +08:00
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
static void wait_panel_status(struct intel_dp *intel_dp,
|
2011-11-02 10:57:50 +08:00
|
|
|
u32 mask,
|
|
|
|
u32 value)
|
2011-09-19 14:09:52 +08:00
|
|
|
{
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2011-11-02 10:57:50 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-03-29 00:55:41 +08:00
|
|
|
u32 pp_stat_reg, pp_ctrl_reg;
|
|
|
|
|
2013-09-06 12:40:05 +08:00
|
|
|
pp_stat_reg = _pp_stat_reg(intel_dp);
|
|
|
|
pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
|
2011-09-30 07:51:26 +08:00
|
|
|
|
2011-11-02 10:57:50 +08:00
|
|
|
DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
|
2013-03-29 00:55:41 +08:00
|
|
|
mask, value,
|
|
|
|
I915_READ(pp_stat_reg),
|
|
|
|
I915_READ(pp_ctrl_reg));
|
2011-09-30 07:51:26 +08:00
|
|
|
|
2013-03-29 00:55:41 +08:00
|
|
|
if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
|
2011-11-02 10:57:50 +08:00
|
|
|
DRM_ERROR("Panel status timeout: status %08x control %08x\n",
|
2013-03-29 00:55:41 +08:00
|
|
|
I915_READ(pp_stat_reg),
|
|
|
|
I915_READ(pp_ctrl_reg));
|
2011-09-30 07:51:26 +08:00
|
|
|
}
|
2013-12-02 17:57:16 +08:00
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Wait complete\n");
|
2011-11-02 10:57:50 +08:00
|
|
|
}
|
2011-09-30 07:51:26 +08:00
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
static void wait_panel_on(struct intel_dp *intel_dp)
|
2011-11-02 10:57:50 +08:00
|
|
|
{
|
|
|
|
DRM_DEBUG_KMS("Wait for panel power on\n");
|
2014-01-17 21:39:48 +08:00
|
|
|
wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
|
2011-09-19 14:09:52 +08:00
|
|
|
}
|
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
static void wait_panel_off(struct intel_dp *intel_dp)
|
2011-11-02 10:57:50 +08:00
|
|
|
{
|
|
|
|
DRM_DEBUG_KMS("Wait for panel power off time\n");
|
2014-01-17 21:39:48 +08:00
|
|
|
wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
|
2011-11-02 10:57:50 +08:00
|
|
|
}
|
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
static void wait_panel_power_cycle(struct intel_dp *intel_dp)
|
2011-11-02 10:57:50 +08:00
|
|
|
{
|
|
|
|
DRM_DEBUG_KMS("Wait for panel power cycle\n");
|
2013-12-20 00:29:40 +08:00
|
|
|
|
|
|
|
/* When we disable the VDD override bit last we have to do the manual
|
|
|
|
* wait. */
|
|
|
|
wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
|
|
|
|
intel_dp->panel_power_cycle_delay);
|
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
|
2011-11-02 10:57:50 +08:00
|
|
|
}
|
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
static void wait_backlight_on(struct intel_dp *intel_dp)
|
2013-12-20 00:29:40 +08:00
|
|
|
{
|
|
|
|
wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
|
|
|
|
intel_dp->backlight_on_delay);
|
|
|
|
}
|
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
static void edp_wait_backlight_off(struct intel_dp *intel_dp)
|
2013-12-20 00:29:40 +08:00
|
|
|
{
|
|
|
|
wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
|
|
|
|
intel_dp->backlight_off_delay);
|
|
|
|
}
|
2011-11-02 10:57:50 +08:00
|
|
|
|
2011-11-02 10:34:06 +08:00
|
|
|
/* Read the current pp_control value, unlocking the register if it
|
|
|
|
* is locked
|
|
|
|
*/
|
|
|
|
|
2013-03-29 00:55:41 +08:00
|
|
|
static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
|
2011-11-02 10:34:06 +08:00
|
|
|
{
|
2013-03-29 00:55:41 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 control;
|
2011-11-02 10:34:06 +08:00
|
|
|
|
2013-09-06 12:40:05 +08:00
|
|
|
control = I915_READ(_pp_ctrl_reg(intel_dp));
|
2011-11-02 10:34:06 +08:00
|
|
|
control &= ~PANEL_UNLOCK_MASK;
|
|
|
|
control |= PANEL_UNLOCK_REGS;
|
|
|
|
return control;
|
2011-09-19 14:09:52 +08:00
|
|
|
}
|
|
|
|
|
2014-03-14 22:51:13 +08:00
|
|
|
static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
|
2011-01-25 09:10:54 +08:00
|
|
|
{
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2014-03-27 23:45:11 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct intel_encoder *intel_encoder = &intel_dig_port->base;
|
2011-01-25 09:10:54 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2014-03-27 23:45:11 +08:00
|
|
|
enum intel_display_power_domain power_domain;
|
2011-01-25 09:10:54 +08:00
|
|
|
u32 pp;
|
2013-03-29 00:55:41 +08:00
|
|
|
u32 pp_stat_reg, pp_ctrl_reg;
|
2014-03-14 22:51:13 +08:00
|
|
|
bool need_to_disable = !intel_dp->want_panel_vdd;
|
2011-01-25 09:10:54 +08:00
|
|
|
|
2011-09-29 07:23:51 +08:00
|
|
|
if (!is_edp(intel_dp))
|
2014-03-14 22:51:13 +08:00
|
|
|
return false;
|
2011-09-19 14:09:52 +08:00
|
|
|
|
|
|
|
intel_dp->want_panel_vdd = true;
|
2011-11-02 10:57:50 +08:00
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
if (edp_have_panel_vdd(intel_dp))
|
2014-03-14 22:51:13 +08:00
|
|
|
return need_to_disable;
|
2013-10-31 05:50:27 +08:00
|
|
|
|
2014-03-27 23:45:11 +08:00
|
|
|
power_domain = intel_display_port_power_domain(intel_encoder);
|
|
|
|
intel_display_power_get(dev_priv, power_domain);
|
2013-11-21 23:47:23 +08:00
|
|
|
|
2013-10-31 05:50:27 +08:00
|
|
|
DRM_DEBUG_KMS("Turning eDP VDD on\n");
|
2011-09-19 14:09:52 +08:00
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
if (!edp_have_panel_power(intel_dp))
|
|
|
|
wait_panel_power_cycle(intel_dp);
|
2011-11-02 10:57:50 +08:00
|
|
|
|
2013-03-29 00:55:41 +08:00
|
|
|
pp = ironlake_get_pp_control(intel_dp);
|
2011-01-25 09:10:54 +08:00
|
|
|
pp |= EDP_FORCE_VDD;
|
2011-09-30 06:53:27 +08:00
|
|
|
|
2013-09-06 12:40:05 +08:00
|
|
|
pp_stat_reg = _pp_stat_reg(intel_dp);
|
|
|
|
pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
|
2013-03-29 00:55:41 +08:00
|
|
|
|
|
|
|
I915_WRITE(pp_ctrl_reg, pp);
|
|
|
|
POSTING_READ(pp_ctrl_reg);
|
|
|
|
DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
|
|
|
|
I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
|
2011-09-30 06:53:27 +08:00
|
|
|
/*
|
|
|
|
* If the panel wasn't on, delay before accessing aux channel
|
|
|
|
*/
|
2014-01-17 21:39:48 +08:00
|
|
|
if (!edp_have_panel_power(intel_dp)) {
|
2011-09-19 14:09:52 +08:00
|
|
|
DRM_DEBUG_KMS("eDP was not running\n");
|
drm/i915: Correct eDP panel power sequencing delay computations
Store the panel power sequencing delays in the dp private structure,
rather than the global device structure. Who knows, maybe we'll get
more than one eDP device in the future.
From the eDP spec, we need the following numbers:
T1 + T3 Power on to Aux Channel operation (panel_power_up_delay)
This marks how long it takes the panel to boot up and
get ready to receive aux channel communications.
T8 Video signal to backlight on (backlight_on_delay)
Once a valid video signal is being sent to the device,
it can take a while before the panel is actuall
showing useful data. This delay allows the panel
to get something reasonable up before the backlight
is turned on.
T9 Backlight off to video off (backlight_off_delay)
Turning the backlight off can take a moment, so
this delay makes sure there is still valid video
data on the screen.
T10 Video off to power off (panel_power_down_delay)
Presumably this delay allows the panel to perform
an orderly shutdown of the display.
T11 + T12 Power off to power on (panel_power_cycle_delay)
So, once you turn the panel off, you have to wait a
while before you can turn it back on. This delay is
usually the longest in the entire sequence.
Neither the VBIOS source code nor the hardware documentation has a
clear mapping between the delay values they provide and those required
by the eDP spec. The VBIOS code actually uses two different labels for
the delay values in the five words of the relevant VBT table.
**** MORE LATER ***
Look at both the current hardware register settings and the VBT
specified panel power sequencing timings. Use the maximum of the two
delays, to make sure things work reliably. If there is no VBT data,
then those values will be initialized to zero, so we'll just use the
values as programmed in the hardware. Note that the BIOS just fetches
delays from the VBT table to place in the hardware registers, so we
should get the same values from both places, except for rounding.
VBT doesn't provide any values for T1 or T2, so we'll always just use
the hardware value for that.
The panel power up delay is thus T1 + T2 + T3, which should be
sufficient in all cases.
The panel power down delay is T1 + T2 + T12, using T1+T2 as a proxy
for T11, which isn't available anywhere.
For the backlight delays, the eDP spec says T6 + T8 is the delay from the
end of link training to backlight on and T9 is the delay from
backlight off until video off. The hardware provides a 'backlight on'
delay, which I'm taking to be T6 + T8 while the VBT provides something
called 'T7', which I'm assuming is s
On the macbook air I'm testing with, this yields a power-up delay of
over 200ms and a power-down delay of over 600ms. It all works now, but
we're frobbing these power controls several times during mode setting,
making the whole process take an awfully long time.
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-09-29 07:48:10 +08:00
|
|
|
msleep(intel_dp->panel_power_up_delay);
|
|
|
|
}
|
2014-03-14 22:51:13 +08:00
|
|
|
|
|
|
|
return need_to_disable;
|
|
|
|
}
|
|
|
|
|
2014-03-19 22:54:37 +08:00
|
|
|
void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
|
2014-03-14 22:51:13 +08:00
|
|
|
{
|
|
|
|
if (is_edp(intel_dp)) {
|
|
|
|
bool vdd = _edp_panel_vdd_on(intel_dp);
|
|
|
|
|
|
|
|
WARN(!vdd, "eDP VDD already requested on\n");
|
|
|
|
}
|
2011-01-25 09:10:54 +08:00
|
|
|
}
|
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
|
2011-01-25 09:10:54 +08:00
|
|
|
{
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2011-01-25 09:10:54 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 pp;
|
2013-03-29 00:55:41 +08:00
|
|
|
u32 pp_stat_reg, pp_ctrl_reg;
|
2011-01-25 09:10:54 +08:00
|
|
|
|
2013-11-20 01:10:12 +08:00
|
|
|
WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
|
2012-12-02 08:05:46 +08:00
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
|
2014-03-27 23:45:11 +08:00
|
|
|
struct intel_digital_port *intel_dig_port =
|
|
|
|
dp_to_dig_port(intel_dp);
|
|
|
|
struct intel_encoder *intel_encoder = &intel_dig_port->base;
|
|
|
|
enum intel_display_power_domain power_domain;
|
|
|
|
|
2013-10-31 05:50:27 +08:00
|
|
|
DRM_DEBUG_KMS("Turning eDP VDD off\n");
|
|
|
|
|
2013-03-29 00:55:41 +08:00
|
|
|
pp = ironlake_get_pp_control(intel_dp);
|
2011-09-19 14:09:52 +08:00
|
|
|
pp &= ~EDP_FORCE_VDD;
|
|
|
|
|
2013-10-31 22:44:21 +08:00
|
|
|
pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
|
|
|
|
pp_stat_reg = _pp_stat_reg(intel_dp);
|
2013-03-29 00:55:41 +08:00
|
|
|
|
|
|
|
I915_WRITE(pp_ctrl_reg, pp);
|
|
|
|
POSTING_READ(pp_ctrl_reg);
|
2011-11-02 10:57:50 +08:00
|
|
|
|
2013-03-29 00:55:41 +08:00
|
|
|
/* Make sure sequencer is idle before allowing subsequent activity */
|
|
|
|
DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
|
|
|
|
I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
|
2013-12-07 03:32:42 +08:00
|
|
|
|
|
|
|
if ((pp & POWER_TARGET_ON) == 0)
|
2013-12-20 00:29:40 +08:00
|
|
|
intel_dp->last_power_cycle = jiffies;
|
2013-11-21 23:47:23 +08:00
|
|
|
|
2014-03-27 23:45:11 +08:00
|
|
|
power_domain = intel_display_port_power_domain(intel_encoder);
|
|
|
|
intel_display_power_put(dev_priv, power_domain);
|
2011-09-19 14:09:52 +08:00
|
|
|
}
|
|
|
|
}
|
2011-01-25 09:10:54 +08:00
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
static void edp_panel_vdd_work(struct work_struct *__work)
|
2011-09-19 14:09:52 +08:00
|
|
|
{
|
|
|
|
struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
|
|
|
|
struct intel_dp, panel_vdd_work);
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2011-09-19 14:09:52 +08:00
|
|
|
|
2013-11-20 01:10:12 +08:00
|
|
|
drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
|
2014-01-17 21:39:48 +08:00
|
|
|
edp_panel_vdd_off_sync(intel_dp);
|
2013-11-20 01:10:12 +08:00
|
|
|
drm_modeset_unlock(&dev->mode_config.connection_mutex);
|
2011-09-19 14:09:52 +08:00
|
|
|
}
|
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
|
2011-09-19 14:09:52 +08:00
|
|
|
{
|
2011-09-29 07:23:51 +08:00
|
|
|
if (!is_edp(intel_dp))
|
|
|
|
return;
|
2011-01-25 09:10:54 +08:00
|
|
|
|
2011-09-19 14:09:52 +08:00
|
|
|
WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
|
2011-11-02 11:01:35 +08:00
|
|
|
|
2011-09-19 14:09:52 +08:00
|
|
|
intel_dp->want_panel_vdd = false;
|
|
|
|
|
|
|
|
if (sync) {
|
2014-01-17 21:39:48 +08:00
|
|
|
edp_panel_vdd_off_sync(intel_dp);
|
2011-09-19 14:09:52 +08:00
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* Queue the timer to fire a long
|
|
|
|
* time from now (relative to the power down delay)
|
|
|
|
* to keep the panel power up across a sequence of operations
|
|
|
|
*/
|
|
|
|
schedule_delayed_work(&intel_dp->panel_vdd_work,
|
|
|
|
msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
|
|
|
|
}
|
2011-01-25 09:10:54 +08:00
|
|
|
}
|
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
void intel_edp_panel_on(struct intel_dp *intel_dp)
|
2010-07-23 04:18:19 +08:00
|
|
|
{
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2010-07-23 04:18:19 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2011-11-02 10:57:50 +08:00
|
|
|
u32 pp;
|
2013-03-29 00:55:41 +08:00
|
|
|
u32 pp_ctrl_reg;
|
2010-07-23 04:18:19 +08:00
|
|
|
|
2011-09-29 07:23:51 +08:00
|
|
|
if (!is_edp(intel_dp))
|
2011-09-19 14:09:52 +08:00
|
|
|
return;
|
2011-11-02 10:57:50 +08:00
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Turn eDP power on\n");
|
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
if (edp_have_panel_power(intel_dp)) {
|
2011-11-02 10:57:50 +08:00
|
|
|
DRM_DEBUG_KMS("eDP power already on\n");
|
2011-09-30 07:05:34 +08:00
|
|
|
return;
|
2011-11-02 10:57:50 +08:00
|
|
|
}
|
2010-07-23 04:18:19 +08:00
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
wait_panel_power_cycle(intel_dp);
|
2010-08-12 01:04:43 +08:00
|
|
|
|
2013-09-06 12:40:05 +08:00
|
|
|
pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
|
2013-03-29 00:55:41 +08:00
|
|
|
pp = ironlake_get_pp_control(intel_dp);
|
2011-09-30 07:33:01 +08:00
|
|
|
if (IS_GEN5(dev)) {
|
|
|
|
/* ILK workaround: disable reset around power sequence */
|
|
|
|
pp &= ~PANEL_POWER_RESET;
|
2013-09-06 12:40:05 +08:00
|
|
|
I915_WRITE(pp_ctrl_reg, pp);
|
|
|
|
POSTING_READ(pp_ctrl_reg);
|
2011-09-30 07:33:01 +08:00
|
|
|
}
|
2010-08-12 01:04:43 +08:00
|
|
|
|
2011-09-20 04:59:29 +08:00
|
|
|
pp |= POWER_TARGET_ON;
|
2011-11-02 10:57:50 +08:00
|
|
|
if (!IS_GEN5(dev))
|
|
|
|
pp |= PANEL_POWER_RESET;
|
|
|
|
|
2013-03-29 00:55:41 +08:00
|
|
|
I915_WRITE(pp_ctrl_reg, pp);
|
|
|
|
POSTING_READ(pp_ctrl_reg);
|
2010-07-23 04:18:19 +08:00
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
wait_panel_on(intel_dp);
|
2013-12-20 00:29:40 +08:00
|
|
|
intel_dp->last_power_on = jiffies;
|
2010-07-23 04:18:19 +08:00
|
|
|
|
2011-09-30 07:33:01 +08:00
|
|
|
if (IS_GEN5(dev)) {
|
|
|
|
pp |= PANEL_POWER_RESET; /* restore panel reset bit */
|
2013-09-06 12:40:05 +08:00
|
|
|
I915_WRITE(pp_ctrl_reg, pp);
|
|
|
|
POSTING_READ(pp_ctrl_reg);
|
2011-09-30 07:33:01 +08:00
|
|
|
}
|
2010-07-23 04:18:19 +08:00
|
|
|
}
|
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
void intel_edp_panel_off(struct intel_dp *intel_dp)
|
2010-07-23 04:18:19 +08:00
|
|
|
{
|
2014-03-27 23:45:11 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct intel_encoder *intel_encoder = &intel_dig_port->base;
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2010-07-23 04:18:19 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2014-03-27 23:45:11 +08:00
|
|
|
enum intel_display_power_domain power_domain;
|
2011-11-02 10:57:50 +08:00
|
|
|
u32 pp;
|
2013-03-29 00:55:41 +08:00
|
|
|
u32 pp_ctrl_reg;
|
2010-07-23 04:18:19 +08:00
|
|
|
|
2011-09-29 07:23:51 +08:00
|
|
|
if (!is_edp(intel_dp))
|
|
|
|
return;
|
2010-08-12 01:04:43 +08:00
|
|
|
|
2011-11-02 10:57:50 +08:00
|
|
|
DRM_DEBUG_KMS("Turn eDP power off\n");
|
2010-08-12 01:04:43 +08:00
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
edp_wait_backlight_off(intel_dp);
|
2013-12-20 00:29:40 +08:00
|
|
|
|
2014-03-17 22:43:36 +08:00
|
|
|
WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
|
|
|
|
|
2013-03-29 00:55:41 +08:00
|
|
|
pp = ironlake_get_pp_control(intel_dp);
|
drm/i915: reorder edp disabling to fix ivb MacBook Air
eDP is tons of fun. It turns out that at least the new MacBook Air 5,1
model absolutely doesn't like the new force vdd dance we've introduced
in
commit 6cb49835da0426f69a2931bc2a0a8156344b0e41
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Sun May 20 17:14:50 2012 +0200
drm/i915: enable vdd when switching off the eDP panel
But that patch also tried to fix some neat edp sequence issue with the
force_vdd timings. Closer inspection reveals that we've raised
force_vdd only to do the aux channel communication dp_sink_dpms. If we
move the edp_panel_off below that, we don't need any force_vdd for the
disable sequence, which makes the Air happy.
Unfortunately the reporter of the original bug that the above commit
fixed is travelling, so we can't test whether this regresses things.
But my theory is that since we don't check for any power-off ->
force_vdd-on delays in edp_panel_vdd_on, this was the actual
root-cause of this failure. With that force_vdd dance completely
eliminated, I'm hopeful the original bug stays fixed, too.
For reference the old bug, which hopefully doesn't get broken by this:
https://bugzilla.kernel.org/show_bug.cgi?id=43163
In any case, regression fixers win over plain bugfixes, so this needs
to go in asap.
v2: The crucial pieces seems to be to clear the force_vdd flag
uncoditionally, too, in edp_panel_off. Looks like this is left behind
by the firmware somehow.
v3: The Apple firmware seems to switch off the panel on it's own, hence
we still need to keep force_vdd on, but properly clear it when switching
the panel off.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=45671
Tested-by: Roberto Romer <sildurin@gmail.com>
Tested-by: Daniel Wagner <wagi@monom.org>
Tested-by: Keith Packard <keithp@keithp.com>
Cc: stable@vger.kernel.org
Cc: Keith Packard <keithp@keithp.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-13 04:17:14 +08:00
|
|
|
/* We need to switch off panel power _and_ force vdd, for otherwise some
|
|
|
|
* panels get very unhappy and cease to work. */
|
2014-03-04 07:42:44 +08:00
|
|
|
pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
|
|
|
|
EDP_BLC_ENABLE);
|
2013-03-29 00:55:41 +08:00
|
|
|
|
2013-09-06 12:40:05 +08:00
|
|
|
pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
|
2013-03-29 00:55:41 +08:00
|
|
|
|
2014-03-08 07:05:20 +08:00
|
|
|
intel_dp->want_panel_vdd = false;
|
|
|
|
|
2013-03-29 00:55:41 +08:00
|
|
|
I915_WRITE(pp_ctrl_reg, pp);
|
|
|
|
POSTING_READ(pp_ctrl_reg);
|
2010-07-23 04:18:19 +08:00
|
|
|
|
2013-12-20 00:29:40 +08:00
|
|
|
intel_dp->last_power_cycle = jiffies;
|
2014-01-17 21:39:48 +08:00
|
|
|
wait_panel_off(intel_dp);
|
2014-03-08 07:05:20 +08:00
|
|
|
|
|
|
|
/* We got a reference when we enabled the VDD. */
|
2014-03-27 23:45:11 +08:00
|
|
|
power_domain = intel_display_port_power_domain(intel_encoder);
|
|
|
|
intel_display_power_put(dev_priv, power_domain);
|
2010-07-23 04:18:19 +08:00
|
|
|
}
|
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
void intel_edp_backlight_on(struct intel_dp *intel_dp)
|
2009-07-24 01:00:32 +08:00
|
|
|
{
|
2012-10-27 05:05:46 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
2009-07-24 01:00:32 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 pp;
|
2013-03-29 00:55:41 +08:00
|
|
|
u32 pp_ctrl_reg;
|
2009-07-24 01:00:32 +08:00
|
|
|
|
drm/i915: Correct eDP panel power sequencing delay computations
Store the panel power sequencing delays in the dp private structure,
rather than the global device structure. Who knows, maybe we'll get
more than one eDP device in the future.
From the eDP spec, we need the following numbers:
T1 + T3 Power on to Aux Channel operation (panel_power_up_delay)
This marks how long it takes the panel to boot up and
get ready to receive aux channel communications.
T8 Video signal to backlight on (backlight_on_delay)
Once a valid video signal is being sent to the device,
it can take a while before the panel is actuall
showing useful data. This delay allows the panel
to get something reasonable up before the backlight
is turned on.
T9 Backlight off to video off (backlight_off_delay)
Turning the backlight off can take a moment, so
this delay makes sure there is still valid video
data on the screen.
T10 Video off to power off (panel_power_down_delay)
Presumably this delay allows the panel to perform
an orderly shutdown of the display.
T11 + T12 Power off to power on (panel_power_cycle_delay)
So, once you turn the panel off, you have to wait a
while before you can turn it back on. This delay is
usually the longest in the entire sequence.
Neither the VBIOS source code nor the hardware documentation has a
clear mapping between the delay values they provide and those required
by the eDP spec. The VBIOS code actually uses two different labels for
the delay values in the five words of the relevant VBT table.
**** MORE LATER ***
Look at both the current hardware register settings and the VBT
specified panel power sequencing timings. Use the maximum of the two
delays, to make sure things work reliably. If there is no VBT data,
then those values will be initialized to zero, so we'll just use the
values as programmed in the hardware. Note that the BIOS just fetches
delays from the VBT table to place in the hardware registers, so we
should get the same values from both places, except for rounding.
VBT doesn't provide any values for T1 or T2, so we'll always just use
the hardware value for that.
The panel power up delay is thus T1 + T2 + T3, which should be
sufficient in all cases.
The panel power down delay is T1 + T2 + T12, using T1+T2 as a proxy
for T11, which isn't available anywhere.
For the backlight delays, the eDP spec says T6 + T8 is the delay from the
end of link training to backlight on and T9 is the delay from
backlight off until video off. The hardware provides a 'backlight on'
delay, which I'm taking to be T6 + T8 while the VBT provides something
called 'T7', which I'm assuming is s
On the macbook air I'm testing with, this yields a power-up delay of
over 200ms and a power-down delay of over 600ms. It all works now, but
we're frobbing these power controls several times during mode setting,
making the whole process take an awfully long time.
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-09-29 07:48:10 +08:00
|
|
|
if (!is_edp(intel_dp))
|
|
|
|
return;
|
|
|
|
|
2009-10-09 11:39:41 +08:00
|
|
|
DRM_DEBUG_KMS("\n");
|
2010-10-08 07:01:12 +08:00
|
|
|
/*
|
|
|
|
* If we enable the backlight right away following a panel power
|
|
|
|
* on, we may see slight flicker as the panel syncs with the eDP
|
|
|
|
* link. So delay a bit to make sure the image is solid before
|
|
|
|
* allowing it to appear.
|
|
|
|
*/
|
2014-01-17 21:39:48 +08:00
|
|
|
wait_backlight_on(intel_dp);
|
2013-03-29 00:55:41 +08:00
|
|
|
pp = ironlake_get_pp_control(intel_dp);
|
2009-07-24 01:00:32 +08:00
|
|
|
pp |= EDP_BLC_ENABLE;
|
2013-03-29 00:55:41 +08:00
|
|
|
|
2013-09-06 12:40:05 +08:00
|
|
|
pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
|
2013-03-29 00:55:41 +08:00
|
|
|
|
|
|
|
I915_WRITE(pp_ctrl_reg, pp);
|
|
|
|
POSTING_READ(pp_ctrl_reg);
|
2012-10-21 02:57:42 +08:00
|
|
|
|
2013-11-01 00:55:49 +08:00
|
|
|
intel_panel_enable_backlight(intel_dp->attached_connector);
|
2009-07-24 01:00:32 +08:00
|
|
|
}
|
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
void intel_edp_backlight_off(struct intel_dp *intel_dp)
|
2009-07-24 01:00:32 +08:00
|
|
|
{
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2009-07-24 01:00:32 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 pp;
|
2013-03-29 00:55:41 +08:00
|
|
|
u32 pp_ctrl_reg;
|
2009-07-24 01:00:32 +08:00
|
|
|
|
drm/i915: Correct eDP panel power sequencing delay computations
Store the panel power sequencing delays in the dp private structure,
rather than the global device structure. Who knows, maybe we'll get
more than one eDP device in the future.
From the eDP spec, we need the following numbers:
T1 + T3 Power on to Aux Channel operation (panel_power_up_delay)
This marks how long it takes the panel to boot up and
get ready to receive aux channel communications.
T8 Video signal to backlight on (backlight_on_delay)
Once a valid video signal is being sent to the device,
it can take a while before the panel is actuall
showing useful data. This delay allows the panel
to get something reasonable up before the backlight
is turned on.
T9 Backlight off to video off (backlight_off_delay)
Turning the backlight off can take a moment, so
this delay makes sure there is still valid video
data on the screen.
T10 Video off to power off (panel_power_down_delay)
Presumably this delay allows the panel to perform
an orderly shutdown of the display.
T11 + T12 Power off to power on (panel_power_cycle_delay)
So, once you turn the panel off, you have to wait a
while before you can turn it back on. This delay is
usually the longest in the entire sequence.
Neither the VBIOS source code nor the hardware documentation has a
clear mapping between the delay values they provide and those required
by the eDP spec. The VBIOS code actually uses two different labels for
the delay values in the five words of the relevant VBT table.
**** MORE LATER ***
Look at both the current hardware register settings and the VBT
specified panel power sequencing timings. Use the maximum of the two
delays, to make sure things work reliably. If there is no VBT data,
then those values will be initialized to zero, so we'll just use the
values as programmed in the hardware. Note that the BIOS just fetches
delays from the VBT table to place in the hardware registers, so we
should get the same values from both places, except for rounding.
VBT doesn't provide any values for T1 or T2, so we'll always just use
the hardware value for that.
The panel power up delay is thus T1 + T2 + T3, which should be
sufficient in all cases.
The panel power down delay is T1 + T2 + T12, using T1+T2 as a proxy
for T11, which isn't available anywhere.
For the backlight delays, the eDP spec says T6 + T8 is the delay from the
end of link training to backlight on and T9 is the delay from
backlight off until video off. The hardware provides a 'backlight on'
delay, which I'm taking to be T6 + T8 while the VBT provides something
called 'T7', which I'm assuming is s
On the macbook air I'm testing with, this yields a power-up delay of
over 200ms and a power-down delay of over 600ms. It all works now, but
we're frobbing these power controls several times during mode setting,
making the whole process take an awfully long time.
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-09-29 07:48:10 +08:00
|
|
|
if (!is_edp(intel_dp))
|
|
|
|
return;
|
|
|
|
|
2013-11-01 00:55:49 +08:00
|
|
|
intel_panel_disable_backlight(intel_dp->attached_connector);
|
2012-10-21 02:57:42 +08:00
|
|
|
|
2009-10-09 11:39:41 +08:00
|
|
|
DRM_DEBUG_KMS("\n");
|
2013-03-29 00:55:41 +08:00
|
|
|
pp = ironlake_get_pp_control(intel_dp);
|
2009-07-24 01:00:32 +08:00
|
|
|
pp &= ~EDP_BLC_ENABLE;
|
2013-03-29 00:55:41 +08:00
|
|
|
|
2013-09-06 12:40:05 +08:00
|
|
|
pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
|
2013-03-29 00:55:41 +08:00
|
|
|
|
|
|
|
I915_WRITE(pp_ctrl_reg, pp);
|
|
|
|
POSTING_READ(pp_ctrl_reg);
|
2013-12-20 00:29:40 +08:00
|
|
|
intel_dp->last_backlight_off = jiffies;
|
2009-07-24 01:00:32 +08:00
|
|
|
}
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2012-09-07 04:15:41 +08:00
|
|
|
static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
|
2010-08-14 06:43:26 +08:00
|
|
|
{
|
2012-10-27 05:05:46 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
|
|
|
|
struct drm_device *dev = crtc->dev;
|
2010-08-14 06:43:26 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 dpa_ctl;
|
|
|
|
|
2012-09-07 04:15:41 +08:00
|
|
|
assert_pipe_disabled(dev_priv,
|
|
|
|
to_intel_crtc(crtc)->pipe);
|
|
|
|
|
2010-08-14 06:43:26 +08:00
|
|
|
DRM_DEBUG_KMS("\n");
|
|
|
|
dpa_ctl = I915_READ(DP_A);
|
2012-09-07 04:15:42 +08:00
|
|
|
WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
|
|
|
|
WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
|
|
|
|
|
|
|
|
/* We don't adjust intel_dp->DP while tearing down the link, to
|
|
|
|
* facilitate link retraining (e.g. after hotplug). Hence clear all
|
|
|
|
* enable bits here to ensure that we don't enable too much. */
|
|
|
|
intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
|
|
|
|
intel_dp->DP |= DP_PLL_ENABLE;
|
|
|
|
I915_WRITE(DP_A, intel_dp->DP);
|
2010-10-08 07:01:24 +08:00
|
|
|
POSTING_READ(DP_A);
|
|
|
|
udelay(200);
|
2010-08-14 06:43:26 +08:00
|
|
|
}
|
|
|
|
|
2012-09-07 04:15:41 +08:00
|
|
|
static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
|
2010-08-14 06:43:26 +08:00
|
|
|
{
|
2012-10-27 05:05:46 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
|
|
|
|
struct drm_device *dev = crtc->dev;
|
2010-08-14 06:43:26 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
u32 dpa_ctl;
|
|
|
|
|
2012-09-07 04:15:41 +08:00
|
|
|
assert_pipe_disabled(dev_priv,
|
|
|
|
to_intel_crtc(crtc)->pipe);
|
|
|
|
|
2010-08-14 06:43:26 +08:00
|
|
|
dpa_ctl = I915_READ(DP_A);
|
2012-09-07 04:15:42 +08:00
|
|
|
WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
|
|
|
|
"dp pll off, should be on\n");
|
|
|
|
WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
|
|
|
|
|
|
|
|
/* We can't rely on the value tracked for the DP register in
|
|
|
|
* intel_dp->DP because link_down must not change that (otherwise link
|
|
|
|
* re-training will fail. */
|
2010-10-08 07:01:24 +08:00
|
|
|
dpa_ctl &= ~DP_PLL_ENABLE;
|
2010-08-14 06:43:26 +08:00
|
|
|
I915_WRITE(DP_A, dpa_ctl);
|
2010-09-09 04:07:28 +08:00
|
|
|
POSTING_READ(DP_A);
|
2010-08-14 06:43:26 +08:00
|
|
|
udelay(200);
|
|
|
|
}
|
|
|
|
|
2011-07-08 02:11:03 +08:00
|
|
|
/* If the sink supports it, try to set the power state appropriately */
|
2012-10-16 02:51:41 +08:00
|
|
|
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
|
2011-07-08 02:11:03 +08:00
|
|
|
{
|
|
|
|
int ret, i;
|
|
|
|
|
|
|
|
/* Should have a valid DPCD by this point */
|
|
|
|
if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (mode != DRM_MODE_DPMS_ON) {
|
2014-03-14 22:51:15 +08:00
|
|
|
ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
|
|
|
|
DP_SET_POWER_D3);
|
2011-07-08 02:11:03 +08:00
|
|
|
if (ret != 1)
|
|
|
|
DRM_DEBUG_DRIVER("failed to write sink power state\n");
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* When turning on, we need to retry for 1ms to give the sink
|
|
|
|
* time to wake up.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < 3; i++) {
|
2014-03-14 22:51:15 +08:00
|
|
|
ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
|
|
|
|
DP_SET_POWER_D0);
|
2011-07-08 02:11:03 +08:00
|
|
|
if (ret == 1)
|
|
|
|
break;
|
|
|
|
msleep(1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-07-02 19:26:27 +08:00
|
|
|
static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
|
|
|
|
enum pipe *pipe)
|
2010-08-14 06:43:26 +08:00
|
|
|
{
|
2012-07-02 19:26:27 +08:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
2013-05-16 19:40:36 +08:00
|
|
|
enum port port = dp_to_dig_port(intel_dp)->port;
|
2012-07-02 19:26:27 +08:00
|
|
|
struct drm_device *dev = encoder->base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2014-03-05 22:20:54 +08:00
|
|
|
enum intel_display_power_domain power_domain;
|
|
|
|
u32 tmp;
|
|
|
|
|
|
|
|
power_domain = intel_display_port_power_domain(encoder);
|
|
|
|
if (!intel_display_power_enabled(dev_priv, power_domain))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
tmp = I915_READ(intel_dp->output_reg);
|
2012-07-02 19:26:27 +08:00
|
|
|
|
|
|
|
if (!(tmp & DP_PORT_EN))
|
|
|
|
return false;
|
|
|
|
|
2013-05-16 19:40:36 +08:00
|
|
|
if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
|
2012-07-02 19:26:27 +08:00
|
|
|
*pipe = PORT_TO_PIPE_CPT(tmp);
|
2014-04-09 18:28:55 +08:00
|
|
|
} else if (IS_CHERRYVIEW(dev)) {
|
|
|
|
*pipe = DP_PORT_TO_PIPE_CHV(tmp);
|
2013-05-16 19:40:36 +08:00
|
|
|
} else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
|
2012-07-02 19:26:27 +08:00
|
|
|
*pipe = PORT_TO_PIPE(tmp);
|
|
|
|
} else {
|
|
|
|
u32 trans_sel;
|
|
|
|
u32 trans_dp;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
switch (intel_dp->output_reg) {
|
|
|
|
case PCH_DP_B:
|
|
|
|
trans_sel = TRANS_DP_PORT_SEL_B;
|
|
|
|
break;
|
|
|
|
case PCH_DP_C:
|
|
|
|
trans_sel = TRANS_DP_PORT_SEL_C;
|
|
|
|
break;
|
|
|
|
case PCH_DP_D:
|
|
|
|
trans_sel = TRANS_DP_PORT_SEL_D;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
for_each_pipe(i) {
|
|
|
|
trans_dp = I915_READ(TRANS_DP_CTL(i));
|
|
|
|
if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
|
|
|
|
*pipe = i;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-26 16:58:11 +08:00
|
|
|
DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
|
|
|
|
intel_dp->output_reg);
|
|
|
|
}
|
2010-08-14 06:43:26 +08:00
|
|
|
|
2012-07-02 19:26:27 +08:00
|
|
|
return true;
|
|
|
|
}
|
2010-08-14 06:43:26 +08:00
|
|
|
|
2013-05-15 08:08:26 +08:00
|
|
|
static void intel_dp_get_config(struct intel_encoder *encoder,
|
|
|
|
struct intel_crtc_config *pipe_config)
|
|
|
|
{
|
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
|
|
|
u32 tmp, flags = 0;
|
2013-06-28 12:59:06 +08:00
|
|
|
struct drm_device *dev = encoder->base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
enum port port = dp_to_dig_port(intel_dp)->port;
|
|
|
|
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
|
2013-09-13 21:00:08 +08:00
|
|
|
int dotclock;
|
2013-05-15 08:08:26 +08:00
|
|
|
|
2014-04-25 05:54:52 +08:00
|
|
|
tmp = I915_READ(intel_dp->output_reg);
|
|
|
|
if (tmp & DP_AUDIO_OUTPUT_ENABLE)
|
|
|
|
pipe_config->has_audio = true;
|
|
|
|
|
2013-06-28 12:59:06 +08:00
|
|
|
if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
|
|
|
|
if (tmp & DP_SYNC_HS_HIGH)
|
|
|
|
flags |= DRM_MODE_FLAG_PHSYNC;
|
|
|
|
else
|
|
|
|
flags |= DRM_MODE_FLAG_NHSYNC;
|
2013-05-15 08:08:26 +08:00
|
|
|
|
2013-06-28 12:59:06 +08:00
|
|
|
if (tmp & DP_SYNC_VS_HIGH)
|
|
|
|
flags |= DRM_MODE_FLAG_PVSYNC;
|
|
|
|
else
|
|
|
|
flags |= DRM_MODE_FLAG_NVSYNC;
|
|
|
|
} else {
|
|
|
|
tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
|
|
|
|
if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
|
|
|
|
flags |= DRM_MODE_FLAG_PHSYNC;
|
|
|
|
else
|
|
|
|
flags |= DRM_MODE_FLAG_NHSYNC;
|
2013-05-15 08:08:26 +08:00
|
|
|
|
2013-06-28 12:59:06 +08:00
|
|
|
if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
|
|
|
|
flags |= DRM_MODE_FLAG_PVSYNC;
|
|
|
|
else
|
|
|
|
flags |= DRM_MODE_FLAG_NVSYNC;
|
|
|
|
}
|
2013-05-15 08:08:26 +08:00
|
|
|
|
|
|
|
pipe_config->adjusted_mode.flags |= flags;
|
2013-06-27 05:39:25 +08:00
|
|
|
|
2013-09-10 22:02:54 +08:00
|
|
|
pipe_config->has_dp_encoder = true;
|
|
|
|
|
|
|
|
intel_dp_get_m_n(crtc, pipe_config);
|
|
|
|
|
2013-09-13 21:00:08 +08:00
|
|
|
if (port == PORT_A) {
|
2013-06-27 05:39:25 +08:00
|
|
|
if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
|
|
|
|
pipe_config->port_clock = 162000;
|
|
|
|
else
|
|
|
|
pipe_config->port_clock = 270000;
|
|
|
|
}
|
2013-09-13 21:00:08 +08:00
|
|
|
|
|
|
|
dotclock = intel_dotclock_calculate(pipe_config->port_clock,
|
|
|
|
&pipe_config->dp_m_n);
|
|
|
|
|
|
|
|
if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
|
|
|
|
ironlake_check_encoder_dotclock(pipe_config, dotclock);
|
|
|
|
|
2013-09-25 23:45:37 +08:00
|
|
|
pipe_config->adjusted_mode.crtc_clock = dotclock;
|
2013-11-04 23:28:47 +08:00
|
|
|
|
drm/i915/dp: workaround BIOS eDP bpp clamping issue
This isn't a real fix to the problem, but rather a stopgap measure while
trying to find a proper solution.
There are several laptops out there that fail to light up the eDP panel
in UEFI boot mode. They seem to be mostly IVB machines, including but
apparently not limited to Dell XPS 13, Asus TX300, Asus UX31A, Asus
UX32VD, Acer Aspire S7. They seem to work in CSM or legacy boot.
The difference between UEFI and CSM is that the BIOS provides a
different VBT to the kernel. The UEFI VBT typically specifies 18 bpp and
1.62 GHz link for eDP, while CSM VBT has 24 bpp and 2.7 GHz link. We end
up clamping to 18 bpp in UEFI mode, which we can fit in the 1.62 Ghz
link, and for reasons yet unknown fail to light up the panel.
Dithering from 24 to 18 bpp itself seems to work; if we use 18 bpp with
2.7 GHz link, the eDP panel lights up. So essentially this is a link
speed issue, and *not* a bpp clamping issue.
The bug raised its head since
commit 657445fe8660100ad174600ebfa61536392b7624
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Sat May 4 10:09:18 2013 +0200
Revert "drm/i915: revert eDP bpp clamping code changes"
which started clamping bpp *before* computing the link requirements, and
thus affecting the required bandwidth. Clamping after the computations
kept the link at 2.7 GHz.
Even though the BIOS tells us to use 18 bpp through the VBT, it happily
boots up at 24 bpp and 2.7 GHz itself! Use this information to
selectively ignore the VBT provided value.
We can't ignore the VBT eDP bpp altogether, as there are other laptops
that do require the clamping to be used due to EDID reporting higher bpp
than the panel can support.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=59841
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67950
Tested-by: Ulf Winkelvos <ulf@winkelvos.de>
Tested-by: jkp <jkp@iki.fi>
CC: stable@vger.kernel.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-10-21 15:52:07 +08:00
|
|
|
if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
|
|
|
|
pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
|
|
|
|
/*
|
|
|
|
* This is a big fat ugly hack.
|
|
|
|
*
|
|
|
|
* Some machines in UEFI boot mode provide us a VBT that has 18
|
|
|
|
* bpp and 1.62 GHz link bandwidth for eDP, which for reasons
|
|
|
|
* unknown we fail to light up. Yet the same BIOS boots up with
|
|
|
|
* 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
|
|
|
|
* max, not what it tells us to use.
|
|
|
|
*
|
|
|
|
* Note: This will still be broken if the eDP panel is not lit
|
|
|
|
* up by the BIOS, and thus we can't get the mode at module
|
|
|
|
* load.
|
|
|
|
*/
|
|
|
|
DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
|
|
|
|
pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
|
|
|
|
dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
|
|
|
|
}
|
2013-05-15 08:08:26 +08:00
|
|
|
}
|
|
|
|
|
2014-06-13 01:16:40 +08:00
|
|
|
static bool is_edp_psr(struct intel_dp *intel_dp)
|
2013-07-12 05:44:56 +08:00
|
|
|
{
|
2014-06-13 01:16:40 +08:00
|
|
|
return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
|
2013-07-12 05:44:56 +08:00
|
|
|
}
|
|
|
|
|
2013-07-12 05:44:58 +08:00
|
|
|
static bool intel_edp_is_psr_enabled(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
2013-09-21 00:35:30 +08:00
|
|
|
if (!HAS_PSR(dev))
|
2013-07-12 05:44:58 +08:00
|
|
|
return false;
|
|
|
|
|
2013-09-21 00:35:30 +08:00
|
|
|
return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
|
2013-07-12 05:44:58 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
|
|
|
|
struct edp_vsc_psr *vsc_psr)
|
|
|
|
{
|
|
|
|
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_device *dev = dig_port->base.base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
|
|
|
|
u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
|
|
|
|
u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
|
|
|
|
uint32_t *data = (uint32_t *) vsc_psr;
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
/* As per BSPec (Pipe Video Data Island Packet), we need to disable
|
|
|
|
the video DIP being updated before program video DIP data buffer
|
|
|
|
registers for DIP being updated. */
|
|
|
|
I915_WRITE(ctl_reg, 0);
|
|
|
|
POSTING_READ(ctl_reg);
|
|
|
|
|
|
|
|
for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
|
|
|
|
if (i < sizeof(struct edp_vsc_psr))
|
|
|
|
I915_WRITE(data_reg + i, *data++);
|
|
|
|
else
|
|
|
|
I915_WRITE(data_reg + i, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
|
|
|
|
POSTING_READ(ctl_reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_edp_psr_setup(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct edp_vsc_psr psr_vsc;
|
|
|
|
|
2014-05-24 04:45:51 +08:00
|
|
|
if (dev_priv->psr.setup_done)
|
2013-07-12 05:44:58 +08:00
|
|
|
return;
|
|
|
|
|
|
|
|
/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
|
|
|
|
memset(&psr_vsc, 0, sizeof(psr_vsc));
|
|
|
|
psr_vsc.sdp_header.HB0 = 0;
|
|
|
|
psr_vsc.sdp_header.HB1 = 0x7;
|
|
|
|
psr_vsc.sdp_header.HB2 = 0x2;
|
|
|
|
psr_vsc.sdp_header.HB3 = 0x8;
|
|
|
|
intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
|
|
|
|
|
|
|
|
/* Avoid continuous PSR exit by masking memup and hpd */
|
2013-09-21 00:35:30 +08:00
|
|
|
I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
|
2013-10-04 00:31:26 +08:00
|
|
|
EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
|
2013-07-12 05:44:58 +08:00
|
|
|
|
2014-05-24 04:45:51 +08:00
|
|
|
dev_priv->psr.setup_done = true;
|
2013-07-12 05:44:58 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
|
|
|
|
{
|
2014-06-13 01:16:44 +08:00
|
|
|
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_device *dev = dig_port->base.base.dev;
|
2013-07-12 05:44:58 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2014-01-21 21:35:39 +08:00
|
|
|
uint32_t aux_clock_divider;
|
2013-07-12 05:44:58 +08:00
|
|
|
int precharge = 0x3;
|
|
|
|
int msg_size = 5; /* Header(4) + Message(1) */
|
2014-06-13 01:16:44 +08:00
|
|
|
bool only_standby = false;
|
2013-07-12 05:44:58 +08:00
|
|
|
|
2014-01-21 21:35:39 +08:00
|
|
|
aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
|
|
|
|
|
2014-06-13 01:16:44 +08:00
|
|
|
if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
|
|
|
|
only_standby = true;
|
|
|
|
|
2013-07-12 05:44:58 +08:00
|
|
|
/* Enable PSR in sink */
|
2014-06-13 01:16:44 +08:00
|
|
|
if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
|
2014-03-14 22:51:15 +08:00
|
|
|
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
|
|
|
|
DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
|
2013-07-12 05:44:58 +08:00
|
|
|
else
|
2014-03-14 22:51:15 +08:00
|
|
|
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
|
|
|
|
DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
|
2013-07-12 05:44:58 +08:00
|
|
|
|
|
|
|
/* Setup AUX registers */
|
2013-09-21 00:35:30 +08:00
|
|
|
I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
|
|
|
|
I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
|
|
|
|
I915_WRITE(EDP_PSR_AUX_CTL(dev),
|
2013-07-12 05:44:58 +08:00
|
|
|
DP_AUX_CH_CTL_TIME_OUT_400us |
|
|
|
|
(msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
|
|
|
|
(precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
|
|
|
|
(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
|
|
|
|
{
|
2014-06-13 01:16:44 +08:00
|
|
|
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_device *dev = dig_port->base.base.dev;
|
2013-07-12 05:44:58 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
uint32_t max_sleep_time = 0x1f;
|
|
|
|
uint32_t idle_frames = 1;
|
|
|
|
uint32_t val = 0x0;
|
2013-11-05 14:45:05 +08:00
|
|
|
const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
|
2014-06-13 01:16:44 +08:00
|
|
|
bool only_standby = false;
|
|
|
|
|
|
|
|
if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
|
|
|
|
only_standby = true;
|
2013-07-12 05:44:58 +08:00
|
|
|
|
2014-06-13 01:16:44 +08:00
|
|
|
if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
|
2013-07-12 05:44:58 +08:00
|
|
|
val |= EDP_PSR_LINK_STANDBY;
|
|
|
|
val |= EDP_PSR_TP2_TP3_TIME_0us;
|
|
|
|
val |= EDP_PSR_TP1_TIME_0us;
|
|
|
|
val |= EDP_PSR_SKIP_AUX_EXIT;
|
2014-06-13 01:16:42 +08:00
|
|
|
val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
|
2013-07-12 05:44:58 +08:00
|
|
|
} else
|
|
|
|
val |= EDP_PSR_LINK_DISABLE;
|
|
|
|
|
2013-09-21 00:35:30 +08:00
|
|
|
I915_WRITE(EDP_PSR_CTL(dev), val |
|
2014-03-05 14:38:10 +08:00
|
|
|
(IS_BROADWELL(dev) ? 0 : link_entry_time) |
|
2013-07-12 05:44:58 +08:00
|
|
|
max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
|
|
|
|
idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
|
|
|
|
EDP_PSR_ENABLE);
|
|
|
|
}
|
|
|
|
|
2013-07-12 05:45:00 +08:00
|
|
|
static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_device *dev = dig_port->base.base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct drm_crtc *crtc = dig_port->base.base.crtc;
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
2014-04-02 06:22:40 +08:00
|
|
|
struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
|
2013-07-12 05:45:00 +08:00
|
|
|
struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
|
|
|
|
|
2013-10-04 03:15:06 +08:00
|
|
|
dev_priv->psr.source_ok = false;
|
|
|
|
|
2014-06-13 01:16:44 +08:00
|
|
|
if (!HAS_PSR(dev)) {
|
|
|
|
DRM_DEBUG_KMS("PSR not supported on this platform\n");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (IS_HASWELL(dev) && (intel_encoder->type != INTEL_OUTPUT_EDP ||
|
|
|
|
dig_port->port != PORT_A)) {
|
2013-07-12 05:45:00 +08:00
|
|
|
DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2014-01-21 17:24:25 +08:00
|
|
|
if (!i915.enable_psr) {
|
2013-07-12 05:45:02 +08:00
|
|
|
DRM_DEBUG_KMS("PSR disable by flag\n");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2013-08-03 03:39:49 +08:00
|
|
|
crtc = dig_port->base.base.crtc;
|
|
|
|
if (crtc == NULL) {
|
|
|
|
DRM_DEBUG_KMS("crtc not active for PSR\n");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
intel_crtc = to_intel_crtc(crtc);
|
2013-09-04 23:25:25 +08:00
|
|
|
if (!intel_crtc_active(crtc)) {
|
2013-07-12 05:45:00 +08:00
|
|
|
DRM_DEBUG_KMS("crtc not active for PSR\n");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2014-04-02 06:22:40 +08:00
|
|
|
obj = to_intel_framebuffer(crtc->primary->fb)->obj;
|
2013-07-12 05:45:00 +08:00
|
|
|
if (obj->tiling_mode != I915_TILING_X ||
|
|
|
|
obj->fence_reg == I915_FENCE_REG_NONE) {
|
|
|
|
DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2014-06-13 01:16:43 +08:00
|
|
|
/* Below limitations aren't valid for Broadwell */
|
|
|
|
if (IS_BROADWELL(dev))
|
|
|
|
goto out;
|
|
|
|
|
2013-07-12 05:45:00 +08:00
|
|
|
if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
|
|
|
|
DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
|
|
|
|
S3D_ENABLE) {
|
|
|
|
DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2013-09-04 23:25:24 +08:00
|
|
|
if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
|
2013-07-12 05:45:00 +08:00
|
|
|
DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2014-06-13 01:16:43 +08:00
|
|
|
out:
|
2013-10-04 03:15:06 +08:00
|
|
|
dev_priv->psr.source_ok = true;
|
2013-07-12 05:45:00 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-07-12 05:45:01 +08:00
|
|
|
static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
|
2013-07-12 05:44:58 +08:00
|
|
|
{
|
2014-06-13 20:10:03 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-07-12 05:44:58 +08:00
|
|
|
|
2014-06-13 20:10:03 +08:00
|
|
|
if (intel_edp_is_psr_enabled(dev))
|
2013-07-12 05:44:58 +08:00
|
|
|
return;
|
|
|
|
|
|
|
|
/* Enable PSR on the panel */
|
|
|
|
intel_edp_psr_enable_sink(intel_dp);
|
|
|
|
|
|
|
|
/* Enable PSR on the host */
|
|
|
|
intel_edp_psr_enable_source(intel_dp);
|
2014-06-13 20:10:03 +08:00
|
|
|
|
|
|
|
dev_priv->psr.enabled = true;
|
|
|
|
dev_priv->psr.active = true;
|
2013-07-12 05:44:58 +08:00
|
|
|
}
|
|
|
|
|
2013-07-12 05:45:01 +08:00
|
|
|
void intel_edp_psr_enable(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
|
|
|
|
2014-06-13 01:16:38 +08:00
|
|
|
if (!HAS_PSR(dev)) {
|
|
|
|
DRM_DEBUG_KMS("PSR not supported on this platform\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2014-06-13 01:16:40 +08:00
|
|
|
if (!is_edp_psr(intel_dp)) {
|
|
|
|
DRM_DEBUG_KMS("PSR not supported by this panel\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2014-06-13 01:16:39 +08:00
|
|
|
/* Setup PSR once */
|
|
|
|
intel_edp_psr_setup(intel_dp);
|
|
|
|
|
2014-06-13 20:10:03 +08:00
|
|
|
if (intel_edp_psr_match_conditions(intel_dp))
|
2013-07-12 05:45:01 +08:00
|
|
|
intel_edp_psr_do_enable(intel_dp);
|
|
|
|
}
|
|
|
|
|
2013-07-12 05:44:58 +08:00
|
|
|
void intel_edp_psr_disable(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
2014-06-13 20:10:03 +08:00
|
|
|
if (!dev_priv->psr.enabled)
|
2013-07-12 05:44:58 +08:00
|
|
|
return;
|
|
|
|
|
2013-09-21 00:35:30 +08:00
|
|
|
I915_WRITE(EDP_PSR_CTL(dev),
|
|
|
|
I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
|
2013-07-12 05:44:58 +08:00
|
|
|
|
|
|
|
/* Wait till PSR is idle */
|
2013-09-21 00:35:30 +08:00
|
|
|
if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
|
2013-07-12 05:44:58 +08:00
|
|
|
EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
|
|
|
|
DRM_ERROR("Timed out waiting for PSR Idle State\n");
|
2014-06-13 20:10:03 +08:00
|
|
|
|
|
|
|
dev_priv->psr.enabled = false;
|
2013-07-12 05:44:58 +08:00
|
|
|
}
|
|
|
|
|
2014-06-17 01:51:21 +08:00
|
|
|
static void intel_edp_psr_work(struct work_struct *work)
|
2014-06-13 20:10:03 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv =
|
|
|
|
container_of(work, typeof(*dev_priv), psr.work.work);
|
|
|
|
struct drm_device *dev = dev_priv->dev;
|
|
|
|
struct intel_encoder *encoder;
|
|
|
|
struct intel_dp *intel_dp = NULL;
|
|
|
|
|
2013-07-12 05:45:01 +08:00
|
|
|
list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
|
|
|
|
if (encoder->type == INTEL_OUTPUT_EDP) {
|
|
|
|
intel_dp = enc_to_intel_dp(&encoder->base);
|
|
|
|
|
|
|
|
if (!intel_edp_psr_match_conditions(intel_dp))
|
|
|
|
intel_edp_psr_disable(intel_dp);
|
|
|
|
else
|
2014-06-13 20:10:03 +08:00
|
|
|
intel_edp_psr_do_enable(intel_dp);
|
2013-07-12 05:45:01 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-06-17 01:51:21 +08:00
|
|
|
static void intel_edp_psr_inactivate(struct drm_device *dev)
|
2014-06-13 20:10:03 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
2014-06-18 19:59:02 +08:00
|
|
|
dev_priv->psr.active = false;
|
2014-06-13 20:10:03 +08:00
|
|
|
|
2014-06-18 19:59:02 +08:00
|
|
|
I915_WRITE(EDP_PSR_CTL(dev), I915_READ(EDP_PSR_CTL(dev))
|
|
|
|
& ~EDP_PSR_ENABLE);
|
2014-06-13 20:10:03 +08:00
|
|
|
}
|
|
|
|
|
2014-06-18 19:59:05 +08:00
|
|
|
void intel_edp_psr_exit(struct drm_device *dev)
|
2014-06-13 20:10:03 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
if (!HAS_PSR(dev))
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (!dev_priv->psr.setup_done)
|
|
|
|
return;
|
|
|
|
|
|
|
|
cancel_delayed_work_sync(&dev_priv->psr.work);
|
|
|
|
|
|
|
|
if (dev_priv->psr.active)
|
|
|
|
intel_edp_psr_inactivate(dev);
|
|
|
|
|
2014-06-18 19:59:05 +08:00
|
|
|
schedule_delayed_work(&dev_priv->psr.work,
|
|
|
|
msecs_to_jiffies(100));
|
2014-06-13 20:10:03 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void intel_edp_psr_init(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
|
|
|
if (!HAS_PSR(dev))
|
|
|
|
return;
|
|
|
|
|
|
|
|
INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
|
|
|
|
}
|
|
|
|
|
2012-07-01 19:05:48 +08:00
|
|
|
static void intel_disable_dp(struct intel_encoder *encoder)
|
2010-08-14 06:43:26 +08:00
|
|
|
{
|
2012-07-01 19:05:48 +08:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
2013-05-24 00:39:40 +08:00
|
|
|
enum port port = dp_to_dig_port(intel_dp)->port;
|
|
|
|
struct drm_device *dev = encoder->base.dev;
|
2012-05-20 23:14:50 +08:00
|
|
|
|
|
|
|
/* Make sure the panel is off before trying to change the mode. But also
|
|
|
|
* ensure that we have vdd while we switch off the panel. */
|
2014-03-17 22:43:36 +08:00
|
|
|
intel_edp_panel_vdd_on(intel_dp);
|
2014-01-17 21:39:48 +08:00
|
|
|
intel_edp_backlight_off(intel_dp);
|
2013-11-12 23:10:13 +08:00
|
|
|
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
|
2014-01-17 21:39:48 +08:00
|
|
|
intel_edp_panel_off(intel_dp);
|
2012-09-07 04:15:44 +08:00
|
|
|
|
|
|
|
/* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
|
2013-05-24 00:39:40 +08:00
|
|
|
if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
|
2012-09-07 04:15:44 +08:00
|
|
|
intel_dp_link_down(intel_dp);
|
2010-08-14 06:43:26 +08:00
|
|
|
}
|
|
|
|
|
2014-03-31 23:21:26 +08:00
|
|
|
static void g4x_post_disable_dp(struct intel_encoder *encoder)
|
2010-08-14 06:43:26 +08:00
|
|
|
{
|
2012-09-07 04:15:41 +08:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
2013-05-24 00:39:40 +08:00
|
|
|
enum port port = dp_to_dig_port(intel_dp)->port;
|
2012-09-07 04:15:41 +08:00
|
|
|
|
2014-03-31 23:21:26 +08:00
|
|
|
if (port != PORT_A)
|
|
|
|
return;
|
|
|
|
|
|
|
|
intel_dp_link_down(intel_dp);
|
|
|
|
ironlake_edp_pll_off(intel_dp);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void vlv_post_disable_dp(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
|
|
|
|
|
|
|
intel_dp_link_down(intel_dp);
|
2012-09-07 04:15:41 +08:00
|
|
|
}
|
|
|
|
|
2014-04-09 18:29:00 +08:00
|
|
|
static void chv_post_disable_dp(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
|
|
|
struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_device *dev = encoder->base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct intel_crtc *intel_crtc =
|
|
|
|
to_intel_crtc(encoder->base.crtc);
|
|
|
|
enum dpio_channel ch = vlv_dport_to_channel(dport);
|
|
|
|
enum pipe pipe = intel_crtc->pipe;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
intel_dp_link_down(intel_dp);
|
|
|
|
|
|
|
|
mutex_lock(&dev_priv->dpio_lock);
|
|
|
|
|
|
|
|
/* Propagate soft reset to data lane reset */
|
2014-04-09 18:29:02 +08:00
|
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
|
2014-04-28 19:15:24 +08:00
|
|
|
val |= CHV_PCS_REQ_SOFTRESET_EN;
|
2014-04-09 18:29:02 +08:00
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
|
2014-04-28 19:15:24 +08:00
|
|
|
|
2014-04-09 18:29:02 +08:00
|
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
|
|
|
|
val |= CHV_PCS_REQ_SOFTRESET_EN;
|
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
|
|
|
|
|
|
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
|
|
|
|
val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
|
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
|
|
|
|
|
|
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
|
2014-04-09 18:29:00 +08:00
|
|
|
val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
|
2014-04-09 18:29:02 +08:00
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
|
2014-04-09 18:29:00 +08:00
|
|
|
|
|
|
|
mutex_unlock(&dev_priv->dpio_lock);
|
|
|
|
}
|
|
|
|
|
2012-07-01 19:05:48 +08:00
|
|
|
static void intel_enable_dp(struct intel_encoder *encoder)
|
2010-08-14 06:43:26 +08:00
|
|
|
{
|
2012-07-01 19:05:48 +08:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
|
|
|
struct drm_device *dev = encoder->base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
uint32_t dp_reg = I915_READ(intel_dp->output_reg);
|
2011-01-25 09:10:54 +08:00
|
|
|
|
2012-09-07 04:15:43 +08:00
|
|
|
if (WARN_ON(dp_reg & DP_PORT_EN))
|
|
|
|
return;
|
2011-01-25 09:10:54 +08:00
|
|
|
|
2014-03-17 22:43:36 +08:00
|
|
|
intel_edp_panel_vdd_on(intel_dp);
|
drm/i915: Correct eDP panel power sequencing delay computations
Store the panel power sequencing delays in the dp private structure,
rather than the global device structure. Who knows, maybe we'll get
more than one eDP device in the future.
From the eDP spec, we need the following numbers:
T1 + T3 Power on to Aux Channel operation (panel_power_up_delay)
This marks how long it takes the panel to boot up and
get ready to receive aux channel communications.
T8 Video signal to backlight on (backlight_on_delay)
Once a valid video signal is being sent to the device,
it can take a while before the panel is actuall
showing useful data. This delay allows the panel
to get something reasonable up before the backlight
is turned on.
T9 Backlight off to video off (backlight_off_delay)
Turning the backlight off can take a moment, so
this delay makes sure there is still valid video
data on the screen.
T10 Video off to power off (panel_power_down_delay)
Presumably this delay allows the panel to perform
an orderly shutdown of the display.
T11 + T12 Power off to power on (panel_power_cycle_delay)
So, once you turn the panel off, you have to wait a
while before you can turn it back on. This delay is
usually the longest in the entire sequence.
Neither the VBIOS source code nor the hardware documentation has a
clear mapping between the delay values they provide and those required
by the eDP spec. The VBIOS code actually uses two different labels for
the delay values in the five words of the relevant VBT table.
**** MORE LATER ***
Look at both the current hardware register settings and the VBT
specified panel power sequencing timings. Use the maximum of the two
delays, to make sure things work reliably. If there is no VBT data,
then those values will be initialized to zero, so we'll just use the
values as programmed in the hardware. Note that the BIOS just fetches
delays from the VBT table to place in the hardware registers, so we
should get the same values from both places, except for rounding.
VBT doesn't provide any values for T1 or T2, so we'll always just use
the hardware value for that.
The panel power up delay is thus T1 + T2 + T3, which should be
sufficient in all cases.
The panel power down delay is T1 + T2 + T12, using T1+T2 as a proxy
for T11, which isn't available anywhere.
For the backlight delays, the eDP spec says T6 + T8 is the delay from the
end of link training to backlight on and T9 is the delay from
backlight off until video off. The hardware provides a 'backlight on'
delay, which I'm taking to be T6 + T8 while the VBT provides something
called 'T7', which I'm assuming is s
On the macbook air I'm testing with, this yields a power-up delay of
over 200ms and a power-down delay of over 600ms. It all works now, but
we're frobbing these power controls several times during mode setting,
making the whole process take an awfully long time.
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-09-29 07:48:10 +08:00
|
|
|
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
|
2010-09-09 03:42:02 +08:00
|
|
|
intel_dp_start_link_train(intel_dp);
|
2014-01-17 21:39:48 +08:00
|
|
|
intel_edp_panel_on(intel_dp);
|
|
|
|
edp_panel_vdd_off(intel_dp, true);
|
2010-09-09 03:42:02 +08:00
|
|
|
intel_dp_complete_link_train(intel_dp);
|
2013-05-03 17:57:41 +08:00
|
|
|
intel_dp_stop_link_train(intel_dp);
|
2013-07-30 17:20:30 +08:00
|
|
|
}
|
2013-04-19 05:51:36 +08:00
|
|
|
|
2013-09-06 12:38:29 +08:00
|
|
|
static void g4x_enable_dp(struct intel_encoder *encoder)
|
|
|
|
{
|
2013-09-05 21:44:45 +08:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
|
|
|
|
2013-09-06 12:38:29 +08:00
|
|
|
intel_enable_dp(encoder);
|
2014-01-17 21:39:48 +08:00
|
|
|
intel_edp_backlight_on(intel_dp);
|
2013-07-30 17:20:30 +08:00
|
|
|
}
|
2013-04-19 05:51:36 +08:00
|
|
|
|
2013-07-30 17:20:30 +08:00
|
|
|
static void vlv_enable_dp(struct intel_encoder *encoder)
|
|
|
|
{
|
2013-09-05 21:44:45 +08:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
intel_edp_backlight_on(intel_dp);
|
2010-08-14 06:43:26 +08:00
|
|
|
}
|
|
|
|
|
2013-09-06 12:38:29 +08:00
|
|
|
static void g4x_pre_enable_dp(struct intel_encoder *encoder)
|
2013-07-30 17:20:30 +08:00
|
|
|
{
|
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
|
|
|
struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
|
|
|
|
|
2014-04-25 05:54:54 +08:00
|
|
|
intel_dp_prepare(encoder);
|
|
|
|
|
2014-04-25 05:54:53 +08:00
|
|
|
/* Only ilk+ has port A */
|
|
|
|
if (dport->port == PORT_A) {
|
|
|
|
ironlake_set_pll_cpu_edp(intel_dp);
|
2013-07-30 17:20:30 +08:00
|
|
|
ironlake_edp_pll_on(intel_dp);
|
2014-04-25 05:54:53 +08:00
|
|
|
}
|
2013-07-30 17:20:30 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void vlv_pre_enable_dp(struct intel_encoder *encoder)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2012-09-07 04:15:41 +08:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
2013-05-16 19:40:36 +08:00
|
|
|
struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
|
2013-03-29 00:55:40 +08:00
|
|
|
struct drm_device *dev = encoder->base.dev;
|
2013-04-19 05:51:36 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-07-30 17:20:30 +08:00
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
|
2013-11-06 14:36:35 +08:00
|
|
|
enum dpio_channel port = vlv_dport_to_channel(dport);
|
2013-07-30 17:20:30 +08:00
|
|
|
int pipe = intel_crtc->pipe;
|
2013-09-06 12:40:05 +08:00
|
|
|
struct edp_power_seq power_seq;
|
2013-07-30 17:20:30 +08:00
|
|
|
u32 val;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2013-07-30 17:20:30 +08:00
|
|
|
mutex_lock(&dev_priv->dpio_lock);
|
2013-04-19 05:51:36 +08:00
|
|
|
|
2013-11-07 10:43:30 +08:00
|
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
|
2013-07-30 17:20:30 +08:00
|
|
|
val = 0;
|
|
|
|
if (pipe)
|
|
|
|
val |= (1<<21);
|
|
|
|
else
|
|
|
|
val &= ~(1<<21);
|
|
|
|
val |= 0x001000c4;
|
2013-11-07 10:43:30 +08:00
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
|
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
|
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
|
2013-04-19 05:51:36 +08:00
|
|
|
|
2013-07-30 17:20:30 +08:00
|
|
|
mutex_unlock(&dev_priv->dpio_lock);
|
|
|
|
|
2014-01-30 22:50:42 +08:00
|
|
|
if (is_edp(intel_dp)) {
|
|
|
|
/* init power sequencer on this pipe and port */
|
|
|
|
intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
|
|
|
|
intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
|
|
|
|
&power_seq);
|
|
|
|
}
|
2013-09-06 12:40:05 +08:00
|
|
|
|
2013-07-30 17:20:30 +08:00
|
|
|
intel_enable_dp(encoder);
|
|
|
|
|
2013-11-06 14:36:35 +08:00
|
|
|
vlv_wait_port_ready(dev_priv, dport);
|
2013-04-19 05:51:36 +08:00
|
|
|
}
|
|
|
|
|
2013-09-06 12:38:29 +08:00
|
|
|
static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
|
2013-04-19 05:51:36 +08:00
|
|
|
{
|
|
|
|
struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
|
|
|
|
struct drm_device *dev = encoder->base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-09-05 20:41:49 +08:00
|
|
|
struct intel_crtc *intel_crtc =
|
|
|
|
to_intel_crtc(encoder->base.crtc);
|
2013-11-06 14:36:35 +08:00
|
|
|
enum dpio_channel port = vlv_dport_to_channel(dport);
|
2013-09-05 20:41:49 +08:00
|
|
|
int pipe = intel_crtc->pipe;
|
2013-04-19 05:51:36 +08:00
|
|
|
|
2014-04-25 05:54:54 +08:00
|
|
|
intel_dp_prepare(encoder);
|
|
|
|
|
2013-04-19 05:51:36 +08:00
|
|
|
/* Program Tx lane resets to default */
|
2013-07-27 02:57:35 +08:00
|
|
|
mutex_lock(&dev_priv->dpio_lock);
|
2013-11-07 10:43:30 +08:00
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
|
2013-04-19 05:51:36 +08:00
|
|
|
DPIO_PCS_TX_LANE2_RESET |
|
|
|
|
DPIO_PCS_TX_LANE1_RESET);
|
2013-11-07 10:43:30 +08:00
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
|
2013-04-19 05:51:36 +08:00
|
|
|
DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
|
|
|
|
DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
|
|
|
|
(1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
|
|
|
|
DPIO_PCS_CLK_SOFT_RESET);
|
|
|
|
|
|
|
|
/* Fix up inter-pair skew failure */
|
2013-11-07 10:43:30 +08:00
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
|
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
|
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
|
2013-07-27 02:57:35 +08:00
|
|
|
mutex_unlock(&dev_priv->dpio_lock);
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
2014-04-09 18:28:20 +08:00
|
|
|
static void chv_pre_enable_dp(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
|
|
|
|
struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_device *dev = encoder->base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct edp_power_seq power_seq;
|
|
|
|
struct intel_crtc *intel_crtc =
|
|
|
|
to_intel_crtc(encoder->base.crtc);
|
|
|
|
enum dpio_channel ch = vlv_dport_to_channel(dport);
|
|
|
|
int pipe = intel_crtc->pipe;
|
|
|
|
int data, i;
|
2014-04-09 18:28:58 +08:00
|
|
|
u32 val;
|
2014-04-09 18:28:20 +08:00
|
|
|
|
|
|
|
mutex_lock(&dev_priv->dpio_lock);
|
2014-04-09 18:28:58 +08:00
|
|
|
|
|
|
|
/* Deassert soft data lane reset*/
|
2014-04-09 18:29:02 +08:00
|
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
|
2014-04-28 19:15:24 +08:00
|
|
|
val |= CHV_PCS_REQ_SOFTRESET_EN;
|
2014-04-09 18:29:02 +08:00
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
|
|
|
|
|
|
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
|
|
|
|
val |= CHV_PCS_REQ_SOFTRESET_EN;
|
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
|
|
|
|
|
|
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
|
|
|
|
val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
|
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
|
2014-04-28 19:15:24 +08:00
|
|
|
|
2014-04-09 18:29:02 +08:00
|
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
|
2014-04-09 18:28:58 +08:00
|
|
|
val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
|
2014-04-09 18:29:02 +08:00
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
|
2014-04-09 18:28:58 +08:00
|
|
|
|
|
|
|
/* Program Tx lane latency optimal setting*/
|
2014-04-09 18:28:20 +08:00
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
/* Set the latency optimal bit */
|
|
|
|
data = (i == 1) ? 0x0 : 0x6;
|
|
|
|
vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
|
|
|
|
data << DPIO_FRC_LATENCY_SHFIT);
|
|
|
|
|
|
|
|
/* Set the upar bit */
|
|
|
|
data = (i == 1) ? 0x0 : 0x1;
|
|
|
|
vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
|
|
|
|
data << DPIO_UPAR_SHIFT);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Data lane stagger programming */
|
|
|
|
/* FIXME: Fix up value only after power analysis */
|
|
|
|
|
|
|
|
mutex_unlock(&dev_priv->dpio_lock);
|
|
|
|
|
|
|
|
if (is_edp(intel_dp)) {
|
|
|
|
/* init power sequencer on this pipe and port */
|
|
|
|
intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
|
|
|
|
intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
|
|
|
|
&power_seq);
|
|
|
|
}
|
|
|
|
|
|
|
|
intel_enable_dp(encoder);
|
|
|
|
|
|
|
|
vlv_wait_port_ready(dev_priv, dport);
|
|
|
|
}
|
|
|
|
|
2014-04-09 18:29:05 +08:00
|
|
|
static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
|
|
|
|
{
|
|
|
|
struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
|
|
|
|
struct drm_device *dev = encoder->base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct intel_crtc *intel_crtc =
|
|
|
|
to_intel_crtc(encoder->base.crtc);
|
|
|
|
enum dpio_channel ch = vlv_dport_to_channel(dport);
|
|
|
|
enum pipe pipe = intel_crtc->pipe;
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
mutex_lock(&dev_priv->dpio_lock);
|
|
|
|
|
2014-05-27 21:30:18 +08:00
|
|
|
/* program left/right clock distribution */
|
|
|
|
if (pipe != PIPE_B) {
|
|
|
|
val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
|
|
|
|
val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
|
|
|
|
if (ch == DPIO_CH0)
|
|
|
|
val |= CHV_BUFLEFTENA1_FORCE;
|
|
|
|
if (ch == DPIO_CH1)
|
|
|
|
val |= CHV_BUFRIGHTENA1_FORCE;
|
|
|
|
vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
|
|
|
|
} else {
|
|
|
|
val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
|
|
|
|
val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
|
|
|
|
if (ch == DPIO_CH0)
|
|
|
|
val |= CHV_BUFLEFTENA2_FORCE;
|
|
|
|
if (ch == DPIO_CH1)
|
|
|
|
val |= CHV_BUFRIGHTENA2_FORCE;
|
|
|
|
vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
|
|
|
|
}
|
|
|
|
|
2014-04-09 18:29:05 +08:00
|
|
|
/* program clock channel usage */
|
|
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
|
|
|
|
val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
|
|
|
|
if (pipe != PIPE_B)
|
|
|
|
val &= ~CHV_PCS_USEDCLKCHANNEL;
|
|
|
|
else
|
|
|
|
val |= CHV_PCS_USEDCLKCHANNEL;
|
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
|
|
|
|
|
|
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
|
|
|
|
val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
|
|
|
|
if (pipe != PIPE_B)
|
|
|
|
val &= ~CHV_PCS_USEDCLKCHANNEL;
|
|
|
|
else
|
|
|
|
val |= CHV_PCS_USEDCLKCHANNEL;
|
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This a a bit weird since generally CL
|
|
|
|
* matches the pipe, but here we need to
|
|
|
|
* pick the CL based on the port.
|
|
|
|
*/
|
|
|
|
val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
|
|
|
|
if (pipe != PIPE_B)
|
|
|
|
val &= ~CHV_CMN_USEDCLKCHANNEL;
|
|
|
|
else
|
|
|
|
val |= CHV_CMN_USEDCLKCHANNEL;
|
|
|
|
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
|
|
|
|
|
|
|
|
mutex_unlock(&dev_priv->dpio_lock);
|
|
|
|
}
|
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
/*
|
2011-07-08 02:11:02 +08:00
|
|
|
* Native read with retry for link status and receiver capability reads for
|
|
|
|
* cases where the sink may still be asleep.
|
2014-03-14 22:51:15 +08:00
|
|
|
*
|
|
|
|
* Sinks are *supposed* to come up within 1ms from an off state, but we're also
|
|
|
|
* supposed to retry 3 times per the spec.
|
2009-04-08 07:16:42 +08:00
|
|
|
*/
|
2014-03-14 22:51:15 +08:00
|
|
|
static ssize_t
|
|
|
|
intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
|
|
|
|
void *buffer, size_t size)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2014-03-14 22:51:15 +08:00
|
|
|
ssize_t ret;
|
|
|
|
int i;
|
2011-07-08 02:10:57 +08:00
|
|
|
|
|
|
|
for (i = 0; i < 3; i++) {
|
2014-03-14 22:51:15 +08:00
|
|
|
ret = drm_dp_dpcd_read(aux, offset, buffer, size);
|
|
|
|
if (ret == size)
|
|
|
|
return ret;
|
2011-07-08 02:10:57 +08:00
|
|
|
msleep(1);
|
|
|
|
}
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2014-03-14 22:51:15 +08:00
|
|
|
return ret;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Fetch AUX CH registers 0x202 - 0x207 which contain
|
|
|
|
* link status information
|
|
|
|
*/
|
|
|
|
static bool
|
2011-11-02 10:45:03 +08:00
|
|
|
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2014-03-14 22:51:15 +08:00
|
|
|
return intel_dp_dpcd_read_wake(&intel_dp->aux,
|
|
|
|
DP_LANE0_1_STATUS,
|
|
|
|
link_status,
|
|
|
|
DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
2014-06-14 05:45:41 +08:00
|
|
|
/* These are source-specific values. */
|
2009-04-08 07:16:42 +08:00
|
|
|
static uint8_t
|
2011-11-17 08:26:07 +08:00
|
|
|
intel_dp_voltage_max(struct intel_dp *intel_dp)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2013-05-16 19:40:36 +08:00
|
|
|
enum port port = dp_to_dig_port(intel_dp)->port;
|
2011-11-17 08:26:07 +08:00
|
|
|
|
2014-06-14 05:45:40 +08:00
|
|
|
if (IS_VALLEYVIEW(dev))
|
2013-04-19 05:44:28 +08:00
|
|
|
return DP_TRAIN_VOLTAGE_SWING_1200;
|
2013-05-16 19:40:36 +08:00
|
|
|
else if (IS_GEN7(dev) && port == PORT_A)
|
2011-11-17 08:26:07 +08:00
|
|
|
return DP_TRAIN_VOLTAGE_SWING_800;
|
2013-05-16 19:40:36 +08:00
|
|
|
else if (HAS_PCH_CPT(dev) && port != PORT_A)
|
2011-11-17 08:26:07 +08:00
|
|
|
return DP_TRAIN_VOLTAGE_SWING_1200;
|
|
|
|
else
|
|
|
|
return DP_TRAIN_VOLTAGE_SWING_800;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint8_t
|
|
|
|
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
|
|
|
|
{
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2013-05-16 19:40:36 +08:00
|
|
|
enum port port = dp_to_dig_port(intel_dp)->port;
|
2011-11-17 08:26:07 +08:00
|
|
|
|
2014-06-14 05:45:40 +08:00
|
|
|
if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
|
2012-10-16 02:51:34 +08:00
|
|
|
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_9_5;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_6;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_3_5;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_1200:
|
|
|
|
default:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_0;
|
|
|
|
}
|
2013-04-19 05:44:28 +08:00
|
|
|
} else if (IS_VALLEYVIEW(dev)) {
|
|
|
|
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_9_5;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_6;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_3_5;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_1200:
|
|
|
|
default:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_0;
|
|
|
|
}
|
2013-05-16 19:40:36 +08:00
|
|
|
} else if (IS_GEN7(dev) && port == PORT_A) {
|
2011-11-17 08:26:07 +08:00
|
|
|
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_6;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600:
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_3_5;
|
|
|
|
default:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_0;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_6;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_6;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_3_5;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_1200:
|
|
|
|
default:
|
|
|
|
return DP_TRAIN_PRE_EMPHASIS_0;
|
|
|
|
}
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-04-19 05:44:28 +08:00
|
|
|
static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
|
2013-09-05 20:41:49 +08:00
|
|
|
struct intel_crtc *intel_crtc =
|
|
|
|
to_intel_crtc(dport->base.base.crtc);
|
2013-04-19 05:44:28 +08:00
|
|
|
unsigned long demph_reg_value, preemph_reg_value,
|
|
|
|
uniqtranscale_reg_value;
|
|
|
|
uint8_t train_set = intel_dp->train_set[0];
|
2013-11-06 14:36:35 +08:00
|
|
|
enum dpio_channel port = vlv_dport_to_channel(dport);
|
2013-09-05 20:41:49 +08:00
|
|
|
int pipe = intel_crtc->pipe;
|
2013-04-19 05:44:28 +08:00
|
|
|
|
|
|
|
switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
|
|
|
|
case DP_TRAIN_PRE_EMPHASIS_0:
|
|
|
|
preemph_reg_value = 0x0004000;
|
|
|
|
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400:
|
|
|
|
demph_reg_value = 0x2B405555;
|
|
|
|
uniqtranscale_reg_value = 0x552AB83A;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600:
|
|
|
|
demph_reg_value = 0x2B404040;
|
|
|
|
uniqtranscale_reg_value = 0x5548B83A;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800:
|
|
|
|
demph_reg_value = 0x2B245555;
|
|
|
|
uniqtranscale_reg_value = 0x5560B83A;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_1200:
|
|
|
|
demph_reg_value = 0x2B405555;
|
|
|
|
uniqtranscale_reg_value = 0x5598DA3A;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_PRE_EMPHASIS_3_5:
|
|
|
|
preemph_reg_value = 0x0002000;
|
|
|
|
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400:
|
|
|
|
demph_reg_value = 0x2B404040;
|
|
|
|
uniqtranscale_reg_value = 0x5552B83A;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600:
|
|
|
|
demph_reg_value = 0x2B404848;
|
|
|
|
uniqtranscale_reg_value = 0x5580B83A;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800:
|
|
|
|
demph_reg_value = 0x2B404040;
|
|
|
|
uniqtranscale_reg_value = 0x55ADDA3A;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_PRE_EMPHASIS_6:
|
|
|
|
preemph_reg_value = 0x0000000;
|
|
|
|
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400:
|
|
|
|
demph_reg_value = 0x2B305555;
|
|
|
|
uniqtranscale_reg_value = 0x5570B83A;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600:
|
|
|
|
demph_reg_value = 0x2B2B4040;
|
|
|
|
uniqtranscale_reg_value = 0x55ADDA3A;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_PRE_EMPHASIS_9_5:
|
|
|
|
preemph_reg_value = 0x0006000;
|
|
|
|
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400:
|
|
|
|
demph_reg_value = 0x1B405555;
|
|
|
|
uniqtranscale_reg_value = 0x55ADDA3A;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-07-27 02:57:35 +08:00
|
|
|
mutex_lock(&dev_priv->dpio_lock);
|
2013-11-07 10:43:30 +08:00
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
|
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
|
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
|
2013-04-19 05:44:28 +08:00
|
|
|
uniqtranscale_reg_value);
|
2013-11-07 10:43:30 +08:00
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
|
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
|
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
|
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
|
2013-07-27 02:57:35 +08:00
|
|
|
mutex_unlock(&dev_priv->dpio_lock);
|
2013-04-19 05:44:28 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-04-09 18:28:20 +08:00
|
|
|
static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
|
|
|
|
struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
|
2014-04-09 18:29:03 +08:00
|
|
|
u32 deemph_reg_value, margin_reg_value, val;
|
2014-04-09 18:28:20 +08:00
|
|
|
uint8_t train_set = intel_dp->train_set[0];
|
|
|
|
enum dpio_channel ch = vlv_dport_to_channel(dport);
|
2014-04-09 18:29:03 +08:00
|
|
|
enum pipe pipe = intel_crtc->pipe;
|
|
|
|
int i;
|
2014-04-09 18:28:20 +08:00
|
|
|
|
|
|
|
switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
|
|
|
|
case DP_TRAIN_PRE_EMPHASIS_0:
|
|
|
|
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400:
|
|
|
|
deemph_reg_value = 128;
|
|
|
|
margin_reg_value = 52;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600:
|
|
|
|
deemph_reg_value = 128;
|
|
|
|
margin_reg_value = 77;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800:
|
|
|
|
deemph_reg_value = 128;
|
|
|
|
margin_reg_value = 102;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_1200:
|
|
|
|
deemph_reg_value = 128;
|
|
|
|
margin_reg_value = 154;
|
|
|
|
/* FIXME extra to set for 1200 */
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_PRE_EMPHASIS_3_5:
|
|
|
|
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400:
|
|
|
|
deemph_reg_value = 85;
|
|
|
|
margin_reg_value = 78;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600:
|
|
|
|
deemph_reg_value = 85;
|
|
|
|
margin_reg_value = 116;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800:
|
|
|
|
deemph_reg_value = 85;
|
|
|
|
margin_reg_value = 154;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_PRE_EMPHASIS_6:
|
|
|
|
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400:
|
|
|
|
deemph_reg_value = 64;
|
|
|
|
margin_reg_value = 104;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600:
|
|
|
|
deemph_reg_value = 64;
|
|
|
|
margin_reg_value = 154;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_PRE_EMPHASIS_9_5:
|
|
|
|
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400:
|
|
|
|
deemph_reg_value = 43;
|
|
|
|
margin_reg_value = 154;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
mutex_lock(&dev_priv->dpio_lock);
|
|
|
|
|
|
|
|
/* Clear calc init */
|
2014-04-09 18:29:04 +08:00
|
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
|
|
|
|
val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
|
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
|
|
|
|
|
|
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
|
|
|
|
val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
|
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
|
2014-04-09 18:28:20 +08:00
|
|
|
|
|
|
|
/* Program swing deemph */
|
2014-04-09 18:29:03 +08:00
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
|
|
|
|
val &= ~DPIO_SWING_DEEMPH9P5_MASK;
|
|
|
|
val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
|
|
|
|
vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
|
|
|
|
}
|
2014-04-09 18:28:20 +08:00
|
|
|
|
|
|
|
/* Program swing margin */
|
2014-04-09 18:29:03 +08:00
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
|
|
|
|
val &= ~DPIO_SWING_MARGIN_MASK;
|
|
|
|
val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
|
|
|
|
vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
|
|
|
|
}
|
2014-04-09 18:28:20 +08:00
|
|
|
|
|
|
|
/* Disable unique transition scale */
|
2014-04-09 18:29:03 +08:00
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
|
|
|
|
val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
|
|
|
|
vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
|
|
|
|
}
|
2014-04-09 18:28:20 +08:00
|
|
|
|
|
|
|
if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
|
|
|
|
== DP_TRAIN_PRE_EMPHASIS_0) &&
|
|
|
|
((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
|
|
|
|
== DP_TRAIN_VOLTAGE_SWING_1200)) {
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The document said it needs to set bit 27 for ch0 and bit 26
|
|
|
|
* for ch1. Might be a typo in the doc.
|
|
|
|
* For now, for this unique transition scale selection, set bit
|
|
|
|
* 27 for ch0 and ch1.
|
|
|
|
*/
|
2014-04-09 18:29:03 +08:00
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
|
|
|
|
val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
|
|
|
|
vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
|
|
|
|
}
|
2014-04-09 18:28:20 +08:00
|
|
|
|
2014-04-09 18:29:03 +08:00
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
|
|
|
|
val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
|
|
|
|
val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
|
|
|
|
vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
|
|
|
|
}
|
2014-04-09 18:28:20 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Start swing calculation */
|
2014-04-09 18:29:04 +08:00
|
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
|
|
|
|
val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
|
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
|
|
|
|
|
|
|
|
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
|
|
|
|
val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
|
|
|
|
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
|
2014-04-09 18:28:20 +08:00
|
|
|
|
|
|
|
/* LRC Bypass */
|
|
|
|
val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
|
|
|
|
val |= DPIO_LRC_BYPASS;
|
|
|
|
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
|
|
|
|
|
|
|
|
mutex_unlock(&dev_priv->dpio_lock);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
static void
|
2013-10-15 14:36:08 +08:00
|
|
|
intel_get_adjust_train(struct intel_dp *intel_dp,
|
|
|
|
const uint8_t link_status[DP_LINK_STATUS_SIZE])
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
|
|
|
uint8_t v = 0;
|
|
|
|
uint8_t p = 0;
|
|
|
|
int lane;
|
2011-11-17 08:26:07 +08:00
|
|
|
uint8_t voltage_max;
|
|
|
|
uint8_t preemph_max;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2010-09-09 03:42:02 +08:00
|
|
|
for (lane = 0; lane < intel_dp->lane_count; lane++) {
|
2012-10-18 16:15:27 +08:00
|
|
|
uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
|
|
|
|
uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
|
2009-04-08 07:16:42 +08:00
|
|
|
|
|
|
|
if (this_v > v)
|
|
|
|
v = this_v;
|
|
|
|
if (this_p > p)
|
|
|
|
p = this_p;
|
|
|
|
}
|
|
|
|
|
2011-11-17 08:26:07 +08:00
|
|
|
voltage_max = intel_dp_voltage_max(intel_dp);
|
2011-11-02 10:54:11 +08:00
|
|
|
if (v >= voltage_max)
|
|
|
|
v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2011-11-17 08:26:07 +08:00
|
|
|
preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
|
|
|
|
if (p >= preemph_max)
|
|
|
|
p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
|
|
|
for (lane = 0; lane < 4; lane++)
|
2010-09-09 03:42:02 +08:00
|
|
|
intel_dp->train_set[lane] = v | p;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t
|
2012-12-07 02:51:50 +08:00
|
|
|
intel_gen4_signal_levels(uint8_t train_set)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2010-11-29 18:09:55 +08:00
|
|
|
uint32_t signal_levels = 0;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2010-11-29 18:09:55 +08:00
|
|
|
switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
|
2009-04-08 07:16:42 +08:00
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400:
|
|
|
|
default:
|
|
|
|
signal_levels |= DP_VOLTAGE_0_4;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600:
|
|
|
|
signal_levels |= DP_VOLTAGE_0_6;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800:
|
|
|
|
signal_levels |= DP_VOLTAGE_0_8;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_1200:
|
|
|
|
signal_levels |= DP_VOLTAGE_1_2;
|
|
|
|
break;
|
|
|
|
}
|
2010-11-29 18:09:55 +08:00
|
|
|
switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
|
2009-04-08 07:16:42 +08:00
|
|
|
case DP_TRAIN_PRE_EMPHASIS_0:
|
|
|
|
default:
|
|
|
|
signal_levels |= DP_PRE_EMPHASIS_0;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_PRE_EMPHASIS_3_5:
|
|
|
|
signal_levels |= DP_PRE_EMPHASIS_3_5;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_PRE_EMPHASIS_6:
|
|
|
|
signal_levels |= DP_PRE_EMPHASIS_6;
|
|
|
|
break;
|
|
|
|
case DP_TRAIN_PRE_EMPHASIS_9_5:
|
|
|
|
signal_levels |= DP_PRE_EMPHASIS_9_5;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return signal_levels;
|
|
|
|
}
|
|
|
|
|
2010-04-08 09:43:27 +08:00
|
|
|
/* Gen6's DP voltage swing and pre-emphasis control */
|
|
|
|
static uint32_t
|
|
|
|
intel_gen6_edp_signal_levels(uint8_t train_set)
|
|
|
|
{
|
2011-01-06 18:26:08 +08:00
|
|
|
int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
|
|
|
|
DP_TRAIN_PRE_EMPHASIS_MASK);
|
|
|
|
switch (signal_levels) {
|
2010-04-08 09:43:27 +08:00
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
|
2011-01-06 18:26:08 +08:00
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
|
|
|
|
return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
|
|
|
|
return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
|
2010-04-08 09:43:27 +08:00
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
|
2011-01-06 18:26:08 +08:00
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
|
|
|
|
return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
|
2010-04-08 09:43:27 +08:00
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
|
2011-01-06 18:26:08 +08:00
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
|
|
|
|
return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
|
2010-04-08 09:43:27 +08:00
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
|
2011-01-06 18:26:08 +08:00
|
|
|
case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
|
|
|
|
return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
|
2010-04-08 09:43:27 +08:00
|
|
|
default:
|
2011-01-06 18:26:08 +08:00
|
|
|
DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
|
|
|
|
"0x%x\n", signal_levels);
|
|
|
|
return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
|
2010-04-08 09:43:27 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-11-17 08:26:07 +08:00
|
|
|
/* Gen7's DP voltage swing and pre-emphasis control */
|
|
|
|
static uint32_t
|
|
|
|
intel_gen7_edp_signal_levels(uint8_t train_set)
|
|
|
|
{
|
|
|
|
int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
|
|
|
|
DP_TRAIN_PRE_EMPHASIS_MASK);
|
|
|
|
switch (signal_levels) {
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
|
|
|
|
return EDP_LINK_TRAIN_400MV_0DB_IVB;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
|
|
|
|
return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
|
|
|
|
return EDP_LINK_TRAIN_400MV_6DB_IVB;
|
|
|
|
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
|
|
|
|
return EDP_LINK_TRAIN_600MV_0DB_IVB;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
|
|
|
|
return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
|
|
|
|
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
|
|
|
|
return EDP_LINK_TRAIN_800MV_0DB_IVB;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
|
|
|
|
return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
|
|
|
|
|
|
|
|
default:
|
|
|
|
DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
|
|
|
|
"0x%x\n", signal_levels);
|
|
|
|
return EDP_LINK_TRAIN_500MV_0DB_IVB;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-16 02:51:34 +08:00
|
|
|
/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
|
|
|
|
static uint32_t
|
2012-12-07 02:51:50 +08:00
|
|
|
intel_hsw_signal_levels(uint8_t train_set)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2012-10-16 02:51:34 +08:00
|
|
|
int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
|
|
|
|
DP_TRAIN_PRE_EMPHASIS_MASK);
|
|
|
|
switch (signal_levels) {
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
|
|
|
|
return DDI_BUF_EMP_400MV_0DB_HSW;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
|
|
|
|
return DDI_BUF_EMP_400MV_3_5DB_HSW;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
|
|
|
|
return DDI_BUF_EMP_400MV_6DB_HSW;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
|
|
|
|
return DDI_BUF_EMP_400MV_9_5DB_HSW;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2012-10-16 02:51:34 +08:00
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
|
|
|
|
return DDI_BUF_EMP_600MV_0DB_HSW;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
|
|
|
|
return DDI_BUF_EMP_600MV_3_5DB_HSW;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
|
|
|
|
return DDI_BUF_EMP_600MV_6DB_HSW;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2012-10-16 02:51:34 +08:00
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
|
|
|
|
return DDI_BUF_EMP_800MV_0DB_HSW;
|
|
|
|
case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
|
|
|
|
return DDI_BUF_EMP_800MV_3_5DB_HSW;
|
|
|
|
default:
|
|
|
|
DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
|
|
|
|
"0x%x\n", signal_levels);
|
|
|
|
return DDI_BUF_EMP_400MV_0DB_HSW;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-12-07 02:51:50 +08:00
|
|
|
/* Properly updates "DP" with the correct signal levels. */
|
|
|
|
static void
|
|
|
|
intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
|
|
|
|
{
|
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
2013-05-16 19:40:36 +08:00
|
|
|
enum port port = intel_dig_port->port;
|
2012-12-07 02:51:50 +08:00
|
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
|
|
|
uint32_t signal_levels, mask;
|
|
|
|
uint8_t train_set = intel_dp->train_set[0];
|
|
|
|
|
2014-06-14 05:45:40 +08:00
|
|
|
if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
|
2012-12-07 02:51:50 +08:00
|
|
|
signal_levels = intel_hsw_signal_levels(train_set);
|
|
|
|
mask = DDI_BUF_EMP_MASK;
|
2014-04-09 18:28:20 +08:00
|
|
|
} else if (IS_CHERRYVIEW(dev)) {
|
|
|
|
signal_levels = intel_chv_signal_levels(intel_dp);
|
|
|
|
mask = 0;
|
2013-04-19 05:44:28 +08:00
|
|
|
} else if (IS_VALLEYVIEW(dev)) {
|
|
|
|
signal_levels = intel_vlv_signal_levels(intel_dp);
|
|
|
|
mask = 0;
|
2013-05-16 19:40:36 +08:00
|
|
|
} else if (IS_GEN7(dev) && port == PORT_A) {
|
2012-12-07 02:51:50 +08:00
|
|
|
signal_levels = intel_gen7_edp_signal_levels(train_set);
|
|
|
|
mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
|
2013-05-16 19:40:36 +08:00
|
|
|
} else if (IS_GEN6(dev) && port == PORT_A) {
|
2012-12-07 02:51:50 +08:00
|
|
|
signal_levels = intel_gen6_edp_signal_levels(train_set);
|
|
|
|
mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
|
|
|
|
} else {
|
|
|
|
signal_levels = intel_gen4_signal_levels(train_set);
|
|
|
|
mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
|
|
|
|
}
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
|
|
|
|
|
|
|
|
*DP = (*DP & ~mask) | signal_levels;
|
|
|
|
}
|
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
static bool
|
2010-08-04 20:50:23 +08:00
|
|
|
intel_dp_set_link_train(struct intel_dp *intel_dp,
|
2013-09-27 20:10:44 +08:00
|
|
|
uint32_t *DP,
|
2010-10-03 17:56:11 +08:00
|
|
|
uint8_t dp_train_pat)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2012-10-27 05:05:50 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
2009-04-08 07:16:42 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-10-27 05:05:50 +08:00
|
|
|
enum port port = intel_dig_port->port;
|
2013-10-04 20:08:48 +08:00
|
|
|
uint8_t buf[sizeof(intel_dp->train_set) + 1];
|
|
|
|
int ret, len;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2013-02-19 06:00:23 +08:00
|
|
|
if (HAS_DDI(dev)) {
|
2013-05-03 17:57:41 +08:00
|
|
|
uint32_t temp = I915_READ(DP_TP_CTL(port));
|
2012-10-16 02:51:34 +08:00
|
|
|
|
|
|
|
if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
|
|
|
|
temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
|
|
|
|
else
|
|
|
|
temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
|
|
|
|
|
|
|
|
temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
|
|
|
|
switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
|
|
|
|
case DP_TRAINING_PATTERN_DISABLE:
|
|
|
|
temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
|
|
|
|
|
|
|
|
break;
|
|
|
|
case DP_TRAINING_PATTERN_1:
|
|
|
|
temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
|
|
|
|
break;
|
|
|
|
case DP_TRAINING_PATTERN_2:
|
|
|
|
temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
|
|
|
|
break;
|
|
|
|
case DP_TRAINING_PATTERN_3:
|
|
|
|
temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
|
|
|
|
break;
|
|
|
|
}
|
2012-10-27 05:05:50 +08:00
|
|
|
I915_WRITE(DP_TP_CTL(port), temp);
|
2012-10-16 02:51:34 +08:00
|
|
|
|
2013-05-16 19:40:36 +08:00
|
|
|
} else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
|
2013-09-27 20:10:44 +08:00
|
|
|
*DP &= ~DP_LINK_TRAIN_MASK_CPT;
|
2012-07-18 03:55:16 +08:00
|
|
|
|
|
|
|
switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
|
|
|
|
case DP_TRAINING_PATTERN_DISABLE:
|
2013-09-27 20:10:44 +08:00
|
|
|
*DP |= DP_LINK_TRAIN_OFF_CPT;
|
2012-07-18 03:55:16 +08:00
|
|
|
break;
|
|
|
|
case DP_TRAINING_PATTERN_1:
|
2013-09-27 20:10:44 +08:00
|
|
|
*DP |= DP_LINK_TRAIN_PAT_1_CPT;
|
2012-07-18 03:55:16 +08:00
|
|
|
break;
|
|
|
|
case DP_TRAINING_PATTERN_2:
|
2013-09-27 20:10:44 +08:00
|
|
|
*DP |= DP_LINK_TRAIN_PAT_2_CPT;
|
2012-07-18 03:55:16 +08:00
|
|
|
break;
|
|
|
|
case DP_TRAINING_PATTERN_3:
|
|
|
|
DRM_ERROR("DP training pattern 3 not supported\n");
|
2013-09-27 20:10:44 +08:00
|
|
|
*DP |= DP_LINK_TRAIN_PAT_2_CPT;
|
2012-07-18 03:55:16 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
} else {
|
2013-09-27 20:10:44 +08:00
|
|
|
*DP &= ~DP_LINK_TRAIN_MASK;
|
2012-07-18 03:55:16 +08:00
|
|
|
|
|
|
|
switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
|
|
|
|
case DP_TRAINING_PATTERN_DISABLE:
|
2013-09-27 20:10:44 +08:00
|
|
|
*DP |= DP_LINK_TRAIN_OFF;
|
2012-07-18 03:55:16 +08:00
|
|
|
break;
|
|
|
|
case DP_TRAINING_PATTERN_1:
|
2013-09-27 20:10:44 +08:00
|
|
|
*DP |= DP_LINK_TRAIN_PAT_1;
|
2012-07-18 03:55:16 +08:00
|
|
|
break;
|
|
|
|
case DP_TRAINING_PATTERN_2:
|
2013-09-27 20:10:44 +08:00
|
|
|
*DP |= DP_LINK_TRAIN_PAT_2;
|
2012-07-18 03:55:16 +08:00
|
|
|
break;
|
|
|
|
case DP_TRAINING_PATTERN_3:
|
|
|
|
DRM_ERROR("DP training pattern 3 not supported\n");
|
2013-09-27 20:10:44 +08:00
|
|
|
*DP |= DP_LINK_TRAIN_PAT_2;
|
2012-07-18 03:55:16 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-09-27 20:10:44 +08:00
|
|
|
I915_WRITE(intel_dp->output_reg, *DP);
|
2010-08-04 20:50:23 +08:00
|
|
|
POSTING_READ(intel_dp->output_reg);
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2013-10-04 20:08:48 +08:00
|
|
|
buf[0] = dp_train_pat;
|
|
|
|
if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
|
2012-07-18 03:55:16 +08:00
|
|
|
DP_TRAINING_PATTERN_DISABLE) {
|
2013-10-04 20:08:48 +08:00
|
|
|
/* don't write DP_TRAINING_LANEx_SET on disable */
|
|
|
|
len = 1;
|
|
|
|
} else {
|
|
|
|
/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
|
|
|
|
memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
|
|
|
|
len = intel_dp->lane_count + 1;
|
2012-07-18 03:55:16 +08:00
|
|
|
}
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2014-03-14 22:51:15 +08:00
|
|
|
ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
|
|
|
|
buf, len);
|
2013-10-04 20:08:48 +08:00
|
|
|
|
|
|
|
return ret == len;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
2013-09-27 20:10:44 +08:00
|
|
|
static bool
|
|
|
|
intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
|
|
|
|
uint8_t dp_train_pat)
|
|
|
|
{
|
2013-10-04 20:08:47 +08:00
|
|
|
memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
|
2013-09-27 20:10:44 +08:00
|
|
|
intel_dp_set_signal_levels(intel_dp, DP);
|
|
|
|
return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool
|
|
|
|
intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
|
2013-10-15 14:36:08 +08:00
|
|
|
const uint8_t link_status[DP_LINK_STATUS_SIZE])
|
2013-09-27 20:10:44 +08:00
|
|
|
{
|
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
intel_get_adjust_train(intel_dp, link_status);
|
|
|
|
intel_dp_set_signal_levels(intel_dp, DP);
|
|
|
|
|
|
|
|
I915_WRITE(intel_dp->output_reg, *DP);
|
|
|
|
POSTING_READ(intel_dp->output_reg);
|
|
|
|
|
2014-03-14 22:51:15 +08:00
|
|
|
ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
|
|
|
|
intel_dp->train_set, intel_dp->lane_count);
|
2013-09-27 20:10:44 +08:00
|
|
|
|
|
|
|
return ret == intel_dp->lane_count;
|
|
|
|
}
|
|
|
|
|
2013-05-03 17:57:41 +08:00
|
|
|
static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
enum port port = intel_dig_port->port;
|
|
|
|
uint32_t val;
|
|
|
|
|
|
|
|
if (!HAS_DDI(dev))
|
|
|
|
return;
|
|
|
|
|
|
|
|
val = I915_READ(DP_TP_CTL(port));
|
|
|
|
val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
|
|
|
|
val |= DP_TP_CTL_LINK_TRAIN_IDLE;
|
|
|
|
I915_WRITE(DP_TP_CTL(port), val);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* On PORT_A we can have only eDP in SST mode. There the only reason
|
|
|
|
* we need to set idle transmission mode is to work around a HW issue
|
|
|
|
* where we enable the pipe while not in idle link-training mode.
|
|
|
|
* In this case there is requirement to wait for a minimum number of
|
|
|
|
* idle patterns to be sent.
|
|
|
|
*/
|
|
|
|
if (port == PORT_A)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
|
|
|
|
1))
|
|
|
|
DRM_ERROR("Timed out waiting for DP idle patterns\n");
|
|
|
|
}
|
|
|
|
|
2010-09-09 03:42:02 +08:00
|
|
|
/* Enable corresponding port and start training pattern 1 */
|
2012-10-16 02:51:41 +08:00
|
|
|
void
|
2010-09-09 03:42:02 +08:00
|
|
|
intel_dp_start_link_train(struct intel_dp *intel_dp)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2012-10-27 05:05:46 +08:00
|
|
|
struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
|
2012-10-16 02:51:41 +08:00
|
|
|
struct drm_device *dev = encoder->dev;
|
2009-04-08 07:16:42 +08:00
|
|
|
int i;
|
|
|
|
uint8_t voltage;
|
2011-11-02 11:00:06 +08:00
|
|
|
int voltage_tries, loop_tries;
|
2010-08-04 20:50:23 +08:00
|
|
|
uint32_t DP = intel_dp->DP;
|
2013-10-04 20:08:10 +08:00
|
|
|
uint8_t link_config[2];
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2012-11-24 01:30:39 +08:00
|
|
|
if (HAS_DDI(dev))
|
2012-10-16 02:51:41 +08:00
|
|
|
intel_ddi_prepare_link_retrain(encoder);
|
|
|
|
|
2010-11-29 18:09:55 +08:00
|
|
|
/* Write the link configuration data */
|
2013-10-04 20:08:10 +08:00
|
|
|
link_config[0] = intel_dp->link_bw;
|
|
|
|
link_config[1] = intel_dp->lane_count;
|
|
|
|
if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
|
|
|
|
link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
|
2014-03-14 22:51:15 +08:00
|
|
|
drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
|
2013-10-04 20:08:10 +08:00
|
|
|
|
|
|
|
link_config[0] = 0;
|
|
|
|
link_config[1] = DP_SET_ANSI_8B10B;
|
2014-03-14 22:51:15 +08:00
|
|
|
drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
|
2009-04-08 07:16:42 +08:00
|
|
|
|
|
|
|
DP |= DP_PORT_EN;
|
2011-11-17 08:26:07 +08:00
|
|
|
|
2013-09-27 20:10:44 +08:00
|
|
|
/* clock recovery */
|
|
|
|
if (!intel_dp_reset_link_train(intel_dp, &DP,
|
|
|
|
DP_TRAINING_PATTERN_1 |
|
|
|
|
DP_LINK_SCRAMBLING_DISABLE)) {
|
|
|
|
DRM_ERROR("failed to enable link training\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
voltage = 0xff;
|
2011-11-02 11:00:06 +08:00
|
|
|
voltage_tries = 0;
|
|
|
|
loop_tries = 0;
|
2009-04-08 07:16:42 +08:00
|
|
|
for (;;) {
|
2013-09-27 20:10:44 +08:00
|
|
|
uint8_t link_status[DP_LINK_STATUS_SIZE];
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2012-10-18 16:15:30 +08:00
|
|
|
drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
|
2011-11-02 10:45:03 +08:00
|
|
|
if (!intel_dp_get_link_status(intel_dp, link_status)) {
|
|
|
|
DRM_ERROR("failed to get link status\n");
|
2009-04-08 07:16:42 +08:00
|
|
|
break;
|
2011-11-02 10:45:03 +08:00
|
|
|
}
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2012-10-18 16:15:25 +08:00
|
|
|
if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
|
2011-11-02 10:45:03 +08:00
|
|
|
DRM_DEBUG_KMS("clock recovery OK\n");
|
2010-11-29 18:09:55 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check to see if we've tried the max voltage */
|
|
|
|
for (i = 0; i < intel_dp->lane_count; i++)
|
|
|
|
if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
|
2009-04-08 07:16:42 +08:00
|
|
|
break;
|
2013-03-12 01:40:16 +08:00
|
|
|
if (i == intel_dp->lane_count) {
|
2012-10-16 15:50:25 +08:00
|
|
|
++loop_tries;
|
|
|
|
if (loop_tries == 5) {
|
2013-10-05 21:13:56 +08:00
|
|
|
DRM_ERROR("too many full retries, give up\n");
|
2011-11-02 11:00:06 +08:00
|
|
|
break;
|
|
|
|
}
|
2013-09-27 20:10:44 +08:00
|
|
|
intel_dp_reset_link_train(intel_dp, &DP,
|
|
|
|
DP_TRAINING_PATTERN_1 |
|
|
|
|
DP_LINK_SCRAMBLING_DISABLE);
|
2011-11-02 11:00:06 +08:00
|
|
|
voltage_tries = 0;
|
|
|
|
continue;
|
|
|
|
}
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2010-11-29 18:09:55 +08:00
|
|
|
/* Check to see if we've tried the same voltage 5 times */
|
2012-10-16 15:50:25 +08:00
|
|
|
if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
|
2012-09-26 23:48:30 +08:00
|
|
|
++voltage_tries;
|
2012-10-16 15:50:25 +08:00
|
|
|
if (voltage_tries == 5) {
|
2013-10-05 21:13:56 +08:00
|
|
|
DRM_ERROR("too many voltage retries, give up\n");
|
2012-10-16 15:50:25 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else
|
|
|
|
voltage_tries = 0;
|
|
|
|
voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2013-09-27 20:10:44 +08:00
|
|
|
/* Update training set as requested by target */
|
|
|
|
if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
|
|
|
|
DRM_ERROR("failed to update link training\n");
|
|
|
|
break;
|
|
|
|
}
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
2010-09-09 03:42:02 +08:00
|
|
|
intel_dp->DP = DP;
|
|
|
|
}
|
|
|
|
|
2012-10-16 02:51:41 +08:00
|
|
|
void
|
2010-09-09 03:42:02 +08:00
|
|
|
intel_dp_complete_link_train(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
bool channel_eq = false;
|
2011-01-06 06:45:24 +08:00
|
|
|
int tries, cr_tries;
|
2010-09-09 03:42:02 +08:00
|
|
|
uint32_t DP = intel_dp->DP;
|
2014-01-21 01:19:39 +08:00
|
|
|
uint32_t training_pattern = DP_TRAINING_PATTERN_2;
|
|
|
|
|
|
|
|
/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
|
|
|
|
if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
|
|
|
|
training_pattern = DP_TRAINING_PATTERN_3;
|
2010-09-09 03:42:02 +08:00
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
/* channel equalization */
|
2013-09-27 20:10:44 +08:00
|
|
|
if (!intel_dp_set_link_train(intel_dp, &DP,
|
2014-01-21 01:19:39 +08:00
|
|
|
training_pattern |
|
2013-09-27 20:10:44 +08:00
|
|
|
DP_LINK_SCRAMBLING_DISABLE)) {
|
|
|
|
DRM_ERROR("failed to start channel equalization\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
tries = 0;
|
2011-01-06 06:45:24 +08:00
|
|
|
cr_tries = 0;
|
2009-04-08 07:16:42 +08:00
|
|
|
channel_eq = false;
|
|
|
|
for (;;) {
|
2013-09-27 20:10:44 +08:00
|
|
|
uint8_t link_status[DP_LINK_STATUS_SIZE];
|
2010-04-08 09:43:27 +08:00
|
|
|
|
2011-01-06 06:45:24 +08:00
|
|
|
if (cr_tries > 5) {
|
|
|
|
DRM_ERROR("failed to train DP, aborting\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2012-10-18 16:15:30 +08:00
|
|
|
drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
|
2013-09-27 20:10:44 +08:00
|
|
|
if (!intel_dp_get_link_status(intel_dp, link_status)) {
|
|
|
|
DRM_ERROR("failed to get link status\n");
|
2009-04-08 07:16:42 +08:00
|
|
|
break;
|
2013-09-27 20:10:44 +08:00
|
|
|
}
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2011-01-06 06:45:24 +08:00
|
|
|
/* Make sure clock is still ok */
|
2012-10-18 16:15:25 +08:00
|
|
|
if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
|
2011-01-06 06:45:24 +08:00
|
|
|
intel_dp_start_link_train(intel_dp);
|
2013-09-27 20:10:44 +08:00
|
|
|
intel_dp_set_link_train(intel_dp, &DP,
|
2014-01-21 01:19:39 +08:00
|
|
|
training_pattern |
|
2013-09-27 20:10:44 +08:00
|
|
|
DP_LINK_SCRAMBLING_DISABLE);
|
2011-01-06 06:45:24 +08:00
|
|
|
cr_tries++;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2012-10-18 16:15:24 +08:00
|
|
|
if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
|
2010-11-29 18:09:55 +08:00
|
|
|
channel_eq = true;
|
|
|
|
break;
|
|
|
|
}
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2011-01-06 06:45:24 +08:00
|
|
|
/* Try 5 times, then try clock recovery if that fails */
|
|
|
|
if (tries > 5) {
|
|
|
|
intel_dp_link_down(intel_dp);
|
|
|
|
intel_dp_start_link_train(intel_dp);
|
2013-09-27 20:10:44 +08:00
|
|
|
intel_dp_set_link_train(intel_dp, &DP,
|
2014-01-21 01:19:39 +08:00
|
|
|
training_pattern |
|
2013-09-27 20:10:44 +08:00
|
|
|
DP_LINK_SCRAMBLING_DISABLE);
|
2011-01-06 06:45:24 +08:00
|
|
|
tries = 0;
|
|
|
|
cr_tries++;
|
|
|
|
continue;
|
|
|
|
}
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2013-09-27 20:10:44 +08:00
|
|
|
/* Update training set as requested by target */
|
|
|
|
if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
|
|
|
|
DRM_ERROR("failed to update link training\n");
|
|
|
|
break;
|
|
|
|
}
|
2010-11-29 18:09:55 +08:00
|
|
|
++tries;
|
2010-10-08 07:01:22 +08:00
|
|
|
}
|
2010-11-29 18:09:55 +08:00
|
|
|
|
2013-05-03 17:57:41 +08:00
|
|
|
intel_dp_set_idle_link_train(intel_dp);
|
|
|
|
|
|
|
|
intel_dp->DP = DP;
|
|
|
|
|
2012-10-16 02:51:34 +08:00
|
|
|
if (channel_eq)
|
2013-03-20 10:00:34 +08:00
|
|
|
DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
|
2012-10-16 02:51:34 +08:00
|
|
|
|
2013-05-03 17:57:41 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void intel_dp_stop_link_train(struct intel_dp *intel_dp)
|
|
|
|
{
|
2013-09-27 20:10:44 +08:00
|
|
|
intel_dp_set_link_train(intel_dp, &intel_dp->DP,
|
2013-05-03 17:57:41 +08:00
|
|
|
DP_TRAINING_PATTERN_DISABLE);
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2010-08-04 20:50:23 +08:00
|
|
|
intel_dp_link_down(struct intel_dp *intel_dp)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2012-10-27 05:05:46 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
2013-05-16 19:40:36 +08:00
|
|
|
enum port port = intel_dig_port->port;
|
2012-10-27 05:05:46 +08:00
|
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
2009-04-08 07:16:42 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-11-29 22:59:33 +08:00
|
|
|
struct intel_crtc *intel_crtc =
|
|
|
|
to_intel_crtc(intel_dig_port->base.base.crtc);
|
2010-08-04 20:50:23 +08:00
|
|
|
uint32_t DP = intel_dp->DP;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2014-05-21 04:46:50 +08:00
|
|
|
if (WARN_ON(HAS_DDI(dev)))
|
2012-10-16 02:51:41 +08:00
|
|
|
return;
|
|
|
|
|
2012-09-07 04:15:43 +08:00
|
|
|
if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
|
2010-12-06 19:20:45 +08:00
|
|
|
return;
|
|
|
|
|
2009-10-09 11:39:41 +08:00
|
|
|
DRM_DEBUG_KMS("\n");
|
2009-07-24 01:00:32 +08:00
|
|
|
|
2013-05-16 19:40:36 +08:00
|
|
|
if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
|
2010-04-08 09:43:27 +08:00
|
|
|
DP &= ~DP_LINK_TRAIN_MASK_CPT;
|
2010-08-04 20:50:23 +08:00
|
|
|
I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
|
2010-04-08 09:43:27 +08:00
|
|
|
} else {
|
|
|
|
DP &= ~DP_LINK_TRAIN_MASK;
|
2010-08-04 20:50:23 +08:00
|
|
|
I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
|
2010-04-08 09:43:27 +08:00
|
|
|
}
|
2010-09-12 04:37:48 +08:00
|
|
|
POSTING_READ(intel_dp->output_reg);
|
2009-07-24 01:00:31 +08:00
|
|
|
|
2012-05-30 18:31:56 +08:00
|
|
|
if (HAS_PCH_IBX(dev) &&
|
2010-12-06 19:20:45 +08:00
|
|
|
I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
|
2012-10-27 05:05:46 +08:00
|
|
|
struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
|
2011-04-17 13:38:35 +08:00
|
|
|
|
2010-11-18 09:32:59 +08:00
|
|
|
/* Hardware workaround: leaving our transcoder select
|
|
|
|
* set to transcoder B while it's off will prevent the
|
|
|
|
* corresponding HDMI output on transcoder A.
|
|
|
|
*
|
|
|
|
* Combine this with another hardware workaround:
|
|
|
|
* transcoder select bit can only be cleared while the
|
|
|
|
* port is enabled.
|
|
|
|
*/
|
|
|
|
DP &= ~DP_PIPEB_SELECT;
|
|
|
|
I915_WRITE(intel_dp->output_reg, DP);
|
|
|
|
|
|
|
|
/* Changes to enable or select take place the vblank
|
|
|
|
* after being written.
|
|
|
|
*/
|
2012-11-29 22:59:34 +08:00
|
|
|
if (WARN_ON(crtc == NULL)) {
|
|
|
|
/* We should never try to disable a port without a crtc
|
|
|
|
* attached. For paranoia keep the code around for a
|
|
|
|
* bit. */
|
2011-04-17 13:38:35 +08:00
|
|
|
POSTING_READ(intel_dp->output_reg);
|
|
|
|
msleep(50);
|
|
|
|
} else
|
2012-11-29 22:59:33 +08:00
|
|
|
intel_wait_for_vblank(dev, intel_crtc->pipe);
|
2010-11-18 09:32:59 +08:00
|
|
|
}
|
|
|
|
|
2011-12-09 20:42:21 +08:00
|
|
|
DP &= ~DP_AUDIO_OUTPUT_ENABLE;
|
2010-08-04 20:50:23 +08:00
|
|
|
I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
|
|
|
|
POSTING_READ(intel_dp->output_reg);
|
drm/i915: Correct eDP panel power sequencing delay computations
Store the panel power sequencing delays in the dp private structure,
rather than the global device structure. Who knows, maybe we'll get
more than one eDP device in the future.
From the eDP spec, we need the following numbers:
T1 + T3 Power on to Aux Channel operation (panel_power_up_delay)
This marks how long it takes the panel to boot up and
get ready to receive aux channel communications.
T8 Video signal to backlight on (backlight_on_delay)
Once a valid video signal is being sent to the device,
it can take a while before the panel is actuall
showing useful data. This delay allows the panel
to get something reasonable up before the backlight
is turned on.
T9 Backlight off to video off (backlight_off_delay)
Turning the backlight off can take a moment, so
this delay makes sure there is still valid video
data on the screen.
T10 Video off to power off (panel_power_down_delay)
Presumably this delay allows the panel to perform
an orderly shutdown of the display.
T11 + T12 Power off to power on (panel_power_cycle_delay)
So, once you turn the panel off, you have to wait a
while before you can turn it back on. This delay is
usually the longest in the entire sequence.
Neither the VBIOS source code nor the hardware documentation has a
clear mapping between the delay values they provide and those required
by the eDP spec. The VBIOS code actually uses two different labels for
the delay values in the five words of the relevant VBT table.
**** MORE LATER ***
Look at both the current hardware register settings and the VBT
specified panel power sequencing timings. Use the maximum of the two
delays, to make sure things work reliably. If there is no VBT data,
then those values will be initialized to zero, so we'll just use the
values as programmed in the hardware. Note that the BIOS just fetches
delays from the VBT table to place in the hardware registers, so we
should get the same values from both places, except for rounding.
VBT doesn't provide any values for T1 or T2, so we'll always just use
the hardware value for that.
The panel power up delay is thus T1 + T2 + T3, which should be
sufficient in all cases.
The panel power down delay is T1 + T2 + T12, using T1+T2 as a proxy
for T11, which isn't available anywhere.
For the backlight delays, the eDP spec says T6 + T8 is the delay from the
end of link training to backlight on and T9 is the delay from
backlight off until video off. The hardware provides a 'backlight on'
delay, which I'm taking to be T6 + T8 while the VBT provides something
called 'T7', which I'm assuming is s
On the macbook air I'm testing with, this yields a power-up delay of
over 200ms and a power-down delay of over 600ms. It all works now, but
we're frobbing these power controls several times during mode setting,
making the whole process take an awfully long time.
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-09-29 07:48:10 +08:00
|
|
|
msleep(intel_dp->panel_power_down_delay);
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
2011-07-26 11:01:09 +08:00
|
|
|
static bool
|
|
|
|
intel_dp_get_dpcd(struct intel_dp *intel_dp)
|
2011-07-26 10:50:10 +08:00
|
|
|
{
|
2013-10-04 03:15:06 +08:00
|
|
|
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_device *dev = dig_port->base.base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
|
2012-12-14 00:09:02 +08:00
|
|
|
char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
|
|
|
|
|
2014-03-14 22:51:15 +08:00
|
|
|
if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
|
|
|
|
sizeof(intel_dp->dpcd)) < 0)
|
2012-09-18 22:58:49 +08:00
|
|
|
return false; /* aux transfer failed */
|
2011-07-26 10:50:10 +08:00
|
|
|
|
2012-12-14 00:09:02 +08:00
|
|
|
hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
|
|
|
|
32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
|
|
|
|
DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
|
|
|
|
|
2012-09-18 22:58:49 +08:00
|
|
|
if (intel_dp->dpcd[DP_DPCD_REV] == 0)
|
|
|
|
return false; /* DPCD not present */
|
|
|
|
|
2013-07-12 05:44:56 +08:00
|
|
|
/* Check if the panel supports PSR */
|
|
|
|
memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
|
2013-09-20 21:42:17 +08:00
|
|
|
if (is_edp(intel_dp)) {
|
2014-03-14 22:51:15 +08:00
|
|
|
intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
|
|
|
|
intel_dp->psr_dpcd,
|
|
|
|
sizeof(intel_dp->psr_dpcd));
|
2013-10-04 03:15:06 +08:00
|
|
|
if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
|
|
|
|
dev_priv->psr.sink_support = true;
|
2013-09-20 21:42:17 +08:00
|
|
|
DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
|
2013-10-04 03:15:06 +08:00
|
|
|
}
|
2013-09-20 21:42:17 +08:00
|
|
|
}
|
|
|
|
|
2014-01-21 01:19:39 +08:00
|
|
|
/* Training Pattern 3 support */
|
|
|
|
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
|
|
|
|
intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
|
|
|
|
intel_dp->use_tps3 = true;
|
|
|
|
DRM_DEBUG_KMS("Displayport TPS3 supported");
|
|
|
|
} else
|
|
|
|
intel_dp->use_tps3 = false;
|
|
|
|
|
2012-09-18 22:58:49 +08:00
|
|
|
if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
|
|
|
|
DP_DWN_STRM_PORT_PRESENT))
|
|
|
|
return true; /* native DP sink */
|
|
|
|
|
|
|
|
if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
|
|
|
|
return true; /* no per-port downstream info */
|
|
|
|
|
2014-03-14 22:51:15 +08:00
|
|
|
if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
|
|
|
|
intel_dp->downstream_ports,
|
|
|
|
DP_MAX_DOWNSTREAM_PORTS) < 0)
|
2012-09-18 22:58:49 +08:00
|
|
|
return false; /* downstream port status fetch failed */
|
|
|
|
|
|
|
|
return true;
|
2011-07-26 10:50:10 +08:00
|
|
|
}
|
|
|
|
|
2012-05-15 04:05:47 +08:00
|
|
|
static void
|
|
|
|
intel_dp_probe_oui(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
u8 buf[3];
|
|
|
|
|
|
|
|
if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
|
|
|
|
return;
|
|
|
|
|
2014-03-17 22:43:36 +08:00
|
|
|
intel_edp_panel_vdd_on(intel_dp);
|
2012-06-12 19:20:47 +08:00
|
|
|
|
2014-03-14 22:51:15 +08:00
|
|
|
if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
|
2012-05-15 04:05:47 +08:00
|
|
|
DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
|
|
|
|
buf[0], buf[1], buf[2]);
|
|
|
|
|
2014-03-14 22:51:15 +08:00
|
|
|
if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
|
2012-05-15 04:05:47 +08:00
|
|
|
DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
|
|
|
|
buf[0], buf[1], buf[2]);
|
2012-06-12 19:20:47 +08:00
|
|
|
|
2014-01-17 21:39:48 +08:00
|
|
|
edp_panel_vdd_off(intel_dp, false);
|
2012-05-15 04:05:47 +08:00
|
|
|
}
|
|
|
|
|
2014-01-24 23:36:17 +08:00
|
|
|
int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
|
|
|
|
{
|
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
|
|
|
struct intel_crtc *intel_crtc =
|
|
|
|
to_intel_crtc(intel_dig_port->base.base.crtc);
|
|
|
|
u8 buf[1];
|
|
|
|
|
2014-03-14 22:51:15 +08:00
|
|
|
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
|
2014-01-24 23:36:17 +08:00
|
|
|
return -EAGAIN;
|
|
|
|
|
|
|
|
if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
|
|
|
|
return -ENOTTY;
|
|
|
|
|
2014-03-14 22:51:15 +08:00
|
|
|
if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
|
|
|
|
DP_TEST_SINK_START) < 0)
|
2014-01-24 23:36:17 +08:00
|
|
|
return -EAGAIN;
|
|
|
|
|
|
|
|
/* Wait 2 vblanks to be sure we will have the correct CRC value */
|
|
|
|
intel_wait_for_vblank(dev, intel_crtc->pipe);
|
|
|
|
intel_wait_for_vblank(dev, intel_crtc->pipe);
|
|
|
|
|
2014-03-14 22:51:15 +08:00
|
|
|
if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
|
2014-01-24 23:36:17 +08:00
|
|
|
return -EAGAIN;
|
|
|
|
|
2014-03-14 22:51:15 +08:00
|
|
|
drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
|
2014-01-24 23:36:17 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-10-21 06:09:17 +08:00
|
|
|
static bool
|
|
|
|
intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
|
|
|
|
{
|
2014-03-14 22:51:15 +08:00
|
|
|
return intel_dp_dpcd_read_wake(&intel_dp->aux,
|
|
|
|
DP_DEVICE_SERVICE_IRQ_VECTOR,
|
|
|
|
sink_irq_vector, 1) == 1;
|
2011-10-21 06:09:17 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
intel_dp_handle_test_request(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
/* NAK by default */
|
2014-03-14 22:51:15 +08:00
|
|
|
drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
|
2011-10-21 06:09:17 +08:00
|
|
|
}
|
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
/*
|
|
|
|
* According to DP spec
|
|
|
|
* 5.1.2:
|
|
|
|
* 1. Read DPCD
|
|
|
|
* 2. Configure link according to Receiver Capabilities
|
|
|
|
* 3. Use Link Training from 2.5.3.3 and 3.5.1.3
|
|
|
|
* 4. Check link status on receipt of hot-plug interrupt
|
|
|
|
*/
|
|
|
|
|
2012-10-27 05:05:52 +08:00
|
|
|
void
|
2010-08-04 20:50:23 +08:00
|
|
|
intel_dp_check_link_status(struct intel_dp *intel_dp)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2012-10-27 05:05:46 +08:00
|
|
|
struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
|
2011-10-21 06:09:17 +08:00
|
|
|
u8 sink_irq_vector;
|
2011-11-02 10:45:03 +08:00
|
|
|
u8 link_status[DP_LINK_STATUS_SIZE];
|
2011-10-21 06:09:17 +08:00
|
|
|
|
drm: Split connection_mutex out of mode_config.mutex (v3)
After the split-out of crtc locks from the big mode_config.mutex
there's still two major areas it protects:
- Various connector probe states, like connector->status, EDID
properties, probed mode lists and similar information.
- The links from connector->encoder and encoder->crtc and other
modeset-relevant connector state (e.g. properties which control the
panel fitter).
The later is used by modeset operations. But they don't really care
about the former since it's allowed to e.g. enable a disconnected VGA
output or with a mode not in the probed list.
Thus far this hasn't been a problem, but for the atomic modeset
conversion Rob Clark needs to convert all modeset relevant locks into
w/w locks. This is required because the order of acquisition is
determined by how userspace supplies the atomic modeset data. This has
run into troubles in the detect path since the i915 load detect code
needs _both_ protections offered by the mode_config.mutex: It updates
probe state and it needs to change the modeset configuration to enable
the temporary load detect pipe.
The big deal here is that for the probe/detect users of this lock a
plain mutex fits best, but for atomic modesets we really want a w/w
mutex. To fix this lets split out a new connection_mutex lock for the
modeset relevant parts.
For simplicity I've decided to only add one additional lock for all
connector/encoder links and modeset configuration states. We have
piles of different modeset objects in addition to those (like bridges
or panels), so adding per-object locks would be much more effort.
Also, we're guaranteed (at least for now) to do a full modeset if we
need to acquire this lock. Which means that fine-grained locking is
fairly irrelevant compared to the amount of time the full modeset will
take.
I've done a full audit, and there's just a few things that justify
special focus:
- Locking in drm_sysfs.c is almost completely absent. We should
sprinkle mode_config.connection_mutex over this file a bit, but
since it already lacks mode_config.mutex this patch wont make the
situation any worse. This is material for a follow-up patch.
- omap has a omap_framebuffer_flush function which walks the
connector->encoder->crtc links and is called from many contexts.
Some look like they don't acquire mode_config.mutex, so this is
already racy. Again fixing this is material for a separate patch.
- The radeon hot_plug function to retrain DP links looks at
connector->dpms. Currently this happens without any locking, so is
already racy. I think radeon_hotplug_work_func should gain
mutex_lock/unlock calls for the mode_config.connection_mutex.
- Same applies to i915's intel_dp_hot_plug. But again, this is already
racy.
- i915 load_detect code needs to acquire this lock. Which means the
w/w dance due to Rob's work will be nicely contained to _just_ this
function.
I've added fixme comments everywhere where it looks suspicious but in
the sysfs code. After a quick irc discussion with Dave Airlie it
sounds like the lack of locking in there is due to sysfs cleanup fun
at module unload.
v1: original (only compile tested)
v2: missing mutex_init(), etc (from Rob Clark)
v3: i915 needs more care in the conversion:
- Protect the edp pp logic with the connection_mutex.
- Use connection_mutex in the backlight code due to
get_pipe_from_connector.
- Use drm_modeset_lock_all in suspend/resume paths.
- Update lock checks in the overlay code.
Cc: Alex Deucher <alexdeucher@gmail.com>
Cc: Rob Clark <robdclark@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2014-05-30 05:54:47 +08:00
|
|
|
/* FIXME: This access isn't protected by any locks. */
|
2012-10-27 05:05:46 +08:00
|
|
|
if (!intel_encoder->connectors_active)
|
2011-07-26 13:37:51 +08:00
|
|
|
return;
|
2011-07-08 02:10:59 +08:00
|
|
|
|
2012-10-27 05:05:46 +08:00
|
|
|
if (WARN_ON(!intel_encoder->base.crtc))
|
2009-04-08 07:16:42 +08:00
|
|
|
return;
|
|
|
|
|
2011-07-26 10:50:10 +08:00
|
|
|
/* Try to read receiver status if the link appears to be up */
|
2011-11-02 10:45:03 +08:00
|
|
|
if (!intel_dp_get_link_status(intel_dp, link_status)) {
|
2009-04-08 07:16:42 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2011-07-26 10:50:10 +08:00
|
|
|
/* Now read the DPCD to see if it's actually running */
|
2011-07-26 11:01:09 +08:00
|
|
|
if (!intel_dp_get_dpcd(intel_dp)) {
|
2011-07-08 02:10:59 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2011-10-21 06:09:17 +08:00
|
|
|
/* Try to read the source of the interrupt */
|
|
|
|
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
|
|
|
|
intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
|
|
|
|
/* Clear interrupt source */
|
2014-03-14 22:51:15 +08:00
|
|
|
drm_dp_dpcd_writeb(&intel_dp->aux,
|
|
|
|
DP_DEVICE_SERVICE_IRQ_VECTOR,
|
|
|
|
sink_irq_vector);
|
2011-10-21 06:09:17 +08:00
|
|
|
|
|
|
|
if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
|
|
|
|
intel_dp_handle_test_request(intel_dp);
|
|
|
|
if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
|
|
|
|
DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
|
|
|
|
}
|
|
|
|
|
2012-10-18 16:15:24 +08:00
|
|
|
if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
|
2011-07-26 10:50:10 +08:00
|
|
|
DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
|
2014-06-03 19:56:21 +08:00
|
|
|
intel_encoder->base.name);
|
2010-09-09 03:42:02 +08:00
|
|
|
intel_dp_start_link_train(intel_dp);
|
|
|
|
intel_dp_complete_link_train(intel_dp);
|
2013-05-03 17:57:41 +08:00
|
|
|
intel_dp_stop_link_train(intel_dp);
|
2010-09-09 03:42:02 +08:00
|
|
|
}
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
2012-09-18 22:58:50 +08:00
|
|
|
/* XXX this is probably wrong for multiple downstream ports */
|
2011-07-13 05:38:04 +08:00
|
|
|
static enum drm_connector_status
|
2011-07-26 11:01:09 +08:00
|
|
|
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
|
2011-07-13 05:38:04 +08:00
|
|
|
{
|
2012-09-18 22:58:50 +08:00
|
|
|
uint8_t *dpcd = intel_dp->dpcd;
|
|
|
|
uint8_t type;
|
|
|
|
|
|
|
|
if (!intel_dp_get_dpcd(intel_dp))
|
|
|
|
return connector_status_disconnected;
|
|
|
|
|
|
|
|
/* if there's no downstream port, we're done */
|
|
|
|
if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
|
2011-07-26 11:01:09 +08:00
|
|
|
return connector_status_connected;
|
2012-09-18 22:58:50 +08:00
|
|
|
|
|
|
|
/* If we're HPD-aware, SINK_COUNT changes dynamically */
|
2013-09-27 19:48:42 +08:00
|
|
|
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
|
|
|
|
intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
|
2012-09-21 04:42:45 +08:00
|
|
|
uint8_t reg;
|
2014-03-14 22:51:15 +08:00
|
|
|
|
|
|
|
if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
|
|
|
|
®, 1) < 0)
|
2012-09-18 22:58:50 +08:00
|
|
|
return connector_status_unknown;
|
2014-03-14 22:51:15 +08:00
|
|
|
|
2012-09-21 04:42:45 +08:00
|
|
|
return DP_GET_SINK_COUNT(reg) ? connector_status_connected
|
|
|
|
: connector_status_disconnected;
|
2012-09-18 22:58:50 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
/* If no HPD, poke DDC gently */
|
2014-03-14 22:51:17 +08:00
|
|
|
if (drm_probe_ddc(&intel_dp->aux.ddc))
|
2011-07-26 11:01:09 +08:00
|
|
|
return connector_status_connected;
|
2012-09-18 22:58:50 +08:00
|
|
|
|
|
|
|
/* Well we tried, say unknown for unreliable port types */
|
2013-09-27 19:48:42 +08:00
|
|
|
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
|
|
|
|
type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
|
|
|
|
if (type == DP_DS_PORT_TYPE_VGA ||
|
|
|
|
type == DP_DS_PORT_TYPE_NON_EDID)
|
|
|
|
return connector_status_unknown;
|
|
|
|
} else {
|
|
|
|
type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
|
|
|
|
DP_DWN_STRM_PORT_TYPE_MASK;
|
|
|
|
if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
|
|
|
|
type == DP_DWN_STRM_PORT_TYPE_OTHER)
|
|
|
|
return connector_status_unknown;
|
|
|
|
}
|
2012-09-18 22:58:50 +08:00
|
|
|
|
|
|
|
/* Anything else is out of spec, warn and ignore */
|
|
|
|
DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
|
2011-07-26 11:01:09 +08:00
|
|
|
return connector_status_disconnected;
|
2011-07-13 05:38:04 +08:00
|
|
|
}
|
|
|
|
|
2009-07-24 01:00:31 +08:00
|
|
|
static enum drm_connector_status
|
2010-09-19 13:09:06 +08:00
|
|
|
ironlake_dp_detect(struct intel_dp *intel_dp)
|
2009-07-24 01:00:31 +08:00
|
|
|
{
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2012-12-14 00:09:01 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
2009-07-24 01:00:31 +08:00
|
|
|
enum drm_connector_status status;
|
|
|
|
|
2011-02-12 18:29:38 +08:00
|
|
|
/* Can't disconnect eDP, but you can close the lid... */
|
|
|
|
if (is_edp(intel_dp)) {
|
2012-10-27 05:05:45 +08:00
|
|
|
status = intel_panel_detect(dev);
|
2011-02-12 18:29:38 +08:00
|
|
|
if (status == connector_status_unknown)
|
|
|
|
status = connector_status_connected;
|
|
|
|
return status;
|
|
|
|
}
|
2010-10-08 07:01:12 +08:00
|
|
|
|
2012-12-14 00:09:01 +08:00
|
|
|
if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
|
|
|
|
return connector_status_disconnected;
|
|
|
|
|
2011-07-26 11:01:09 +08:00
|
|
|
return intel_dp_detect_dpcd(intel_dp);
|
2009-07-24 01:00:31 +08:00
|
|
|
}
|
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
static enum drm_connector_status
|
2010-09-19 13:09:06 +08:00
|
|
|
g4x_dp_detect(struct intel_dp *intel_dp)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2012-10-27 05:05:45 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2009-04-08 07:16:42 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-01-24 21:29:27 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
2012-05-12 01:01:32 +08:00
|
|
|
uint32_t bit;
|
2009-07-24 01:00:31 +08:00
|
|
|
|
2013-03-02 05:14:31 +08:00
|
|
|
/* Can't disconnect eDP, but you can close the lid... */
|
|
|
|
if (is_edp(intel_dp)) {
|
|
|
|
enum drm_connector_status status;
|
|
|
|
|
|
|
|
status = intel_panel_detect(dev);
|
|
|
|
if (status == connector_status_unknown)
|
|
|
|
status = connector_status_connected;
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
2014-01-23 15:13:41 +08:00
|
|
|
if (IS_VALLEYVIEW(dev)) {
|
|
|
|
switch (intel_dig_port->port) {
|
|
|
|
case PORT_B:
|
|
|
|
bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
|
|
|
|
break;
|
|
|
|
case PORT_C:
|
|
|
|
bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
|
|
|
|
break;
|
|
|
|
case PORT_D:
|
|
|
|
bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return connector_status_unknown;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
switch (intel_dig_port->port) {
|
|
|
|
case PORT_B:
|
|
|
|
bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
|
|
|
|
break;
|
|
|
|
case PORT_C:
|
|
|
|
bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
|
|
|
|
break;
|
|
|
|
case PORT_D:
|
|
|
|
bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return connector_status_unknown;
|
|
|
|
}
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
2012-05-12 01:01:32 +08:00
|
|
|
if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
|
2009-04-08 07:16:42 +08:00
|
|
|
return connector_status_disconnected;
|
|
|
|
|
2011-07-26 11:01:09 +08:00
|
|
|
return intel_dp_detect_dpcd(intel_dp);
|
2010-09-19 13:09:06 +08:00
|
|
|
}
|
|
|
|
|
2011-09-29 07:38:44 +08:00
|
|
|
static struct edid *
|
|
|
|
intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
|
|
|
|
{
|
2012-10-19 19:51:52 +08:00
|
|
|
struct intel_connector *intel_connector = to_intel_connector(connector);
|
2012-06-15 03:28:33 +08:00
|
|
|
|
2012-10-19 19:51:52 +08:00
|
|
|
/* use cached edid if we have one */
|
|
|
|
if (intel_connector->edid) {
|
|
|
|
/* invalid edid */
|
|
|
|
if (IS_ERR(intel_connector->edid))
|
2012-06-15 03:28:33 +08:00
|
|
|
return NULL;
|
|
|
|
|
2013-10-01 15:38:54 +08:00
|
|
|
return drm_edid_duplicate(intel_connector->edid);
|
2012-06-15 03:28:33 +08:00
|
|
|
}
|
2011-09-29 07:38:44 +08:00
|
|
|
|
2012-10-19 19:51:52 +08:00
|
|
|
return drm_get_edid(connector, adapter);
|
2011-09-29 07:38:44 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
|
|
|
|
{
|
2012-10-19 19:51:52 +08:00
|
|
|
struct intel_connector *intel_connector = to_intel_connector(connector);
|
2011-09-29 07:38:44 +08:00
|
|
|
|
2012-10-19 19:51:52 +08:00
|
|
|
/* use cached edid if we have one */
|
|
|
|
if (intel_connector->edid) {
|
|
|
|
/* invalid edid */
|
|
|
|
if (IS_ERR(intel_connector->edid))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
return intel_connector_update_modes(connector,
|
|
|
|
intel_connector->edid);
|
2012-06-15 03:28:33 +08:00
|
|
|
}
|
|
|
|
|
2012-10-19 19:51:52 +08:00
|
|
|
return intel_ddc_get_modes(connector, adapter);
|
2011-09-29 07:38:44 +08:00
|
|
|
}
|
|
|
|
|
2010-09-19 13:09:06 +08:00
|
|
|
static enum drm_connector_status
|
|
|
|
intel_dp_detect(struct drm_connector *connector, bool force)
|
|
|
|
{
|
|
|
|
struct intel_dp *intel_dp = intel_attached_dp(connector);
|
2012-10-27 05:05:49 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct intel_encoder *intel_encoder = &intel_dig_port->base;
|
2012-10-27 05:05:44 +08:00
|
|
|
struct drm_device *dev = connector->dev;
|
2013-11-28 04:21:54 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2010-09-19 13:09:06 +08:00
|
|
|
enum drm_connector_status status;
|
2014-03-05 22:20:53 +08:00
|
|
|
enum intel_display_power_domain power_domain;
|
2010-09-19 13:09:06 +08:00
|
|
|
struct edid *edid = NULL;
|
|
|
|
|
2013-11-28 04:21:54 +08:00
|
|
|
intel_runtime_pm_get(dev_priv);
|
|
|
|
|
2014-03-05 22:20:53 +08:00
|
|
|
power_domain = intel_display_port_power_domain(intel_encoder);
|
|
|
|
intel_display_power_get(dev_priv, power_domain);
|
|
|
|
|
2013-07-21 03:27:08 +08:00
|
|
|
DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
|
2014-06-03 19:56:17 +08:00
|
|
|
connector->base.id, connector->name);
|
2013-07-21 03:27:08 +08:00
|
|
|
|
2010-09-19 13:09:06 +08:00
|
|
|
intel_dp->has_audio = false;
|
|
|
|
|
|
|
|
if (HAS_PCH_SPLIT(dev))
|
|
|
|
status = ironlake_dp_detect(intel_dp);
|
|
|
|
else
|
|
|
|
status = g4x_dp_detect(intel_dp);
|
2011-07-13 05:38:01 +08:00
|
|
|
|
2010-09-19 13:09:06 +08:00
|
|
|
if (status != connector_status_connected)
|
2013-11-28 04:21:54 +08:00
|
|
|
goto out;
|
2010-09-19 13:09:06 +08:00
|
|
|
|
2012-05-15 04:05:47 +08:00
|
|
|
intel_dp_probe_oui(intel_dp);
|
|
|
|
|
2012-02-24 00:14:47 +08:00
|
|
|
if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
|
|
|
|
intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
|
2010-09-19 16:29:33 +08:00
|
|
|
} else {
|
2014-03-14 22:51:17 +08:00
|
|
|
edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
|
2010-09-19 16:29:33 +08:00
|
|
|
if (edid) {
|
|
|
|
intel_dp->has_audio = drm_detect_monitor_audio(edid);
|
|
|
|
kfree(edid);
|
|
|
|
}
|
2010-09-19 13:09:06 +08:00
|
|
|
}
|
|
|
|
|
2012-10-27 05:05:49 +08:00
|
|
|
if (intel_encoder->type != INTEL_OUTPUT_EDP)
|
|
|
|
intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
|
2013-11-28 04:21:54 +08:00
|
|
|
status = connector_status_connected;
|
|
|
|
|
|
|
|
out:
|
2014-03-05 22:20:53 +08:00
|
|
|
intel_display_power_put(dev_priv, power_domain);
|
|
|
|
|
2013-11-28 04:21:54 +08:00
|
|
|
intel_runtime_pm_put(dev_priv);
|
2014-03-05 22:20:53 +08:00
|
|
|
|
2013-11-28 04:21:54 +08:00
|
|
|
return status;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int intel_dp_get_modes(struct drm_connector *connector)
|
|
|
|
{
|
2010-09-09 23:20:55 +08:00
|
|
|
struct intel_dp *intel_dp = intel_attached_dp(connector);
|
2014-03-05 22:20:53 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct intel_encoder *intel_encoder = &intel_dig_port->base;
|
2012-10-19 19:51:50 +08:00
|
|
|
struct intel_connector *intel_connector = to_intel_connector(connector);
|
2012-10-27 05:05:44 +08:00
|
|
|
struct drm_device *dev = connector->dev;
|
2014-03-05 22:20:53 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
enum intel_display_power_domain power_domain;
|
2009-07-24 01:00:32 +08:00
|
|
|
int ret;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
|
|
|
/* We should parse the EDID data and find out if it has an audio sink
|
|
|
|
*/
|
|
|
|
|
2014-03-05 22:20:53 +08:00
|
|
|
power_domain = intel_display_port_power_domain(intel_encoder);
|
|
|
|
intel_display_power_get(dev_priv, power_domain);
|
|
|
|
|
2014-03-14 22:51:17 +08:00
|
|
|
ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
|
2014-03-05 22:20:53 +08:00
|
|
|
intel_display_power_put(dev_priv, power_domain);
|
2012-10-19 19:51:48 +08:00
|
|
|
if (ret)
|
2009-07-24 01:00:32 +08:00
|
|
|
return ret;
|
|
|
|
|
2012-10-19 19:51:48 +08:00
|
|
|
/* if eDP has no EDID, fall back to fixed mode */
|
2012-10-19 19:51:50 +08:00
|
|
|
if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
|
2012-10-19 19:51:48 +08:00
|
|
|
struct drm_display_mode *mode;
|
2012-10-19 19:51:50 +08:00
|
|
|
mode = drm_mode_duplicate(dev,
|
|
|
|
intel_connector->panel.fixed_mode);
|
2012-10-19 19:51:48 +08:00
|
|
|
if (mode) {
|
2009-07-24 01:00:32 +08:00
|
|
|
drm_mode_probed_add(connector, mode);
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return 0;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
2011-02-10 02:46:58 +08:00
|
|
|
static bool
|
|
|
|
intel_dp_detect_audio(struct drm_connector *connector)
|
|
|
|
{
|
|
|
|
struct intel_dp *intel_dp = intel_attached_dp(connector);
|
2014-03-05 22:20:53 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
|
|
struct intel_encoder *intel_encoder = &intel_dig_port->base;
|
|
|
|
struct drm_device *dev = connector->dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
enum intel_display_power_domain power_domain;
|
2011-02-10 02:46:58 +08:00
|
|
|
struct edid *edid;
|
|
|
|
bool has_audio = false;
|
|
|
|
|
2014-03-05 22:20:53 +08:00
|
|
|
power_domain = intel_display_port_power_domain(intel_encoder);
|
|
|
|
intel_display_power_get(dev_priv, power_domain);
|
|
|
|
|
2014-03-14 22:51:17 +08:00
|
|
|
edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
|
2011-02-10 02:46:58 +08:00
|
|
|
if (edid) {
|
|
|
|
has_audio = drm_detect_monitor_audio(edid);
|
|
|
|
kfree(edid);
|
|
|
|
}
|
|
|
|
|
2014-03-05 22:20:53 +08:00
|
|
|
intel_display_power_put(dev_priv, power_domain);
|
|
|
|
|
2011-02-10 02:46:58 +08:00
|
|
|
return has_audio;
|
|
|
|
}
|
|
|
|
|
2010-09-19 16:29:33 +08:00
|
|
|
static int
|
|
|
|
intel_dp_set_property(struct drm_connector *connector,
|
|
|
|
struct drm_property *property,
|
|
|
|
uint64_t val)
|
|
|
|
{
|
2011-02-22 06:23:52 +08:00
|
|
|
struct drm_i915_private *dev_priv = connector->dev->dev_private;
|
2012-10-26 17:04:00 +08:00
|
|
|
struct intel_connector *intel_connector = to_intel_connector(connector);
|
2012-10-27 05:05:46 +08:00
|
|
|
struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
|
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
|
2010-09-19 16:29:33 +08:00
|
|
|
int ret;
|
|
|
|
|
2012-10-12 09:36:04 +08:00
|
|
|
ret = drm_object_property_set_value(&connector->base, property, val);
|
2010-09-19 16:29:33 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2011-05-13 05:17:24 +08:00
|
|
|
if (property == dev_priv->force_audio_property) {
|
2011-02-10 02:46:58 +08:00
|
|
|
int i = val;
|
|
|
|
bool has_audio;
|
|
|
|
|
|
|
|
if (i == intel_dp->force_audio)
|
2010-09-19 16:29:33 +08:00
|
|
|
return 0;
|
|
|
|
|
2011-02-10 02:46:58 +08:00
|
|
|
intel_dp->force_audio = i;
|
2010-09-19 16:29:33 +08:00
|
|
|
|
2012-02-24 00:14:47 +08:00
|
|
|
if (i == HDMI_AUDIO_AUTO)
|
2011-02-10 02:46:58 +08:00
|
|
|
has_audio = intel_dp_detect_audio(connector);
|
|
|
|
else
|
2012-02-24 00:14:47 +08:00
|
|
|
has_audio = (i == HDMI_AUDIO_ON);
|
2011-02-10 02:46:58 +08:00
|
|
|
|
|
|
|
if (has_audio == intel_dp->has_audio)
|
2010-09-19 16:29:33 +08:00
|
|
|
return 0;
|
|
|
|
|
2011-02-10 02:46:58 +08:00
|
|
|
intel_dp->has_audio = has_audio;
|
2010-09-19 16:29:33 +08:00
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
2011-02-22 06:23:52 +08:00
|
|
|
if (property == dev_priv->broadcast_rgb_property) {
|
2013-04-22 23:07:23 +08:00
|
|
|
bool old_auto = intel_dp->color_range_auto;
|
|
|
|
uint32_t old_range = intel_dp->color_range;
|
|
|
|
|
2013-01-17 22:31:29 +08:00
|
|
|
switch (val) {
|
|
|
|
case INTEL_BROADCAST_RGB_AUTO:
|
|
|
|
intel_dp->color_range_auto = true;
|
|
|
|
break;
|
|
|
|
case INTEL_BROADCAST_RGB_FULL:
|
|
|
|
intel_dp->color_range_auto = false;
|
|
|
|
intel_dp->color_range = 0;
|
|
|
|
break;
|
|
|
|
case INTEL_BROADCAST_RGB_LIMITED:
|
|
|
|
intel_dp->color_range_auto = false;
|
|
|
|
intel_dp->color_range = DP_COLOR_RANGE_16_235;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2013-04-22 23:07:23 +08:00
|
|
|
|
|
|
|
if (old_auto == intel_dp->color_range_auto &&
|
|
|
|
old_range == intel_dp->color_range)
|
|
|
|
return 0;
|
|
|
|
|
2011-02-22 06:23:52 +08:00
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
2012-10-26 17:04:00 +08:00
|
|
|
if (is_edp(intel_dp) &&
|
|
|
|
property == connector->dev->mode_config.scaling_mode_property) {
|
|
|
|
if (val == DRM_MODE_SCALE_NONE) {
|
|
|
|
DRM_DEBUG_KMS("no scaling not supported\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (intel_connector->panel.fitting_mode == val) {
|
|
|
|
/* the eDP scaling property is not changed */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
intel_connector->panel.fitting_mode = val;
|
|
|
|
|
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
2010-09-19 16:29:33 +08:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
done:
|
2012-12-20 00:08:43 +08:00
|
|
|
if (intel_encoder->base.crtc)
|
|
|
|
intel_crtc_restore_mode(intel_encoder->base.crtc);
|
2010-09-19 16:29:33 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
static void
|
2013-06-13 04:27:30 +08:00
|
|
|
intel_dp_connector_destroy(struct drm_connector *connector)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2012-10-19 19:51:49 +08:00
|
|
|
struct intel_connector *intel_connector = to_intel_connector(connector);
|
2011-08-12 18:11:33 +08:00
|
|
|
|
2012-10-19 19:51:52 +08:00
|
|
|
if (!IS_ERR_OR_NULL(intel_connector->edid))
|
|
|
|
kfree(intel_connector->edid);
|
|
|
|
|
2013-06-13 04:27:23 +08:00
|
|
|
/* Can't call is_edp() since the encoder may have been destroyed
|
|
|
|
* already. */
|
|
|
|
if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
|
2012-10-19 19:51:49 +08:00
|
|
|
intel_panel_fini(&intel_connector->panel);
|
2011-08-12 18:11:33 +08:00
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
drm_connector_cleanup(connector);
|
2010-03-29 16:13:57 +08:00
|
|
|
kfree(connector);
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
|
|
|
|
2012-10-27 05:05:52 +08:00
|
|
|
void intel_dp_encoder_destroy(struct drm_encoder *encoder)
|
2010-08-21 00:08:28 +08:00
|
|
|
{
|
2012-10-27 05:05:46 +08:00
|
|
|
struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
|
|
|
|
struct intel_dp *intel_dp = &intel_dig_port->dp;
|
2013-03-25 18:24:10 +08:00
|
|
|
struct drm_device *dev = intel_dp_to_dev(intel_dp);
|
2010-08-21 00:08:28 +08:00
|
|
|
|
2014-06-04 14:02:28 +08:00
|
|
|
drm_dp_aux_unregister(&intel_dp->aux);
|
2010-08-21 00:08:28 +08:00
|
|
|
drm_encoder_cleanup(encoder);
|
2011-09-19 14:09:52 +08:00
|
|
|
if (is_edp(intel_dp)) {
|
|
|
|
cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
|
2013-11-20 01:10:12 +08:00
|
|
|
drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
|
2014-01-17 21:39:48 +08:00
|
|
|
edp_panel_vdd_off_sync(intel_dp);
|
2013-11-20 01:10:12 +08:00
|
|
|
drm_modeset_unlock(&dev->mode_config.connection_mutex);
|
2011-09-19 14:09:52 +08:00
|
|
|
}
|
2012-10-27 05:05:46 +08:00
|
|
|
kfree(intel_dig_port);
|
2010-08-21 00:08:28 +08:00
|
|
|
}
|
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
static const struct drm_connector_funcs intel_dp_connector_funcs = {
|
2012-09-07 04:15:41 +08:00
|
|
|
.dpms = intel_connector_dpms,
|
2009-04-08 07:16:42 +08:00
|
|
|
.detect = intel_dp_detect,
|
|
|
|
.fill_modes = drm_helper_probe_single_connector_modes,
|
2010-09-19 16:29:33 +08:00
|
|
|
.set_property = intel_dp_set_property,
|
2013-06-13 04:27:30 +08:00
|
|
|
.destroy = intel_dp_connector_destroy,
|
2009-04-08 07:16:42 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
|
|
|
|
.get_modes = intel_dp_get_modes,
|
|
|
|
.mode_valid = intel_dp_mode_valid,
|
2010-09-09 23:20:55 +08:00
|
|
|
.best_encoder = intel_best_encoder,
|
2009-04-08 07:16:42 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct drm_encoder_funcs intel_dp_enc_funcs = {
|
2010-08-21 00:08:28 +08:00
|
|
|
.destroy = intel_dp_encoder_destroy,
|
2009-04-08 07:16:42 +08:00
|
|
|
};
|
|
|
|
|
2010-08-20 20:23:26 +08:00
|
|
|
static void
|
2010-03-26 02:11:14 +08:00
|
|
|
intel_dp_hot_plug(struct intel_encoder *intel_encoder)
|
2009-05-07 02:51:10 +08:00
|
|
|
{
|
2012-10-27 05:05:44 +08:00
|
|
|
struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
|
2009-05-07 02:51:10 +08:00
|
|
|
|
2011-07-08 02:11:01 +08:00
|
|
|
intel_dp_check_link_status(intel_dp);
|
2009-05-07 02:51:10 +08:00
|
|
|
}
|
2010-01-06 09:49:31 +08:00
|
|
|
|
2010-04-08 09:43:27 +08:00
|
|
|
/* Return which DP Port should be selected for Transcoder DP control */
|
|
|
|
int
|
2011-08-17 03:34:10 +08:00
|
|
|
intel_trans_dp_port_sel(struct drm_crtc *crtc)
|
2010-04-08 09:43:27 +08:00
|
|
|
{
|
|
|
|
struct drm_device *dev = crtc->dev;
|
2012-10-27 05:05:44 +08:00
|
|
|
struct intel_encoder *intel_encoder;
|
|
|
|
struct intel_dp *intel_dp;
|
2010-04-08 09:43:27 +08:00
|
|
|
|
2012-10-27 05:05:44 +08:00
|
|
|
for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
|
|
|
|
intel_dp = enc_to_intel_dp(&intel_encoder->base);
|
2010-04-08 09:43:27 +08:00
|
|
|
|
2012-10-27 05:05:44 +08:00
|
|
|
if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
|
|
|
|
intel_encoder->type == INTEL_OUTPUT_EDP)
|
2010-08-04 20:50:23 +08:00
|
|
|
return intel_dp->output_reg;
|
2010-04-08 09:43:27 +08:00
|
|
|
}
|
2010-08-04 20:50:23 +08:00
|
|
|
|
2010-04-08 09:43:27 +08:00
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2010-06-12 14:32:21 +08:00
|
|
|
/* check the VBT to see whether the eDP is on DP-D port */
|
2013-11-02 00:22:39 +08:00
|
|
|
bool intel_dp_is_edp(struct drm_device *dev, enum port port)
|
2010-06-12 14:32:21 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-09-12 05:02:47 +08:00
|
|
|
union child_device_config *p_child;
|
2010-06-12 14:32:21 +08:00
|
|
|
int i;
|
2013-11-02 00:22:39 +08:00
|
|
|
static const short port_mapping[] = {
|
|
|
|
[PORT_B] = PORT_IDPB,
|
|
|
|
[PORT_C] = PORT_IDPC,
|
|
|
|
[PORT_D] = PORT_IDPD,
|
|
|
|
};
|
2010-06-12 14:32:21 +08:00
|
|
|
|
2013-11-02 00:22:41 +08:00
|
|
|
if (port == PORT_A)
|
|
|
|
return true;
|
|
|
|
|
2013-05-10 07:03:18 +08:00
|
|
|
if (!dev_priv->vbt.child_dev_num)
|
2010-06-12 14:32:21 +08:00
|
|
|
return false;
|
|
|
|
|
2013-05-10 07:03:18 +08:00
|
|
|
for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
|
|
|
|
p_child = dev_priv->vbt.child_dev + i;
|
2010-06-12 14:32:21 +08:00
|
|
|
|
2013-11-02 00:22:39 +08:00
|
|
|
if (p_child->common.dvo_port == port_mapping[port] &&
|
2013-11-02 02:32:08 +08:00
|
|
|
(p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
|
|
|
|
(DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
|
2010-06-12 14:32:21 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2010-09-19 16:29:33 +08:00
|
|
|
static void
|
|
|
|
intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
|
|
|
|
{
|
2012-10-26 17:04:00 +08:00
|
|
|
struct intel_connector *intel_connector = to_intel_connector(connector);
|
|
|
|
|
2011-05-13 05:17:24 +08:00
|
|
|
intel_attach_force_audio_property(connector);
|
2011-02-22 06:23:52 +08:00
|
|
|
intel_attach_broadcast_rgb_property(connector);
|
2013-01-17 22:31:29 +08:00
|
|
|
intel_dp->color_range_auto = true;
|
2012-10-26 17:04:00 +08:00
|
|
|
|
|
|
|
if (is_edp(intel_dp)) {
|
|
|
|
drm_mode_create_scaling_mode_property(connector->dev);
|
2012-10-12 09:36:04 +08:00
|
|
|
drm_object_attach_property(
|
|
|
|
&connector->base,
|
2012-10-26 17:04:00 +08:00
|
|
|
connector->dev->mode_config.scaling_mode_property,
|
2012-10-26 17:04:01 +08:00
|
|
|
DRM_MODE_SCALE_ASPECT);
|
|
|
|
intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
|
2012-10-26 17:04:00 +08:00
|
|
|
}
|
2010-09-19 16:29:33 +08:00
|
|
|
}
|
|
|
|
|
2014-01-29 19:25:41 +08:00
|
|
|
static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
|
|
|
|
{
|
|
|
|
intel_dp->last_power_cycle = jiffies;
|
|
|
|
intel_dp->last_power_on = jiffies;
|
|
|
|
intel_dp->last_backlight_off = jiffies;
|
|
|
|
}
|
|
|
|
|
2012-10-21 02:57:45 +08:00
|
|
|
static void
|
|
|
|
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
|
2013-01-16 16:53:40 +08:00
|
|
|
struct intel_dp *intel_dp,
|
|
|
|
struct edp_power_seq *out)
|
2012-10-21 02:57:45 +08:00
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct edp_power_seq cur, vbt, spec, final;
|
|
|
|
u32 pp_on, pp_off, pp_div, pp;
|
2013-09-06 12:40:05 +08:00
|
|
|
int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
|
2013-03-29 00:55:41 +08:00
|
|
|
|
|
|
|
if (HAS_PCH_SPLIT(dev)) {
|
2013-09-06 12:40:05 +08:00
|
|
|
pp_ctrl_reg = PCH_PP_CONTROL;
|
2013-03-29 00:55:41 +08:00
|
|
|
pp_on_reg = PCH_PP_ON_DELAYS;
|
|
|
|
pp_off_reg = PCH_PP_OFF_DELAYS;
|
|
|
|
pp_div_reg = PCH_PP_DIVISOR;
|
|
|
|
} else {
|
2013-09-06 12:40:05 +08:00
|
|
|
enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
|
|
|
|
|
|
|
|
pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
|
|
|
|
pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
|
|
|
|
pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
|
|
|
|
pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
|
2013-03-29 00:55:41 +08:00
|
|
|
}
|
2012-10-21 02:57:45 +08:00
|
|
|
|
|
|
|
/* Workaround: Need to write PP_CONTROL with the unlock key as
|
|
|
|
* the very first thing. */
|
2013-03-29 00:55:41 +08:00
|
|
|
pp = ironlake_get_pp_control(intel_dp);
|
2013-09-06 12:40:05 +08:00
|
|
|
I915_WRITE(pp_ctrl_reg, pp);
|
2012-10-21 02:57:45 +08:00
|
|
|
|
2013-03-29 00:55:41 +08:00
|
|
|
pp_on = I915_READ(pp_on_reg);
|
|
|
|
pp_off = I915_READ(pp_off_reg);
|
|
|
|
pp_div = I915_READ(pp_div_reg);
|
2012-10-21 02:57:45 +08:00
|
|
|
|
|
|
|
/* Pull timing values out of registers */
|
|
|
|
cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
|
|
|
|
PANEL_POWER_UP_DELAY_SHIFT;
|
|
|
|
|
|
|
|
cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
|
|
|
|
PANEL_LIGHT_ON_DELAY_SHIFT;
|
|
|
|
|
|
|
|
cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
|
|
|
|
PANEL_LIGHT_OFF_DELAY_SHIFT;
|
|
|
|
|
|
|
|
cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
|
|
|
|
PANEL_POWER_DOWN_DELAY_SHIFT;
|
|
|
|
|
|
|
|
cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
|
|
|
|
PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
|
|
|
|
cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
|
|
|
|
|
2013-05-10 07:03:18 +08:00
|
|
|
vbt = dev_priv->vbt.edp_pps;
|
2012-10-21 02:57:45 +08:00
|
|
|
|
|
|
|
/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
|
|
|
|
* our hw here, which are all in 100usec. */
|
|
|
|
spec.t1_t3 = 210 * 10;
|
|
|
|
spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
|
|
|
|
spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
|
|
|
|
spec.t10 = 500 * 10;
|
|
|
|
/* This one is special and actually in units of 100ms, but zero
|
|
|
|
* based in the hw (so we need to add 100 ms). But the sw vbt
|
|
|
|
* table multiplies it with 1000 to make it in units of 100usec,
|
|
|
|
* too. */
|
|
|
|
spec.t11_t12 = (510 + 100) * 10;
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
|
|
|
|
vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
|
|
|
|
|
|
|
|
/* Use the max of the register settings and vbt. If both are
|
|
|
|
* unset, fall back to the spec limits. */
|
|
|
|
#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
|
|
|
|
spec.field : \
|
|
|
|
max(cur.field, vbt.field))
|
|
|
|
assign_final(t1_t3);
|
|
|
|
assign_final(t8);
|
|
|
|
assign_final(t9);
|
|
|
|
assign_final(t10);
|
|
|
|
assign_final(t11_t12);
|
|
|
|
#undef assign_final
|
|
|
|
|
|
|
|
#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
|
|
|
|
intel_dp->panel_power_up_delay = get_delay(t1_t3);
|
|
|
|
intel_dp->backlight_on_delay = get_delay(t8);
|
|
|
|
intel_dp->backlight_off_delay = get_delay(t9);
|
|
|
|
intel_dp->panel_power_down_delay = get_delay(t10);
|
|
|
|
intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
|
|
|
|
#undef get_delay
|
|
|
|
|
2013-01-16 16:53:40 +08:00
|
|
|
DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
|
|
|
|
intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
|
|
|
|
intel_dp->panel_power_cycle_delay);
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
|
|
|
|
intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
|
|
|
|
|
|
|
|
if (out)
|
|
|
|
*out = final;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
|
|
|
|
struct intel_dp *intel_dp,
|
|
|
|
struct edp_power_seq *seq)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2013-03-29 00:55:41 +08:00
|
|
|
u32 pp_on, pp_off, pp_div, port_sel = 0;
|
|
|
|
int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
|
|
|
|
int pp_on_reg, pp_off_reg, pp_div_reg;
|
|
|
|
|
|
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
|
|
pp_on_reg = PCH_PP_ON_DELAYS;
|
|
|
|
pp_off_reg = PCH_PP_OFF_DELAYS;
|
|
|
|
pp_div_reg = PCH_PP_DIVISOR;
|
|
|
|
} else {
|
2013-09-06 12:40:05 +08:00
|
|
|
enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
|
|
|
|
|
|
|
|
pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
|
|
|
|
pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
|
|
|
|
pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
|
2013-03-29 00:55:41 +08:00
|
|
|
}
|
|
|
|
|
2013-12-20 00:29:44 +08:00
|
|
|
/*
|
|
|
|
* And finally store the new values in the power sequencer. The
|
|
|
|
* backlight delays are set to 1 because we do manual waits on them. For
|
|
|
|
* T8, even BSpec recommends doing it. For T9, if we don't do this,
|
|
|
|
* we'll end up waiting for the backlight off delay twice: once when we
|
|
|
|
* do the manual sleep, and once when we disable the panel and wait for
|
|
|
|
* the PP_STATUS bit to become zero.
|
|
|
|
*/
|
2013-01-16 16:53:40 +08:00
|
|
|
pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
|
2013-12-20 00:29:44 +08:00
|
|
|
(1 << PANEL_LIGHT_ON_DELAY_SHIFT);
|
|
|
|
pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
|
2013-01-16 16:53:40 +08:00
|
|
|
(seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
|
2012-10-21 02:57:45 +08:00
|
|
|
/* Compute the divisor for the pp clock, simply match the Bspec
|
|
|
|
* formula. */
|
2013-03-29 00:55:41 +08:00
|
|
|
pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
|
2013-01-16 16:53:40 +08:00
|
|
|
pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
|
2012-10-21 02:57:45 +08:00
|
|
|
<< PANEL_POWER_CYCLE_DELAY_SHIFT);
|
|
|
|
|
|
|
|
/* Haswell doesn't have any port selection bits for the panel
|
|
|
|
* power sequencer any more. */
|
2013-05-16 19:40:36 +08:00
|
|
|
if (IS_VALLEYVIEW(dev)) {
|
2013-09-06 12:40:05 +08:00
|
|
|
if (dp_to_dig_port(intel_dp)->port == PORT_B)
|
|
|
|
port_sel = PANEL_PORT_SELECT_DPB_VLV;
|
|
|
|
else
|
|
|
|
port_sel = PANEL_PORT_SELECT_DPC_VLV;
|
2013-05-16 19:40:36 +08:00
|
|
|
} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
|
|
|
|
if (dp_to_dig_port(intel_dp)->port == PORT_A)
|
2013-09-05 21:44:46 +08:00
|
|
|
port_sel = PANEL_PORT_SELECT_DPA;
|
2012-10-21 02:57:45 +08:00
|
|
|
else
|
2013-09-05 21:44:46 +08:00
|
|
|
port_sel = PANEL_PORT_SELECT_DPD;
|
2012-10-21 02:57:45 +08:00
|
|
|
}
|
|
|
|
|
2013-03-29 00:55:41 +08:00
|
|
|
pp_on |= port_sel;
|
|
|
|
|
|
|
|
I915_WRITE(pp_on_reg, pp_on);
|
|
|
|
I915_WRITE(pp_off_reg, pp_off);
|
|
|
|
I915_WRITE(pp_div_reg, pp_div);
|
2012-10-21 02:57:45 +08:00
|
|
|
|
|
|
|
DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
|
2013-03-29 00:55:41 +08:00
|
|
|
I915_READ(pp_on_reg),
|
|
|
|
I915_READ(pp_off_reg),
|
|
|
|
I915_READ(pp_div_reg));
|
2010-09-19 16:29:33 +08:00
|
|
|
}
|
|
|
|
|
2014-04-05 14:43:28 +08:00
|
|
|
void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
|
|
|
|
{
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct intel_encoder *encoder;
|
|
|
|
struct intel_dp *intel_dp = NULL;
|
|
|
|
struct intel_crtc_config *config = NULL;
|
|
|
|
struct intel_crtc *intel_crtc = NULL;
|
|
|
|
struct intel_connector *intel_connector = dev_priv->drrs.connector;
|
|
|
|
u32 reg, val;
|
|
|
|
enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
|
|
|
|
|
|
|
|
if (refresh_rate <= 0) {
|
|
|
|
DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (intel_connector == NULL) {
|
|
|
|
DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
|
|
|
|
DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
encoder = intel_attached_encoder(&intel_connector->base);
|
|
|
|
intel_dp = enc_to_intel_dp(&encoder->base);
|
|
|
|
intel_crtc = encoder->new_crtc;
|
|
|
|
|
|
|
|
if (!intel_crtc) {
|
|
|
|
DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
config = &intel_crtc->config;
|
|
|
|
|
|
|
|
if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
|
|
|
|
DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
|
|
|
|
index = DRRS_LOW_RR;
|
|
|
|
|
|
|
|
if (index == intel_dp->drrs_state.refresh_rate_type) {
|
|
|
|
DRM_DEBUG_KMS(
|
|
|
|
"DRRS requested for previously set RR...ignoring\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!intel_crtc->active) {
|
|
|
|
DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
|
|
|
|
reg = PIPECONF(intel_crtc->config.cpu_transcoder);
|
|
|
|
val = I915_READ(reg);
|
|
|
|
if (index > DRRS_HIGH_RR) {
|
|
|
|
val |= PIPECONF_EDP_RR_MODE_SWITCH;
|
|
|
|
intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
|
|
|
|
} else {
|
|
|
|
val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
|
|
|
|
}
|
|
|
|
I915_WRITE(reg, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* mutex taken to ensure that there is no race between differnt
|
|
|
|
* drrs calls trying to update refresh rate. This scenario may occur
|
|
|
|
* in future when idleness detection based DRRS in kernel and
|
|
|
|
* possible calls from user space to set differnt RR are made.
|
|
|
|
*/
|
|
|
|
|
|
|
|
mutex_lock(&intel_dp->drrs_state.mutex);
|
|
|
|
|
|
|
|
intel_dp->drrs_state.refresh_rate_type = index;
|
|
|
|
|
|
|
|
mutex_unlock(&intel_dp->drrs_state.mutex);
|
|
|
|
|
|
|
|
DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
|
|
|
|
}
|
|
|
|
|
2014-04-05 14:42:31 +08:00
|
|
|
static struct drm_display_mode *
|
|
|
|
intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
|
|
|
|
struct intel_connector *intel_connector,
|
|
|
|
struct drm_display_mode *fixed_mode)
|
|
|
|
{
|
|
|
|
struct drm_connector *connector = &intel_connector->base;
|
|
|
|
struct intel_dp *intel_dp = &intel_dig_port->dp;
|
|
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct drm_display_mode *downclock_mode = NULL;
|
|
|
|
|
|
|
|
if (INTEL_INFO(dev)->gen <= 6) {
|
|
|
|
DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
|
|
|
|
DRM_INFO("VBT doesn't support DRRS\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
downclock_mode = intel_find_panel_downclock
|
|
|
|
(dev, fixed_mode, connector);
|
|
|
|
|
|
|
|
if (!downclock_mode) {
|
|
|
|
DRM_INFO("DRRS not supported\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2014-04-05 14:43:28 +08:00
|
|
|
dev_priv->drrs.connector = intel_connector;
|
|
|
|
|
|
|
|
mutex_init(&intel_dp->drrs_state.mutex);
|
|
|
|
|
2014-04-05 14:42:31 +08:00
|
|
|
intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
|
|
|
|
|
|
|
|
intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
|
|
|
|
DRM_INFO("seamless DRRS supported for eDP panel.\n");
|
|
|
|
return downclock_mode;
|
|
|
|
}
|
|
|
|
|
2013-06-13 04:27:24 +08:00
|
|
|
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
|
drm/i915: init the DP panel power seq variables earlier
Our driver has two different ways of waiting for panel power
sequencing delays. One of these ways is through
ironlake_wait_panel_status, which implicitly uses the values written
to our registers. The other way is through the functions that call
intel_wait_until_after, and on this case we do direct msleep() calls
on the intel_dp->xxx_delay variables.
Function intel_dp_init_panel_power_sequencer is responsible for
initializing the _delay variables and deciding which values we need to
write to the registers, but it does not write these values to the
registers. Only at intel_dp_init_panel_power_sequencer_registers we
actually do this write.
Then problem is that when we call intel_dp_i2c_init, we will get some
I2C calls, which will trigger a VDD enable, which will make use of the
panel power sequencing registers and the _delay variables, so we need
to have both ready by this time. Today, when this happens, the _delay
variables are zero (because they were not computed) and the panel
power sequence registers contain whatever values were written by the
BIOS (which are usually correct).
What this patch does is to make sure that function
intel_dp_init_panel_power_sequencer is called earlier, so by the time
we call intel_dp_i2c_init, the _delay variables will already be
initialized. The actual registers won't contain their final values,
but at least they will contain the values set by the BIOS.
The good side is that we were reading the values, but were not using
them for anything (because we were just skipping the msleep(0) calls),
so this "fix" shouldn't fix any real existing bugs. I was only able to
identify the problem because I added some debug code to check how much
time time we were saving with my previous patch.
Regression introduced by:
commit ed92f0b239ac971edc509169ae3d6955fbe0a188
Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date: Wed Jun 12 17:27:24 2013 -0300
drm/i915: extract intel_edp_init_connector
v2: - Rewrite commit message.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-12-20 00:29:39 +08:00
|
|
|
struct intel_connector *intel_connector,
|
|
|
|
struct edp_power_seq *power_seq)
|
2013-06-13 04:27:24 +08:00
|
|
|
{
|
|
|
|
struct drm_connector *connector = &intel_connector->base;
|
|
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
2014-04-23 06:55:42 +08:00
|
|
|
struct intel_encoder *intel_encoder = &intel_dig_port->base;
|
|
|
|
struct drm_device *dev = intel_encoder->base.dev;
|
2013-06-13 04:27:24 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
struct drm_display_mode *fixed_mode = NULL;
|
2014-04-05 14:42:31 +08:00
|
|
|
struct drm_display_mode *downclock_mode = NULL;
|
2013-06-13 04:27:24 +08:00
|
|
|
bool has_dpcd;
|
|
|
|
struct drm_display_mode *scan;
|
|
|
|
struct edid *edid;
|
|
|
|
|
2014-04-05 14:42:31 +08:00
|
|
|
intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
|
|
|
|
|
2013-06-13 04:27:24 +08:00
|
|
|
if (!is_edp(intel_dp))
|
|
|
|
return true;
|
|
|
|
|
2014-04-23 06:55:42 +08:00
|
|
|
/* The VDD bit needs a power domain reference, so if the bit is already
|
|
|
|
* enabled when we boot, grab this reference. */
|
|
|
|
if (edp_have_panel_vdd(intel_dp)) {
|
|
|
|
enum intel_display_power_domain power_domain;
|
|
|
|
power_domain = intel_display_port_power_domain(intel_encoder);
|
|
|
|
intel_display_power_get(dev_priv, power_domain);
|
|
|
|
}
|
|
|
|
|
2013-06-13 04:27:24 +08:00
|
|
|
/* Cache DPCD and EDID for edp. */
|
2014-03-17 22:43:36 +08:00
|
|
|
intel_edp_panel_vdd_on(intel_dp);
|
2013-06-13 04:27:24 +08:00
|
|
|
has_dpcd = intel_dp_get_dpcd(intel_dp);
|
2014-01-17 21:39:48 +08:00
|
|
|
edp_panel_vdd_off(intel_dp, false);
|
2013-06-13 04:27:24 +08:00
|
|
|
|
|
|
|
if (has_dpcd) {
|
|
|
|
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
|
|
|
|
dev_priv->no_aux_handshake =
|
|
|
|
intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
|
|
|
|
DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
|
|
|
|
} else {
|
|
|
|
/* if this fails, presume the device is a ghost */
|
|
|
|
DRM_INFO("failed to retrieve link info, disabling eDP\n");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* We now know it's not a ghost, init power sequence regs. */
|
drm/i915: init the DP panel power seq variables earlier
Our driver has two different ways of waiting for panel power
sequencing delays. One of these ways is through
ironlake_wait_panel_status, which implicitly uses the values written
to our registers. The other way is through the functions that call
intel_wait_until_after, and on this case we do direct msleep() calls
on the intel_dp->xxx_delay variables.
Function intel_dp_init_panel_power_sequencer is responsible for
initializing the _delay variables and deciding which values we need to
write to the registers, but it does not write these values to the
registers. Only at intel_dp_init_panel_power_sequencer_registers we
actually do this write.
Then problem is that when we call intel_dp_i2c_init, we will get some
I2C calls, which will trigger a VDD enable, which will make use of the
panel power sequencing registers and the _delay variables, so we need
to have both ready by this time. Today, when this happens, the _delay
variables are zero (because they were not computed) and the panel
power sequence registers contain whatever values were written by the
BIOS (which are usually correct).
What this patch does is to make sure that function
intel_dp_init_panel_power_sequencer is called earlier, so by the time
we call intel_dp_i2c_init, the _delay variables will already be
initialized. The actual registers won't contain their final values,
but at least they will contain the values set by the BIOS.
The good side is that we were reading the values, but were not using
them for anything (because we were just skipping the msleep(0) calls),
so this "fix" shouldn't fix any real existing bugs. I was only able to
identify the problem because I added some debug code to check how much
time time we were saving with my previous patch.
Regression introduced by:
commit ed92f0b239ac971edc509169ae3d6955fbe0a188
Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date: Wed Jun 12 17:27:24 2013 -0300
drm/i915: extract intel_edp_init_connector
v2: - Rewrite commit message.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-12-20 00:29:39 +08:00
|
|
|
intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
|
2013-06-13 04:27:24 +08:00
|
|
|
|
2014-03-22 06:22:35 +08:00
|
|
|
mutex_lock(&dev->mode_config.mutex);
|
2014-03-14 22:51:17 +08:00
|
|
|
edid = drm_get_edid(connector, &intel_dp->aux.ddc);
|
2013-06-13 04:27:24 +08:00
|
|
|
if (edid) {
|
|
|
|
if (drm_add_edid_modes(connector, edid)) {
|
|
|
|
drm_mode_connector_update_edid_property(connector,
|
|
|
|
edid);
|
|
|
|
drm_edid_to_eld(connector, edid);
|
|
|
|
} else {
|
|
|
|
kfree(edid);
|
|
|
|
edid = ERR_PTR(-EINVAL);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
edid = ERR_PTR(-ENOENT);
|
|
|
|
}
|
|
|
|
intel_connector->edid = edid;
|
|
|
|
|
|
|
|
/* prefer fixed mode from EDID if available */
|
|
|
|
list_for_each_entry(scan, &connector->probed_modes, head) {
|
|
|
|
if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
|
|
|
|
fixed_mode = drm_mode_duplicate(dev, scan);
|
2014-04-05 14:42:31 +08:00
|
|
|
downclock_mode = intel_dp_drrs_init(
|
|
|
|
intel_dig_port,
|
|
|
|
intel_connector, fixed_mode);
|
2013-06-13 04:27:24 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* fallback to VBT if available for eDP */
|
|
|
|
if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
|
|
|
|
fixed_mode = drm_mode_duplicate(dev,
|
|
|
|
dev_priv->vbt.lfp_lvds_vbt_mode);
|
|
|
|
if (fixed_mode)
|
|
|
|
fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
|
|
|
|
}
|
2014-03-22 06:22:35 +08:00
|
|
|
mutex_unlock(&dev->mode_config.mutex);
|
2013-06-13 04:27:24 +08:00
|
|
|
|
2014-04-05 14:42:31 +08:00
|
|
|
intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
|
2013-06-13 04:27:24 +08:00
|
|
|
intel_panel_setup_backlight(connector);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-06-13 04:27:25 +08:00
|
|
|
bool
|
2012-10-27 05:05:48 +08:00
|
|
|
intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
|
|
|
|
struct intel_connector *intel_connector)
|
2009-04-08 07:16:42 +08:00
|
|
|
{
|
2012-10-27 05:05:48 +08:00
|
|
|
struct drm_connector *connector = &intel_connector->base;
|
|
|
|
struct intel_dp *intel_dp = &intel_dig_port->dp;
|
|
|
|
struct intel_encoder *intel_encoder = &intel_dig_port->base;
|
|
|
|
struct drm_device *dev = intel_encoder->base.dev;
|
2009-04-08 07:16:42 +08:00
|
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
2012-10-27 05:05:50 +08:00
|
|
|
enum port port = intel_dig_port->port;
|
drm/i915: init the DP panel power seq variables earlier
Our driver has two different ways of waiting for panel power
sequencing delays. One of these ways is through
ironlake_wait_panel_status, which implicitly uses the values written
to our registers. The other way is through the functions that call
intel_wait_until_after, and on this case we do direct msleep() calls
on the intel_dp->xxx_delay variables.
Function intel_dp_init_panel_power_sequencer is responsible for
initializing the _delay variables and deciding which values we need to
write to the registers, but it does not write these values to the
registers. Only at intel_dp_init_panel_power_sequencer_registers we
actually do this write.
Then problem is that when we call intel_dp_i2c_init, we will get some
I2C calls, which will trigger a VDD enable, which will make use of the
panel power sequencing registers and the _delay variables, so we need
to have both ready by this time. Today, when this happens, the _delay
variables are zero (because they were not computed) and the panel
power sequence registers contain whatever values were written by the
BIOS (which are usually correct).
What this patch does is to make sure that function
intel_dp_init_panel_power_sequencer is called earlier, so by the time
we call intel_dp_i2c_init, the _delay variables will already be
initialized. The actual registers won't contain their final values,
but at least they will contain the values set by the BIOS.
The good side is that we were reading the values, but were not using
them for anything (because we were just skipping the msleep(0) calls),
so this "fix" shouldn't fix any real existing bugs. I was only able to
identify the problem because I added some debug code to check how much
time time we were saving with my previous patch.
Regression introduced by:
commit ed92f0b239ac971edc509169ae3d6955fbe0a188
Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date: Wed Jun 12 17:27:24 2013 -0300
drm/i915: extract intel_edp_init_connector
v2: - Rewrite commit message.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-12-20 00:29:39 +08:00
|
|
|
struct edp_power_seq power_seq = { 0 };
|
2014-03-14 22:51:17 +08:00
|
|
|
int type;
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2014-01-21 21:35:39 +08:00
|
|
|
/* intel_dp vfuncs */
|
|
|
|
if (IS_VALLEYVIEW(dev))
|
|
|
|
intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
|
|
|
|
else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
|
|
|
|
intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
|
|
|
|
else if (HAS_PCH_SPLIT(dev))
|
|
|
|
intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
|
|
|
|
else
|
|
|
|
intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
|
|
|
|
|
2014-01-21 21:37:15 +08:00
|
|
|
intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
|
|
|
|
|
2012-09-07 04:15:42 +08:00
|
|
|
/* Preserve the current hw state. */
|
|
|
|
intel_dp->DP = I915_READ(intel_dp->output_reg);
|
2012-10-19 19:51:50 +08:00
|
|
|
intel_dp->attached_connector = intel_connector;
|
2011-02-12 18:33:12 +08:00
|
|
|
|
2013-11-02 00:22:41 +08:00
|
|
|
if (intel_dp_is_edp(dev, port))
|
2010-07-17 02:46:28 +08:00
|
|
|
type = DRM_MODE_CONNECTOR_eDP;
|
2013-11-02 00:22:41 +08:00
|
|
|
else
|
|
|
|
type = DRM_MODE_CONNECTOR_DisplayPort;
|
2010-07-17 02:46:28 +08:00
|
|
|
|
2013-05-08 18:14:05 +08:00
|
|
|
/*
|
|
|
|
* For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
|
|
|
|
* for DP the encoder type can be set by the caller to
|
|
|
|
* INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
|
|
|
|
*/
|
|
|
|
if (type == DRM_MODE_CONNECTOR_eDP)
|
|
|
|
intel_encoder->type = INTEL_OUTPUT_EDP;
|
|
|
|
|
2013-05-08 18:14:08 +08:00
|
|
|
DRM_DEBUG_KMS("Adding %s connector on port %c\n",
|
|
|
|
type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
|
|
|
|
port_name(port));
|
|
|
|
|
2010-07-17 02:46:28 +08:00
|
|
|
drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
|
2009-04-08 07:16:42 +08:00
|
|
|
drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
|
|
|
|
|
|
|
|
connector->interlace_allowed = true;
|
|
|
|
connector->doublescan_allowed = 0;
|
|
|
|
|
2012-10-27 05:05:48 +08:00
|
|
|
INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
|
2014-01-17 21:39:48 +08:00
|
|
|
edp_panel_vdd_work);
|
2009-04-08 07:16:42 +08:00
|
|
|
|
2010-09-09 23:20:55 +08:00
|
|
|
intel_connector_attach_encoder(intel_connector, intel_encoder);
|
2009-04-08 07:16:42 +08:00
|
|
|
drm_sysfs_connector_add(connector);
|
|
|
|
|
2012-11-24 01:30:39 +08:00
|
|
|
if (HAS_DDI(dev))
|
2012-10-27 05:05:51 +08:00
|
|
|
intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
|
|
|
|
else
|
|
|
|
intel_connector->get_hw_state = intel_connector_get_hw_state;
|
2014-02-11 23:12:49 +08:00
|
|
|
intel_connector->unregister = intel_dp_connector_unregister;
|
2012-10-27 05:05:51 +08:00
|
|
|
|
2014-03-14 22:51:17 +08:00
|
|
|
/* Set up the hotplug pin. */
|
2012-07-18 04:53:45 +08:00
|
|
|
switch (port) {
|
|
|
|
case PORT_A:
|
2013-02-26 01:06:49 +08:00
|
|
|
intel_encoder->hpd_pin = HPD_PORT_A;
|
2012-07-18 04:53:45 +08:00
|
|
|
break;
|
|
|
|
case PORT_B:
|
2013-02-26 01:06:49 +08:00
|
|
|
intel_encoder->hpd_pin = HPD_PORT_B;
|
2012-07-18 04:53:45 +08:00
|
|
|
break;
|
|
|
|
case PORT_C:
|
2013-02-26 01:06:49 +08:00
|
|
|
intel_encoder->hpd_pin = HPD_PORT_C;
|
2012-07-18 04:53:45 +08:00
|
|
|
break;
|
|
|
|
case PORT_D:
|
2013-02-26 01:06:49 +08:00
|
|
|
intel_encoder->hpd_pin = HPD_PORT_D;
|
2012-07-18 04:53:45 +08:00
|
|
|
break;
|
|
|
|
default:
|
2013-03-07 23:30:28 +08:00
|
|
|
BUG();
|
2009-07-24 01:00:31 +08:00
|
|
|
}
|
|
|
|
|
2014-01-29 19:25:41 +08:00
|
|
|
if (is_edp(intel_dp)) {
|
|
|
|
intel_dp_init_panel_power_timestamps(intel_dp);
|
drm/i915: init the DP panel power seq variables earlier
Our driver has two different ways of waiting for panel power
sequencing delays. One of these ways is through
ironlake_wait_panel_status, which implicitly uses the values written
to our registers. The other way is through the functions that call
intel_wait_until_after, and on this case we do direct msleep() calls
on the intel_dp->xxx_delay variables.
Function intel_dp_init_panel_power_sequencer is responsible for
initializing the _delay variables and deciding which values we need to
write to the registers, but it does not write these values to the
registers. Only at intel_dp_init_panel_power_sequencer_registers we
actually do this write.
Then problem is that when we call intel_dp_i2c_init, we will get some
I2C calls, which will trigger a VDD enable, which will make use of the
panel power sequencing registers and the _delay variables, so we need
to have both ready by this time. Today, when this happens, the _delay
variables are zero (because they were not computed) and the panel
power sequence registers contain whatever values were written by the
BIOS (which are usually correct).
What this patch does is to make sure that function
intel_dp_init_panel_power_sequencer is called earlier, so by the time
we call intel_dp_i2c_init, the _delay variables will already be
initialized. The actual registers won't contain their final values,
but at least they will contain the values set by the BIOS.
The good side is that we were reading the values, but were not using
them for anything (because we were just skipping the msleep(0) calls),
so this "fix" shouldn't fix any real existing bugs. I was only able to
identify the problem because I added some debug code to check how much
time time we were saving with my previous patch.
Regression introduced by:
commit ed92f0b239ac971edc509169ae3d6955fbe0a188
Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date: Wed Jun 12 17:27:24 2013 -0300
drm/i915: extract intel_edp_init_connector
v2: - Rewrite commit message.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-12-20 00:29:39 +08:00
|
|
|
intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
|
2014-01-29 19:25:41 +08:00
|
|
|
}
|
drm/i915: init the DP panel power seq variables earlier
Our driver has two different ways of waiting for panel power
sequencing delays. One of these ways is through
ironlake_wait_panel_status, which implicitly uses the values written
to our registers. The other way is through the functions that call
intel_wait_until_after, and on this case we do direct msleep() calls
on the intel_dp->xxx_delay variables.
Function intel_dp_init_panel_power_sequencer is responsible for
initializing the _delay variables and deciding which values we need to
write to the registers, but it does not write these values to the
registers. Only at intel_dp_init_panel_power_sequencer_registers we
actually do this write.
Then problem is that when we call intel_dp_i2c_init, we will get some
I2C calls, which will trigger a VDD enable, which will make use of the
panel power sequencing registers and the _delay variables, so we need
to have both ready by this time. Today, when this happens, the _delay
variables are zero (because they were not computed) and the panel
power sequence registers contain whatever values were written by the
BIOS (which are usually correct).
What this patch does is to make sure that function
intel_dp_init_panel_power_sequencer is called earlier, so by the time
we call intel_dp_i2c_init, the _delay variables will already be
initialized. The actual registers won't contain their final values,
but at least they will contain the values set by the BIOS.
The good side is that we were reading the values, but were not using
them for anything (because we were just skipping the msleep(0) calls),
so this "fix" shouldn't fix any real existing bugs. I was only able to
identify the problem because I added some debug code to check how much
time time we were saving with my previous patch.
Regression introduced by:
commit ed92f0b239ac971edc509169ae3d6955fbe0a188
Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date: Wed Jun 12 17:27:24 2013 -0300
drm/i915: extract intel_edp_init_connector
v2: - Rewrite commit message.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-12-20 00:29:39 +08:00
|
|
|
|
2014-03-14 22:51:15 +08:00
|
|
|
intel_dp_aux_init(intel_dp, intel_connector);
|
2012-08-30 09:06:18 +08:00
|
|
|
|
drm/i915: init the DP panel power seq variables earlier
Our driver has two different ways of waiting for panel power
sequencing delays. One of these ways is through
ironlake_wait_panel_status, which implicitly uses the values written
to our registers. The other way is through the functions that call
intel_wait_until_after, and on this case we do direct msleep() calls
on the intel_dp->xxx_delay variables.
Function intel_dp_init_panel_power_sequencer is responsible for
initializing the _delay variables and deciding which values we need to
write to the registers, but it does not write these values to the
registers. Only at intel_dp_init_panel_power_sequencer_registers we
actually do this write.
Then problem is that when we call intel_dp_i2c_init, we will get some
I2C calls, which will trigger a VDD enable, which will make use of the
panel power sequencing registers and the _delay variables, so we need
to have both ready by this time. Today, when this happens, the _delay
variables are zero (because they were not computed) and the panel
power sequence registers contain whatever values were written by the
BIOS (which are usually correct).
What this patch does is to make sure that function
intel_dp_init_panel_power_sequencer is called earlier, so by the time
we call intel_dp_i2c_init, the _delay variables will already be
initialized. The actual registers won't contain their final values,
but at least they will contain the values set by the BIOS.
The good side is that we were reading the values, but were not using
them for anything (because we were just skipping the msleep(0) calls),
so this "fix" shouldn't fix any real existing bugs. I was only able to
identify the problem because I added some debug code to check how much
time time we were saving with my previous patch.
Regression introduced by:
commit ed92f0b239ac971edc509169ae3d6955fbe0a188
Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date: Wed Jun 12 17:27:24 2013 -0300
drm/i915: extract intel_edp_init_connector
v2: - Rewrite commit message.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-12-20 00:29:39 +08:00
|
|
|
if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
|
2014-06-04 14:02:28 +08:00
|
|
|
drm_dp_aux_unregister(&intel_dp->aux);
|
2013-06-13 04:27:27 +08:00
|
|
|
if (is_edp(intel_dp)) {
|
|
|
|
cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
|
2013-11-20 01:10:12 +08:00
|
|
|
drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
|
2014-01-17 21:39:48 +08:00
|
|
|
edp_panel_vdd_off_sync(intel_dp);
|
2013-11-20 01:10:12 +08:00
|
|
|
drm_modeset_unlock(&dev->mode_config.connection_mutex);
|
2013-06-13 04:27:27 +08:00
|
|
|
}
|
2013-06-13 04:27:26 +08:00
|
|
|
drm_sysfs_connector_remove(connector);
|
|
|
|
drm_connector_cleanup(connector);
|
2013-06-13 04:27:25 +08:00
|
|
|
return false;
|
2013-06-13 04:27:26 +08:00
|
|
|
}
|
2009-07-24 01:00:32 +08:00
|
|
|
|
2010-09-19 16:29:33 +08:00
|
|
|
intel_dp_add_properties(intel_dp, connector);
|
|
|
|
|
2009-04-08 07:16:42 +08:00
|
|
|
/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
|
|
|
|
* 0xd. Failure to do so will result in spurious interrupts being
|
|
|
|
* generated on the port when a cable is not attached.
|
|
|
|
*/
|
|
|
|
if (IS_G4X(dev) && !IS_GM45(dev)) {
|
|
|
|
u32 temp = I915_READ(PEG_BAND_GAP_DATA);
|
|
|
|
I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
|
|
|
|
}
|
2013-06-13 04:27:25 +08:00
|
|
|
|
|
|
|
return true;
|
2009-04-08 07:16:42 +08:00
|
|
|
}
|
2012-10-27 05:05:48 +08:00
|
|
|
|
|
|
|
void
|
|
|
|
intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
|
|
|
|
{
|
|
|
|
struct intel_digital_port *intel_dig_port;
|
|
|
|
struct intel_encoder *intel_encoder;
|
|
|
|
struct drm_encoder *encoder;
|
|
|
|
struct intel_connector *intel_connector;
|
|
|
|
|
2013-09-19 18:18:32 +08:00
|
|
|
intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
|
2012-10-27 05:05:48 +08:00
|
|
|
if (!intel_dig_port)
|
|
|
|
return;
|
|
|
|
|
2013-09-19 18:18:32 +08:00
|
|
|
intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
|
2012-10-27 05:05:48 +08:00
|
|
|
if (!intel_connector) {
|
|
|
|
kfree(intel_dig_port);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
intel_encoder = &intel_dig_port->base;
|
|
|
|
encoder = &intel_encoder->base;
|
|
|
|
|
|
|
|
drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
|
|
|
|
DRM_MODE_ENCODER_TMDS);
|
|
|
|
|
2013-03-27 07:44:55 +08:00
|
|
|
intel_encoder->compute_config = intel_dp_compute_config;
|
2012-10-27 05:05:52 +08:00
|
|
|
intel_encoder->disable = intel_disable_dp;
|
|
|
|
intel_encoder->get_hw_state = intel_dp_get_hw_state;
|
2013-05-15 08:08:26 +08:00
|
|
|
intel_encoder->get_config = intel_dp_get_config;
|
2014-04-09 18:28:20 +08:00
|
|
|
if (IS_CHERRYVIEW(dev)) {
|
2014-04-09 18:29:05 +08:00
|
|
|
intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
|
2014-04-09 18:28:20 +08:00
|
|
|
intel_encoder->pre_enable = chv_pre_enable_dp;
|
|
|
|
intel_encoder->enable = vlv_enable_dp;
|
2014-04-09 18:29:00 +08:00
|
|
|
intel_encoder->post_disable = chv_post_disable_dp;
|
2014-04-09 18:28:20 +08:00
|
|
|
} else if (IS_VALLEYVIEW(dev)) {
|
2013-09-06 12:38:29 +08:00
|
|
|
intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
|
2013-07-30 17:20:30 +08:00
|
|
|
intel_encoder->pre_enable = vlv_pre_enable_dp;
|
|
|
|
intel_encoder->enable = vlv_enable_dp;
|
2014-03-31 23:21:26 +08:00
|
|
|
intel_encoder->post_disable = vlv_post_disable_dp;
|
2013-07-30 17:20:30 +08:00
|
|
|
} else {
|
2013-09-06 12:38:29 +08:00
|
|
|
intel_encoder->pre_enable = g4x_pre_enable_dp;
|
|
|
|
intel_encoder->enable = g4x_enable_dp;
|
2014-03-31 23:21:26 +08:00
|
|
|
intel_encoder->post_disable = g4x_post_disable_dp;
|
2013-07-30 17:20:30 +08:00
|
|
|
}
|
2012-10-27 05:05:48 +08:00
|
|
|
|
2012-10-27 05:05:50 +08:00
|
|
|
intel_dig_port->port = port;
|
2012-10-27 05:05:48 +08:00
|
|
|
intel_dig_port->dp.output_reg = output_reg;
|
|
|
|
|
2012-10-27 05:05:52 +08:00
|
|
|
intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
|
2014-04-28 19:07:43 +08:00
|
|
|
if (IS_CHERRYVIEW(dev)) {
|
|
|
|
if (port == PORT_D)
|
|
|
|
intel_encoder->crtc_mask = 1 << 2;
|
|
|
|
else
|
|
|
|
intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
|
|
|
|
} else {
|
|
|
|
intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
|
|
|
|
}
|
2014-03-03 22:15:28 +08:00
|
|
|
intel_encoder->cloneable = 0;
|
2012-10-27 05:05:48 +08:00
|
|
|
intel_encoder->hot_plug = intel_dp_hot_plug;
|
|
|
|
|
2013-06-13 04:27:27 +08:00
|
|
|
if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
|
|
|
|
drm_encoder_cleanup(encoder);
|
|
|
|
kfree(intel_dig_port);
|
2013-06-13 04:27:26 +08:00
|
|
|
kfree(intel_connector);
|
2013-06-13 04:27:27 +08:00
|
|
|
}
|
2012-10-27 05:05:48 +08:00
|
|
|
}
|